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gerrit.nordix.org / codeaurora / quic / qsdk / oss / boot / u-boot-2016 / 5da6f806b400372b8a0664f3282c9e83a402eb66 / . / include / ppc440.h
blob: 01f6eaf35e6bfb8f4d757ac481af38610b93e628 [file] [log] [blame]
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1/*----------------------------------------------------------------------------+
2|
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]3| This source code has been made available to you by IBM on an AS-IS
4| basis. Anyone receiving this source is licensed under IBM
5| copyrights to use it in any way he or she deems fit, including
6| copying it, modifying it, compiling it, and redistributing it either
7| with or without modifications. No license under IBM patents or
8| patent applications is to be implied by the copyright license.
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]9|
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]10| Any user of this software should understand that IBM cannot provide
11| technical support for this software and will not be responsible for
12| any consequences resulting from the use of this software.
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]13|
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]14| Any person who transfers this source code or any derivative work
15| must include the IBM copyright notice, this paragraph, and the
16| preceding two paragraphs in the transferred software.
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]17|
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]18| COPYRIGHT I B M CORPORATION 1999
19| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]20+----------------------------------------------------------------------------*/
21
Larry Johnsonc46f5332007-12-22 15:15:13 -0500[diff] [blame]22/*
23 * (C) Copyright 2006
24 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
25 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
26 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
27 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
28 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
29 *
30 * This program is free software; you can redistribute it and/or
31 * modify it under the terms of the GNU General Public License as
32 * published by the Free Software Foundation; either version 2 of
33 * the License, or (at your option) any later version.
34 *
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
39 *
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
43 * MA 02111-1307 USA
44 */
45
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]46#ifndef __PPC440_H__
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]47#define __PPC440_H__
48
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]49#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
Stefan Roese9b94ac62007-10-31 17:55:58 +0100[diff] [blame]50
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]51/*--------------------------------------------------------------------- */
52/* Special Purpose Registers */
53/*--------------------------------------------------------------------- */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]54#define xer_reg 0x001
55#define lr_reg 0x008
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]56#define dec 0x016 /* decrementer */
57#define srr0 0x01a /* save/restore register 0 */
58#define srr1 0x01b /* save/restore register 1 */
59#define pid 0x030 /* process id */
60#define decar 0x036 /* decrementer auto-reload */
61#define csrr0 0x03a /* critical save/restore register 0 */
62#define csrr1 0x03b /* critical save/restore register 1 */
63#define dear 0x03d /* data exception address register */
64#define esr 0x03e /* exception syndrome register */
65#define ivpr 0x03f /* interrupt prefix register */
66#define usprg0 0x100 /* user special purpose register general 0 */
67#define usprg1 0x110 /* user special purpose register general 1 */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]68#define tblr 0x10c /* time base lower, read only */
69#define tbur 0x10d /* time base upper, read only */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]70#define sprg1 0x111 /* special purpose register general 1 */
71#define sprg2 0x112 /* special purpose register general 2 */
72#define sprg3 0x113 /* special purpose register general 3 */
73#define sprg4 0x114 /* special purpose register general 4 */
74#define sprg5 0x115 /* special purpose register general 5 */
75#define sprg6 0x116 /* special purpose register general 6 */
76#define sprg7 0x117 /* special purpose register general 7 */
77#define tbl 0x11c /* time base lower (supervisor)*/
78#define tbu 0x11d /* time base upper (supervisor)*/
79#define pir 0x11e /* processor id register */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]80#define dbsr 0x130 /* debug status register */
81#define dbcr0 0x134 /* debug control register 0 */
82#define dbcr1 0x135 /* debug control register 1 */
83#define dbcr2 0x136 /* debug control register 2 */
84#define iac1 0x138 /* instruction address compare 1 */
85#define iac2 0x139 /* instruction address compare 2 */
86#define iac3 0x13a /* instruction address compare 3 */
87#define iac4 0x13b /* instruction address compare 4 */
88#define dac1 0x13c /* data address compare 1 */
89#define dac2 0x13d /* data address compare 2 */
90#define dvc1 0x13e /* data value compare 1 */
91#define dvc2 0x13f /* data value compare 2 */
92#define tsr 0x150 /* timer status register */
93#define tcr 0x154 /* timer control register */
94#define ivor0 0x190 /* interrupt vector offset register 0 */
95#define ivor1 0x191 /* interrupt vector offset register 1 */
96#define ivor2 0x192 /* interrupt vector offset register 2 */
97#define ivor3 0x193 /* interrupt vector offset register 3 */
98#define ivor4 0x194 /* interrupt vector offset register 4 */
99#define ivor5 0x195 /* interrupt vector offset register 5 */
100#define ivor6 0x196 /* interrupt vector offset register 6 */
101#define ivor7 0x197 /* interrupt vector offset register 7 */
102#define ivor8 0x198 /* interrupt vector offset register 8 */
103#define ivor9 0x199 /* interrupt vector offset register 9 */
104#define ivor10 0x19a /* interrupt vector offset register 10 */
105#define ivor11 0x19b /* interrupt vector offset register 11 */
106#define ivor12 0x19c /* interrupt vector offset register 12 */
107#define ivor13 0x19d /* interrupt vector offset register 13 */
108#define ivor14 0x19e /* interrupt vector offset register 14 */
109#define ivor15 0x19f /* interrupt vector offset register 15 */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200[diff] [blame]110#if defined(CONFIG_440)
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]111#define mcsrr0 0x23a /* machine check save/restore register 0 */
112#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
113#define mcsr 0x23c /* machine check status register */
114#endif
115#define inv0 0x370 /* instruction cache normal victim 0 */
116#define inv1 0x371 /* instruction cache normal victim 1 */
117#define inv2 0x372 /* instruction cache normal victim 2 */
118#define inv3 0x373 /* instruction cache normal victim 3 */
119#define itv0 0x374 /* instruction cache transient victim 0 */
120#define itv1 0x375 /* instruction cache transient victim 1 */
121#define itv2 0x376 /* instruction cache transient victim 2 */
122#define itv3 0x377 /* instruction cache transient victim 3 */
123#define dnv0 0x390 /* data cache normal victim 0 */
124#define dnv1 0x391 /* data cache normal victim 1 */
125#define dnv2 0x392 /* data cache normal victim 2 */
126#define dnv3 0x393 /* data cache normal victim 3 */
127#define dtv0 0x394 /* data cache transient victim 0 */
128#define dtv1 0x395 /* data cache transient victim 1 */
129#define dtv2 0x396 /* data cache transient victim 2 */
130#define dtv3 0x397 /* data cache transient victim 3 */
131#define dvlim 0x398 /* data cache victim limit */
132#define ivlim 0x399 /* instruction cache victim limit */
133#define rstcfg 0x39b /* reset configuration */
134#define dcdbtrl 0x39c /* data cache debug tag register low */
135#define dcdbtrh 0x39d /* data cache debug tag register high */
136#define icdbtrl 0x39e /* instruction cache debug tag register low */
137#define icdbtrh 0x39f /* instruction cache debug tag register high */
138#define mmucr 0x3b2 /* mmu control register */
139#define ccr0 0x3b3 /* core configuration register 0 */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200[diff] [blame]140#define ccr1 0x378 /* core configuration for 440x5 only */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]141#define icdbdr 0x3d3 /* instruction cache debug data register */
142#define dbdr 0x3f3 /* debug data register */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]143
144/******************************************************************************
145 * DCRs & Related
146 ******************************************************************************/
147
148/*-----------------------------------------------------------------------------
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]149 | Clocking Controller
150 +----------------------------------------------------------------------------*/
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]151/* values for clkcfga register - indirect addressing of these regs */
152#define clk_clkukpd 0x0020
153#define clk_pllc 0x0040
154#define clk_plld 0x0060
155#define clk_primad 0x0080
156#define clk_primbd 0x00a0
157#define clk_opbd 0x00c0
158#define clk_perd 0x00e0
159#define clk_mald 0x0100
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200[diff] [blame]160#define clk_spcid 0x0120
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]161#define clk_icfg 0x0140
162
163/* 440gx sdr register definations */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]164#define sdr_sdstp0 0x0020 /* */
165#define sdr_sdstp1 0x0021 /* */
Stefan Roese90e6f412007-04-18 12:05:59 +0200[diff] [blame]166#define SDR_PINSTP 0x0040
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]167#define sdr_sdcs 0x0060
168#define sdr_ecid0 0x0080
169#define sdr_ecid1 0x0081
170#define sdr_ecid2 0x0082
171#define sdr_jtag 0x00c0
Steven A. Falco711e2b22008-11-20 14:37:57 -0500[diff] [blame]172#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
173#define SDR0_DDRCFG 0x00e0
174#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]175#define sdr_ebc 0x0100
176#define sdr_uart0 0x0120 /* UART0 Config */
177#define sdr_uart1 0x0121 /* UART1 Config */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]178#define sdr_uart2 0x0122 /* UART2 Config */
179#define sdr_uart3 0x0123 /* UART3 Config */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]180#define sdr_cp440 0x0180
181#define sdr_xcr 0x01c0
182#define sdr_xpllc 0x01c1
183#define sdr_xplld 0x01c2
184#define sdr_srst 0x0200
185#define sdr_slpipe 0x0220
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]186#define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
187#define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]188#define sdr_mirq0 0x0260
189#define sdr_mirq1 0x0261
190#define sdr_maltbl 0x0280
191#define sdr_malrbl 0x02a0
192#define sdr_maltbs 0x02c0
193#define sdr_malrbs 0x02e0
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]194#define sdr_pci0 0x0300
195#define sdr_usb0 0x0320
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]196#define sdr_cust0 0x4000
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]197#define sdr_cust1 0x4002
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]198#define sdr_pfc0 0x4100 /* Pin Function 0 */
199#define sdr_pfc1 0x4101 /* Pin Function 1 */
200#define sdr_plbtr 0x4200
201#define sdr_mfr 0x4300 /* SDR0_MFR reg */
202
Marian Balakowiczbba68372006-06-30 18:35:04 +0200[diff] [blame]203#ifdef CONFIG_440GX
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]204#define sdr_amp 0x0240
205#define sdr_xpllc 0x01c1
206#define sdr_xplld 0x01c2
207#define sdr_xcr 0x01c0
208#define sdr_sdstp2 0x4001
209#define sdr_sdstp3 0x4003
Marian Balakowiczbba68372006-06-30 18:35:04 +0200[diff] [blame]210#endif /* CONFIG_440GX */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]211
Igor Lisitsina11e0692007-03-28 19:06:19 +0400[diff] [blame]212/*----------------------------------------------------------------------------+
213| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
214+----------------------------------------------------------------------------*/
215#define CCR0_PRE 0x40000000
216#define CCR0_CRPE 0x08000000
217#define CCR0_DSTG 0x00200000
218#define CCR0_DAPUIB 0x00100000
219#define CCR0_DTB 0x00008000
220#define CCR0_GICBT 0x00004000
221#define CCR0_GDCBT 0x00002000
222#define CCR0_FLSTA 0x00000100
223#define CCR0_ICSLC_MASK 0x0000000C
224#define CCR0_ICSLT_MASK 0x00000003
225#define CCR1_TCS_MASK 0x00000080
226#define CCR1_TCS_INTCLK 0x00000000
227#define CCR1_TCS_EXTCLK 0x00000080
228#define MMUCR_SWOA 0x01000000
229#define MMUCR_U1TE 0x00400000
230#define MMUCR_U2SWOAE 0x00200000
231#define MMUCR_DULXE 0x00800000
232#define MMUCR_IULXE 0x00400000
233#define MMUCR_STS 0x00100000
234#define MMUCR_STID_MASK 0x000000FF
Igor Lisitsina11e0692007-03-28 19:06:19 +0400[diff] [blame]235
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]236#ifdef CONFIG_440SPE
237#undef sdr_sdstp2
238#define sdr_sdstp2 0x0022
239#undef sdr_sdstp3
240#define sdr_sdstp3 0x0023
241#define sdr_ddr0 0x00E1
242#define sdr_uart2 0x0122
243#define sdr_xcr0 0x01c0
244/* #define sdr_xcr1 0x01c3 only one PCIX - SG */
245/* #define sdr_xcr2 0x01c6 only one PCIX - SG */
246#define sdr_xpllc0 0x01c1
247#define sdr_xplld0 0x01c2
248#define sdr_xpllc1 0x01c4 /*notRCW - SG */
249#define sdr_xplld1 0x01c5 /*notRCW - SG */
250#define sdr_xpllc2 0x01c7 /*notRCW - SG */
251#define sdr_xplld2 0x01c8 /*notRCW - SG */
252#define sdr_amp0 0x0240
253#define sdr_amp1 0x0241
254#define sdr_cust2 0x4004
255#define sdr_cust3 0x4006
256#define sdr_sdstp4 0x4001
257#define sdr_sdstp5 0x4003
258#define sdr_sdstp6 0x4005
259#define sdr_sdstp7 0x4007
260
Stefan Roesedf294492007-03-08 10:06:09 +0100[diff] [blame]261#endif /* CONFIG_440SPE */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]262
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]263/*-----------------------------------------------------------------------------
Wolfgang Denk6ed6ce62005-09-25 16:01:42 +0200[diff] [blame]264 | External Bus Controller
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]265 +----------------------------------------------------------------------------*/
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]266/* values for ebccfga register - indirect addressing of these regs */
267#define pb0cr 0x00 /* periph bank 0 config reg */
268#define pb1cr 0x01 /* periph bank 1 config reg */
269#define pb2cr 0x02 /* periph bank 2 config reg */
270#define pb3cr 0x03 /* periph bank 3 config reg */
271#define pb4cr 0x04 /* periph bank 4 config reg */
272#define pb5cr 0x05 /* periph bank 5 config reg */
273#define pb6cr 0x06 /* periph bank 6 config reg */
274#define pb7cr 0x07 /* periph bank 7 config reg */
275#define pb0ap 0x10 /* periph bank 0 access parameters */
276#define pb1ap 0x11 /* periph bank 1 access parameters */
277#define pb2ap 0x12 /* periph bank 2 access parameters */
278#define pb3ap 0x13 /* periph bank 3 access parameters */
279#define pb4ap 0x14 /* periph bank 4 access parameters */
280#define pb5ap 0x15 /* periph bank 5 access parameters */
281#define pb6ap 0x16 /* periph bank 6 access parameters */
282#define pb7ap 0x17 /* periph bank 7 access parameters */
283#define pbear 0x20 /* periph bus error addr reg */
284#define pbesr 0x21 /* periph bus error status reg */
285#define xbcfg 0x23 /* external bus configuration reg */
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]286#define EBC0_CFG 0x23 /* external bus configuration reg */
Wolfgang Denk6ed6ce62005-09-25 16:01:42 +0200[diff] [blame]287#define xbcid 0x24 /* external bus core id reg */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]288
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]289#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
290 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]291
292/* PLB4 to PLB3 Bridge OUT */
293#define P4P3_DCR_BASE 0x020
294#define p4p3_esr0_read (P4P3_DCR_BASE+0x0)
295#define p4p3_esr0_write (P4P3_DCR_BASE+0x1)
296#define p4p3_eadr (P4P3_DCR_BASE+0x2)
297#define p4p3_euadr (P4P3_DCR_BASE+0x3)
298#define p4p3_esr1_read (P4P3_DCR_BASE+0x4)
299#define p4p3_esr1_write (P4P3_DCR_BASE+0x5)
300#define p4p3_confg (P4P3_DCR_BASE+0x6)
301#define p4p3_pic (P4P3_DCR_BASE+0x7)
302#define p4p3_peir (P4P3_DCR_BASE+0x8)
303#define p4p3_rev (P4P3_DCR_BASE+0xA)
304
305/* PLB3 to PLB4 Bridge IN */
306#define P3P4_DCR_BASE 0x030
307#define p3p4_esr0_read (P3P4_DCR_BASE+0x0)
308#define p3p4_esr0_write (P3P4_DCR_BASE+0x1)
309#define p3p4_eadr (P3P4_DCR_BASE+0x2)
310#define p3p4_euadr (P3P4_DCR_BASE+0x3)
311#define p3p4_esr1_read (P3P4_DCR_BASE+0x4)
312#define p3p4_esr1_write (P3P4_DCR_BASE+0x5)
313#define p3p4_confg (P3P4_DCR_BASE+0x6)
314#define p3p4_pic (P3P4_DCR_BASE+0x7)
315#define p3p4_peir (P3P4_DCR_BASE+0x8)
316#define p3p4_rev (P3P4_DCR_BASE+0xA)
317
318/* PLB3 Arbiter */
319#define PLB3_DCR_BASE 0x070
320#define plb3_revid (PLB3_DCR_BASE+0x2)
321#define plb3_besr (PLB3_DCR_BASE+0x3)
322#define plb3_bear (PLB3_DCR_BASE+0x6)
323#define plb3_acr (PLB3_DCR_BASE+0x7)
324
325/* PLB4 Arbiter - PowerPC440EP Pass1 */
326#define PLB4_DCR_BASE 0x080
Stefan Roesea78bc442007-01-05 10:40:36 +0100[diff] [blame]327#define plb4_acr (PLB4_DCR_BASE+0x1)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]328#define plb4_revid (PLB4_DCR_BASE+0x2)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]329#define plb4_besr (PLB4_DCR_BASE+0x4)
330#define plb4_bearl (PLB4_DCR_BASE+0x6)
331#define plb4_bearh (PLB4_DCR_BASE+0x7)
332
Stefan Roesea78bc442007-01-05 10:40:36 +0100[diff] [blame]333#define PLB4_ACR_WRP (0x80000000 >> 7)
334
Stefan Roese17f50f22005-08-04 17:09:16 +0200[diff] [blame]335/* Pin Function Control Register 1 */
336#define SDR0_PFC1 0x4101
337#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
338#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
339#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
340#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
341#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
342#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
343#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
344#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
345#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
346#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
347#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
348#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
349#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
350#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
351#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
352#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
353#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
354#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
355#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
356#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
357#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
358#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
359#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
360#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
361
362#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
363#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
364#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
365#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
366
367/* USB Control Register */
368#define SDR0_USB0 0x0320
369#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
370#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
371#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
372#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
373#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
374#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
375
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]376/* Miscealleneaous Function Reg. */
377#define SDR0_MFR 0x4300
378#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
379#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
380#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
381#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
382#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
383#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
384#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
385#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
386#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
387#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
388#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
389#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
390#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
391
392#define SDR0_MFR_ERRATA3_EN0 0x00800000
393#define SDR0_MFR_ERRATA3_EN1 0x00400000
394#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
395#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
396#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
397#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
398#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
399
Stefan Roese8f24e062008-01-09 10:28:20 +0100[diff] [blame]400#define GPT0_COMP6 0x00000098
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100[diff] [blame]401#define GPT0_COMP5 0x00000094
402#define GPT0_COMP4 0x00000090
403#define GPT0_COMP3 0x0000008C
Yuri Tikhonov3d610182008-02-06 18:48:36 +0100[diff] [blame]404#define GPT0_COMP2 0x00000088
405#define GPT0_COMP1 0x00000084
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]406
Yuri Tikhonoveb0615b2008-04-24 10:30:53 +0200[diff] [blame]407#define GPT0_MASK6 0x000000D8
408#define GPT0_MASK5 0x000000D4
409#define GPT0_MASK4 0x000000D0
410#define GPT0_MASK3 0x000000CC
411#define GPT0_MASK2 0x000000C8
412#define GPT0_MASK1 0x000000C4
413
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]414#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Niklaus Gigerf780b832007-06-27 18:11:38 +0200[diff] [blame]415#define SDR0_USB2D0CR 0x0320
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]416#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
417#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
418#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
419
420#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
421#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
422#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
423
424#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
425#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
426#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
427
428/* USB2 Host Control Register */
429#define SDR0_USB2H0CR 0x0340
430#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
431#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
432#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
433#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
434
435/* Pin Function Control Register 1 */
436#define SDR0_PFC1 0x4101
437#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
438#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
439#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
440
441#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
442#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
443#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
444#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
445#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
446#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
447#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
448#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
449
450#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
451#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
452#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
453#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
454#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
455#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
456#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
457#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
458#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
459#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
460#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
461#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
462#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
463#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
464#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
465#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
466#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
467#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
468#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
469#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
470#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
471
472#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
473#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
474#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
475#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
476
477/* Ethernet PLL Configuration Register */
478#define SDR0_PFC2 0x4102
479#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
480#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
481#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
482#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
483
484#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
485#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
486#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
487#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
488#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
489#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
490#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
491#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
492
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200[diff] [blame]493#define SDR0_PFC4 0x4104
494
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]495/* USB2PHY0 Control Register */
496#define SDR0_USB2PHY0CR 0x4103
497#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
498#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
499#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
500
501#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
502#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
503#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
504
505#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
506#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
507#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
508
509#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
510#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
511#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
512
513#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
514#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
515#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
516
517#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
518#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
519#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
520
521#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
522#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
523#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
524
525#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
526#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
527#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
528
529#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
530#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
531#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
532
533#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
534#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
535#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
536#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
537
538/* Miscealleneaous Function Reg. */
539#define SDR0_MFR 0x4300
540#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
541#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
542#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
543#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
544#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
545#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
546#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
547#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
548#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
549#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
550#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
551
552#define SDR0_MFR_ERRATA3_EN0 0x00800000
553#define SDR0_MFR_ERRATA3_EN1 0x00400000
554#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
555#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
556#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
557#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
558#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
559
560#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
561
Stefan Roese17f50f22005-08-04 17:09:16 +0200[diff] [blame]562/* CUST1 Customer Configuration Register1 */
563#define SDR0_CUST1 0x4002
564#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
565#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
566#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
567
568/* Pin Function Control Register 0 */
569#define SDR0_PFC0 0x4100
570#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
571#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
572#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
573#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
574#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
575
576/* Pin Function Control Register 1 */
577#define SDR0_PFC1 0x4101
578#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
579#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
580#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
581#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
582#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
583#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
584#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
585#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
586#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
587#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
588#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
589#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
590#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
591#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
592#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
593#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
594#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
595#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
596#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
597#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
598#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
599#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
600#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
601#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
602
603#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
604#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
605#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
606#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
607
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]608#endif /* 440EP || 440GR || 440EPX || 440GRX */
609
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]610#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
611 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
612 defined(CONFIG_460EX) || defined(CONFIG_460GT)
613/* CUST0 Customer Configuration Register0 */
614#define SDR0_CUST0 0x4000
615#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
616#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
617#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
618#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]619
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]620#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
621#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
622#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
623
624#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
625#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
626#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
627
628#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
629#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
630#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
631
632#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
633#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
634#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
635
636#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
637#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
638#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
639
640#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
641#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
642#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
643
644#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
645#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
646#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
647
648#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
649#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
650#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
651#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
652#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
653#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
654#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
655#endif
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]656
657/*-----------------------------------------------------------------------------
658 | On-Chip Buses
659 +----------------------------------------------------------------------------*/
660/* TODO: as needed */
661
662/*-----------------------------------------------------------------------------
663 | Clocking, Power Management and Chip Control
664 +----------------------------------------------------------------------------*/
Feng Kan96e5fc02008-07-08 22:48:07 -0700[diff] [blame]665#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
666 defined(CONFIG_460SX)
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]667#define CNTRL_DCR_BASE 0x160
668#else
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]669#define CNTRL_DCR_BASE 0x0b0
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]670#endif
Eugene O'Brien5b2052e2008-04-11 10:00:35 -0400[diff] [blame]671
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]672#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
673#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
674#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]675
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]676#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
677#define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
678#define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */
679#define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]680
681#define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
682#define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
683#define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
684#define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
685
Stefan Roese5568e612005-11-22 13:20:42 +0100[diff] [blame]686#define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
687
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]688#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
689#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]690
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]691/*-----------------------------------------------------------------------------
692 | DMA
693 +----------------------------------------------------------------------------*/
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]694#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
695#define DMA_DCR_BASE 0x200
696#else
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]697#define DMA_DCR_BASE 0x100
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]698#endif
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]699#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
700#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
701#define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */
702#define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */
703#define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */
704#define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]705#define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */
706#define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]707#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
708#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
709#define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */
710#define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */
711#define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */
712#define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]713#define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */
714#define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]715#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
716#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
717#define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */
718#define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */
719#define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */
720#define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]721#define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */
722#define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]723#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
724#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */
725#define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */
726#define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */
727#define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */
728#define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]729#define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */
730#define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]731#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
732#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
733#define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */
734#define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]735
736/*-----------------------------------------------------------------------------
737 | Memory Access Layer
738 +----------------------------------------------------------------------------*/
739#define MAL_DCR_BASE 0x180
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]740#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
741#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
742#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
743#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
744#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]745#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
746#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]747#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
748#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */
749#define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */
750#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]751#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
752#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]753#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
754#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */
755#define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]756#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
757#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]758#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
759#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]760#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
761#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]762#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
763#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]764#if defined(CONFIG_440GX) || \
765 defined(CONFIG_460EX) || defined(CONFIG_460GT)
766#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
767#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
768#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100[diff] [blame]769#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */
770#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]771#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
772#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]773#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100[diff] [blame]774#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
775#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
Stefan Roese846b0dd2005-08-08 12:42:22 +0200[diff] [blame]776#endif /* CONFIG_440GX */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]777
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]778/*-----------------------------------------------------------------------------+
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]779| SDR0 Bit Settings
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]780+-----------------------------------------------------------------------------*/
Stefan Roesedf294492007-03-08 10:06:09 +0100[diff] [blame]781#if defined(CONFIG_440SP)
782#define SDR0_SRST 0x0200
783
784#define SDR0_DDR0 0x00E1
785#define SDR0_DDR0_DPLLRST 0x80000000
786#define SDR0_DDR0_DDRM_MASK 0x60000000
787#define SDR0_DDR0_DDRM_DDR1 0x20000000
788#define SDR0_DDR0_DDRM_DDR2 0x40000000
789#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
790#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
791#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
792#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
793#endif
794
Feng Kan96e5fc02008-07-08 22:48:07 -0700[diff] [blame]795#if defined(CONFIG_440SPE) || defined(CONFIG_460SX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]796#define SDR0_CP440 0x0180
797#define SDR0_CP440_ERPN_MASK 0x30000000
798#define SDR0_CP440_ERPN_MASK_HI 0x3000
799#define SDR0_CP440_ERPN_MASK_LO 0x0000
800#define SDR0_CP440_ERPN_EBC 0x10000000
801#define SDR0_CP440_ERPN_EBC_HI 0x1000
802#define SDR0_CP440_ERPN_EBC_LO 0x0000
803#define SDR0_CP440_ERPN_PCI 0x20000000
804#define SDR0_CP440_ERPN_PCI_HI 0x2000
805#define SDR0_CP440_ERPN_PCI_LO 0x0000
806#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
807#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
808#define SDR0_CP440_NTO1_MASK 0x00000002
809#define SDR0_CP440_NTO1_NTOP 0x00000000
810#define SDR0_CP440_NTO1_NTO1 0x00000002
811#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
812#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]813
814#define SDR0_SDSTP0 0x0020
815#define SDR0_SDSTP0_ENG_MASK 0x80000000
816#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
817#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
818#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
819#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
820#define SDR0_SDSTP0_SRC_MASK 0x40000000
821#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
822#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
823#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
824#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
825#define SDR0_SDSTP0_SEL_MASK 0x38000000
826#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
827#define SDR0_SDSTP0_SEL_CPU 0x08000000
828#define SDR0_SDSTP0_SEL_EBC 0x28000000
829#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
830#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
831#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
832#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
833#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
834#define SDR0_SDSTP0_FBDV_MASK 0x0001F000
835#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
836#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
837#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
838#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
839#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
840#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
841#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
842#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
843#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
844#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
845#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
846#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
847#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
848#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
849
850
851#define SDR0_SDSTP1 0x0021
852#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
853#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
854#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
855#define SDR0_SDSTP1_PERDV0_MASK 0x03000000
856#define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
857#define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
858#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
859#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
860#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
861#define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000
862#define SDR0_SDSTP1_DDR1_MODE 0x00100000
863#define SDR0_SDSTP1_DDR2_MODE 0x00200000
864#define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
865#define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
866#define SDR0_SDSTP1_ERPN_MASK 0x00080000
867#define SDR0_SDSTP1_ERPN_EBC 0x00000000
868#define SDR0_SDSTP1_ERPN_PCI 0x00080000
869#define SDR0_SDSTP1_PAE_MASK 0x00040000
870#define SDR0_SDSTP1_PAE_DISABLE 0x00000000
871#define SDR0_SDSTP1_PAE_ENABLE 0x00040000
872#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
873#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
874#define SDR0_SDSTP1_PHCE_MASK 0x00020000
875#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
876#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
877#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
878#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
879#define SDR0_SDSTP1_PISE_MASK 0x00010000
880#define SDR0_SDSTP1_PISE_DISABLE 0x00000000
881#define SDR0_SDSTP1_PISE_ENABLE 0x00001000
882#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
883#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
884#define SDR0_SDSTP1_PCWE_MASK 0x00008000
885#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
886#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
887#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
888#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
889#define SDR0_SDSTP1_PPIM_MASK 0x00007800
890#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
891#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
892#define SDR0_SDSTP1_PR64E_MASK 0x00000400
893#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
894#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
895#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
896#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
897#define SDR0_SDSTP1_PXFS_MASK 0x00000300
898#define SDR0_SDSTP1_PXFS_100_133 0x00000000
899#define SDR0_SDSTP1_PXFS_66_100 0x00000100
900#define SDR0_SDSTP1_PXFS_50_66 0x00000200
901#define SDR0_SDSTP1_PXFS_0_50 0x00000300
902#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
903#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
904#define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */
905#define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */
906#define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */
907#define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
908#define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
909#define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
910#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
911#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
912#define SDR0_SDSTP1_ETH_MASK 0x00000004
913#define SDR0_SDSTP1_ETH_10_100 0x00000000
914#define SDR0_SDSTP1_ETH_GIGA 0x00000004
915#define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
916#define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
917#define SDR0_SDSTP1_NTO1_MASK 0x00000001
918#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
919#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
920#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
921#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
922
923#define SDR0_SDSTP2 0x0022
924#define SDR0_SDSTP2_P1AE_MASK 0x80000000
925#define SDR0_SDSTP2_P1AE_DISABLE 0x00000000
926#define SDR0_SDSTP2_P1AE_ENABLE 0x80000000
927#define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
928#define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
929#define SDR0_SDSTP2_P1HCE_MASK 0x40000000
930#define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000
931#define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000
932#define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
933#define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
934#define SDR0_SDSTP2_P1ISE_MASK 0x20000000
935#define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000
936#define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000
937#define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
938#define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
939#define SDR0_SDSTP2_P1CWE_MASK 0x10000000
940#define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000
941#define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000
942#define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
943#define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
944#define SDR0_SDSTP2_P1PIM_MASK 0x0F000000
945#define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
946#define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
947#define SDR0_SDSTP2_P1R64E_MASK 0x00800000
948#define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000
949#define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000
950#define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
951#define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
952#define SDR0_SDSTP2_P1XFS_MASK 0x00600000
953#define SDR0_SDSTP2_P1XFS_100_133 0x00000000
954#define SDR0_SDSTP2_P1XFS_66_100 0x00200000
955#define SDR0_SDSTP2_P1XFS_50_66 0x00400000
956#define SDR0_SDSTP2_P1XFS_0_50 0x00600000
957#define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
958#define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
959#define SDR0_SDSTP2_P2AE_MASK 0x00040000
960#define SDR0_SDSTP2_P2AE_DISABLE 0x00000000
961#define SDR0_SDSTP2_P2AE_ENABLE 0x00040000
962#define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
963#define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
964#define SDR0_SDSTP2_P2HCE_MASK 0x00020000
965#define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000
966#define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000
967#define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
968#define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
969#define SDR0_SDSTP2_P2ISE_MASK 0x00010000
970#define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000
971#define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000
972#define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
973#define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
974#define SDR0_SDSTP2_P2CWE_MASK 0x00008000
975#define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000
976#define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000
977#define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
978#define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
979#define SDR0_SDSTP2_P2PIM_MASK 0x00007800
980#define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
981#define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
982#define SDR0_SDSTP2_P2XFS_MASK 0x00000300
983#define SDR0_SDSTP2_P2XFS_100_133 0x00000000
984#define SDR0_SDSTP2_P2XFS_66_100 0x00000100
985#define SDR0_SDSTP2_P2XFS_50_66 0x00000200
986#define SDR0_SDSTP2_P2XFS_0_50 0x00000100
987#define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
988#define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
989
990#define SDR0_SDSTP3 0x0023
991
992#define SDR0_PINSTP 0x0040
993#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
994#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
995#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
996#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
997#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
998#define SDR0_SDCS 0x0060
999#define SDR0_ECID0 0x0080
1000#define SDR0_ECID1 0x0081
1001#define SDR0_ECID2 0x0082
1002#define SDR0_JTAG 0x00C0
1003
1004#define SDR0_DDR0 0x00E1
1005#define SDR0_DDR0_DPLLRST 0x80000000
1006#define SDR0_DDR0_DDRM_MASK 0x60000000
1007#define SDR0_DDR0_DDRM_DDR1 0x20000000
1008#define SDR0_DDR0_DDRM_DDR2 0x40000000
1009#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
1010#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
1011#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
1012#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
1013
1014#define SDR0_UART0 0x0120
1015#define SDR0_UART1 0x0121
1016#define SDR0_UART2 0x0122
1017#define SDR0_UARTX_UXICS_MASK 0xF0000000
1018#define SDR0_UARTX_UXICS_PLB 0x20000000
1019#define SDR0_UARTX_UXEC_MASK 0x00800000
1020#define SDR0_UARTX_UXEC_INT 0x00000000
1021#define SDR0_UARTX_UXEC_EXT 0x00800000
1022#define SDR0_UARTX_UXDIV_MASK 0x000000FF
1023#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
1024#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
1025
1026#define SDR0_CP440 0x0180
1027#define SDR0_CP440_ERPN_MASK 0x30000000
1028#define SDR0_CP440_ERPN_MASK_HI 0x3000
1029#define SDR0_CP440_ERPN_MASK_LO 0x0000
1030#define SDR0_CP440_ERPN_EBC 0x10000000
1031#define SDR0_CP440_ERPN_EBC_HI 0x1000
1032#define SDR0_CP440_ERPN_EBC_LO 0x0000
1033#define SDR0_CP440_ERPN_PCI 0x20000000
1034#define SDR0_CP440_ERPN_PCI_HI 0x2000
1035#define SDR0_CP440_ERPN_PCI_LO 0x0000
1036#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
1037#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
1038#define SDR0_CP440_NTO1_MASK 0x00000002
1039#define SDR0_CP440_NTO1_NTOP 0x00000000
1040#define SDR0_CP440_NTO1_NTO1 0x00000002
1041#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
1042#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
1043
1044#define SDR0_XCR0 0x01C0
1045#define SDR0_XCR1 0x01C3
1046#define SDR0_XCR2 0x01C6
1047#define SDR0_XCRn_PAE_MASK 0x80000000
1048#define SDR0_XCRn_PAE_DISABLE 0x00000000
1049#define SDR0_XCRn_PAE_ENABLE 0x80000000
1050#define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1051#define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1052#define SDR0_XCRn_PHCE_MASK 0x40000000
1053#define SDR0_XCRn_PHCE_DISABLE 0x00000000
1054#define SDR0_XCRn_PHCE_ENABLE 0x40000000
1055#define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1056#define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1057#define SDR0_XCRn_PISE_MASK 0x20000000
1058#define SDR0_XCRn_PISE_DISABLE 0x00000000
1059#define SDR0_XCRn_PISE_ENABLE 0x20000000
1060#define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1061#define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1062#define SDR0_XCRn_PCWE_MASK 0x10000000
1063#define SDR0_XCRn_PCWE_DISABLE 0x00000000
1064#define SDR0_XCRn_PCWE_ENABLE 0x10000000
1065#define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
1066#define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
1067#define SDR0_XCRn_PPIM_MASK 0x0F000000
1068#define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
1069#define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1070#define SDR0_XCRn_PR64E_MASK 0x00800000
1071#define SDR0_XCRn_PR64E_DISABLE 0x00000000
1072#define SDR0_XCRn_PR64E_ENABLE 0x00800000
1073#define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
1074#define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
1075#define SDR0_XCRn_PXFS_MASK 0x00600000
1076#define SDR0_XCRn_PXFS_100_133 0x00000000
1077#define SDR0_XCRn_PXFS_66_100 0x00200000
1078#define SDR0_XCRn_PXFS_50_66 0x00400000
1079#define SDR0_XCRn_PXFS_0_33 0x00600000
1080#define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
1081#define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
1082
1083#define SDR0_XPLLC0 0x01C1
1084#define SDR0_XPLLD0 0x01C2
1085#define SDR0_XPLLC1 0x01C4
1086#define SDR0_XPLLD1 0x01C5
1087#define SDR0_XPLLC2 0x01C7
1088#define SDR0_XPLLD2 0x01C8
1089#define SDR0_SRST 0x0200
1090#define SDR0_SLPIPE 0x0220
1091
1092#define SDR0_AMP0 0x0240
1093#define SDR0_AMP0_PRIORITY 0xFFFF0000
1094#define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00
1095#define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF
1096
1097#define SDR0_AMP1 0x0241
1098#define SDR0_AMP1_PRIORITY 0xFC000000
1099#define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000
1100#define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF
1101
1102#define SDR0_MIRQ0 0x0260
1103#define SDR0_MIRQ1 0x0261
1104#define SDR0_MALTBL 0x0280
1105#define SDR0_MALRBL 0x02A0
1106#define SDR0_MALTBS 0x02C0
1107#define SDR0_MALRBS 0x02E0
1108
1109/* Reserved for Customer Use */
1110#define SDR0_CUST0 0x4000
1111#define SDR0_CUST0_AUTONEG_MASK 0x8000000
1112#define SDR0_CUST0_NO_AUTONEG 0x0000000
1113#define SDR0_CUST0_AUTONEG 0x8000000
1114#define SDR0_CUST0_ETH_FORCE_MASK 0x6000000
1115#define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000
1116#define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000
1117#define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000
1118#define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000
1119#define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000
1120#define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000
1121
1122#define SDR0_SDSTP4 0x4001
1123#define SDR0_CUST1 0x4002
1124#define SDR0_SDSTP5 0x4003
1125#define SDR0_CUST2 0x4004
1126#define SDR0_SDSTP6 0x4005
1127#define SDR0_CUST3 0x4006
1128#define SDR0_SDSTP7 0x4007
1129
1130#define SDR0_PFC0 0x4100
1131#define SDR0_PFC0_GPIO_0 0x80000000
1132#define SDR0_PFC0_PCIX0REQ2_N 0x00000000
1133#define SDR0_PFC0_GPIO_1 0x40000000
1134#define SDR0_PFC0_PCIX0REQ3_N 0x00000000
1135#define SDR0_PFC0_GPIO_2 0x20000000
1136#define SDR0_PFC0_PCIX0GNT2_N 0x00000000
1137#define SDR0_PFC0_GPIO_3 0x10000000
1138#define SDR0_PFC0_PCIX0GNT3_N 0x00000000
1139#define SDR0_PFC0_GPIO_4 0x08000000
1140#define SDR0_PFC0_PCIX1REQ2_N 0x00000000
1141#define SDR0_PFC0_GPIO_5 0x04000000
1142#define SDR0_PFC0_PCIX1REQ3_N 0x00000000
1143#define SDR0_PFC0_GPIO_6 0x02000000
1144#define SDR0_PFC0_PCIX1GNT2_N 0x00000000
1145#define SDR0_PFC0_GPIO_7 0x01000000
1146#define SDR0_PFC0_PCIX1GNT3_N 0x00000000
1147#define SDR0_PFC0_GPIO_8 0x00800000
1148#define SDR0_PFC0_PERREADY 0x00000000
1149#define SDR0_PFC0_GPIO_9 0x00400000
1150#define SDR0_PFC0_PERCS1_N 0x00000000
1151#define SDR0_PFC0_GPIO_10 0x00200000
1152#define SDR0_PFC0_PERCS2_N 0x00000000
1153#define SDR0_PFC0_GPIO_11 0x00100000
1154#define SDR0_PFC0_IRQ0 0x00000000
1155#define SDR0_PFC0_GPIO_12 0x00080000
1156#define SDR0_PFC0_IRQ1 0x00000000
1157#define SDR0_PFC0_GPIO_13 0x00040000
1158#define SDR0_PFC0_IRQ2 0x00000000
1159#define SDR0_PFC0_GPIO_14 0x00020000
1160#define SDR0_PFC0_IRQ3 0x00000000
1161#define SDR0_PFC0_GPIO_15 0x00010000
1162#define SDR0_PFC0_IRQ4 0x00000000
1163#define SDR0_PFC0_GPIO_16 0x00008000
1164#define SDR0_PFC0_IRQ5 0x00000000
1165#define SDR0_PFC0_GPIO_17 0x00004000
1166#define SDR0_PFC0_PERBE0_N 0x00000000
1167#define SDR0_PFC0_GPIO_18 0x00002000
1168#define SDR0_PFC0_PCI0GNT0_N 0x00000000
1169#define SDR0_PFC0_GPIO_19 0x00001000
1170#define SDR0_PFC0_PCI0GNT1_N 0x00000000
1171#define SDR0_PFC0_GPIO_20 0x00000800
1172#define SDR0_PFC0_PCI0REQ0_N 0x00000000
1173#define SDR0_PFC0_GPIO_21 0x00000400
1174#define SDR0_PFC0_PCI0REQ1_N 0x00000000
1175#define SDR0_PFC0_GPIO_22 0x00000200
1176#define SDR0_PFC0_PCI1GNT0_N 0x00000000
1177#define SDR0_PFC0_GPIO_23 0x00000100
1178#define SDR0_PFC0_PCI1GNT1_N 0x00000000
1179#define SDR0_PFC0_GPIO_24 0x00000080
1180#define SDR0_PFC0_PCI1REQ0_N 0x00000000
1181#define SDR0_PFC0_GPIO_25 0x00000040
1182#define SDR0_PFC0_PCI1REQ1_N 0x00000000
1183#define SDR0_PFC0_GPIO_26 0x00000020
1184#define SDR0_PFC0_PCI2GNT0_N 0x00000000
1185#define SDR0_PFC0_GPIO_27 0x00000010
1186#define SDR0_PFC0_PCI2GNT1_N 0x00000000
1187#define SDR0_PFC0_GPIO_28 0x00000008
1188#define SDR0_PFC0_PCI2REQ0_N 0x00000000
1189#define SDR0_PFC0_GPIO_29 0x00000004
1190#define SDR0_PFC0_PCI2REQ1_N 0x00000000
1191#define SDR0_PFC0_GPIO_30 0x00000002
1192#define SDR0_PFC0_UART1RX 0x00000000
1193#define SDR0_PFC0_GPIO_31 0x00000001
1194#define SDR0_PFC0_UART1TX 0x00000000
1195
1196#define SDR0_PFC1 0x4101
1197#define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000
1198#define SDR0_PFC1_UART1_DSR_DTR 0x00000000
1199#define SDR0_PFC1_UART1_CTS_RTS 0x02000000
1200#define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000
1201#define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000
1202#define SDR0_PFC1_UART2_IN_SERVICE 0x01000000
1203#define SDR0_PFC1_ETH_GIGA_MASK 0x00200000
1204#define SDR0_PFC1_ETH_10_100 0x00000000
1205#define SDR0_PFC1_ETH_GIGA 0x00200000
1206#define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21)
1207#define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
1208#define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
1209#define SDR0_PFC1_CPU_NO_TRACE 0x00000000
1210#define SDR0_PFC1_CPU_TRACE 0x00080000
1211#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
1212#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
1213
1214#define SDR0_MFR 0x4300
1215#endif /* CONFIG_440SPE */
1216
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]1217#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1218/* Pin Function Control Register 0 (SDR0_PFC0) */
1219#define SDR0_PFC0 0x4100
1220#define SDR0_PFC0_DBG 0x00008000 /* debug enable */
1221#define SDR0_PFC0_G49E 0x00004000 /* GPIO 49 enable */
1222#define SDR0_PFC0_G50E 0x00002000 /* GPIO 50 enable */
1223#define SDR0_PFC0_G51E 0x00001000 /* GPIO 51 enable */
1224#define SDR0_PFC0_G52E 0x00000800 /* GPIO 52 enable */
1225#define SDR0_PFC0_G53E 0x00000400 /* GPIO 53 enable */
1226#define SDR0_PFC0_G54E 0x00000200 /* GPIO 54 enable */
1227#define SDR0_PFC0_G55E 0x00000100 /* GPIO 55 enable */
1228#define SDR0_PFC0_G56E 0x00000080 /* GPIO 56 enable */
1229#define SDR0_PFC0_G57E 0x00000040 /* GPIO 57 enable */
1230#define SDR0_PFC0_G58E 0x00000020 /* GPIO 58 enable */
1231#define SDR0_PFC0_G59E 0x00000010 /* GPIO 59 enable */
1232#define SDR0_PFC0_G60E 0x00000008 /* GPIO 60 enable */
1233#define SDR0_PFC0_G61E 0x00000004 /* GPIO 61 enable */
1234#define SDR0_PFC0_G62E 0x00000002 /* GPIO 62 enable */
1235#define SDR0_PFC0_G63E 0x00000001 /* GPIO 63 enable */
1236
1237/* Pin Function Control Register 1 (SDR0_PFC1) */
1238#define SDR0_PFC1 0x4101
1239#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
1240#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
1241#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
1242#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
1243#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
1244#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
1245#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
1246#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins*/
1247#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins*/
1248#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
1249#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
1250#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
1251
1252/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
1253#define SDR0_ETH_PLL 0x4102
1254#define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/
1255#define SDR0_ETH_PLL_REF_CLK_SEL 0x10000000 /* Ethernet reference clock */
1256#define SDR0_ETH_PLL_BYPASS 0x08000000 /* bypass mode enable */
1257#define SDR0_ETH_PLL_STOPCLK 0x04000000 /* output clock disable */
1258#define SDR0_ETH_PLL_TUNE_MASK 0x03FF0000 /* loop stability tuning bits */
1259#define SDR0_ETH_PLL_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3ff)<<16)
1260#define SDR0_ETH_PLL_MULTI_MASK 0x0000FF00 /* frequency multiplication */
1261#define SDR0_ETH_PLL_MULTI_ENCODE(n) ((((unsigned long)(n))&0xff)<<8)
1262#define SDR0_ETH_PLL_RANGEB_MASK 0x000000F0 /* PLLOUTB/C frequency */
1263#define SDR0_ETH_PLL_RANGEB_ENCODE(n) ((((unsigned long)(n))&0x0f)<<4)
1264#define SDR0_ETH_PLL_RANGEA_MASK 0x0000000F /* PLLOUTA frequency */
1265#define SDR0_ETH_PLL_RANGEA_ENCODE(n) (((unsigned long)(n))&0x0f)
1266
1267/* Ethernet Configuration Register (SDR0_ETH_CFG) */
1268#define SDR0_ETH_CFG 0x4103
1269#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /* SGMII3 port loopback enable */
1270#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /* SGMII2 port loopback enable */
1271#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /* SGMII1 port loopback enable */
1272#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /* SGMII0 port loopback enable */
1273#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /* SGMII Mask */
1274#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /* SGMII2 port enable */
1275#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /* SGMII1 port enable */
1276#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /* SGMII0 port enable */
1277#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /* TAHOE1 Bypass selector */
1278#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /* TAHOE0 Bypass selector */
1279#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /* EMAC 3 PHY clock selector */
1280#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /* EMAC 2 PHY clock selector */
1281#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /* EMAC 1 PHY clock selector */
1282#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /* EMAC 0 PHY clock selector */
1283#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /* Swap EMAC2 with EMAC1 */
1284#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /* Swap EMAC0 with EMAC3 */
1285#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /* MDIO source selector mask */
1286#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /* MDIO source - EMAC0 */
1287#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /* MDIO source - EMAC1 */
1288#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /* MDIO source - EMAC2 */
1289#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /* MDIO source - EMAC3 */
1290#define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /* ZMII bridge mode selector mask */
1291#define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /* ZMII bridge mode - MII */
1292#define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /* ZMII bridge mode - SMII */
1293#define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /* ZMII bridge mode - RMII (10 Mbps) */
1294#define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /* ZMII bridge mode - RMII (100 Mbps) */
1295#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /* GMC Port 1 bridge selector */
1296#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /* GMC Port 0 bridge selector */
1297
1298#define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4
1299#define SDR0_ETH_CFG_ZMII_MII_MODE 0x00
1300#define SDR0_ETH_CFG_ZMII_SMII_MODE 0x01
1301#define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10
1302#define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11
1303
Adam Grahamf09f09d2008-10-08 10:12:53 -0700[diff] [blame]1304/* Ethernet Status Register */
1305#define SDR0_ETH_STS 0x4104
1306
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]1307/* Miscealleneaous Function Reg. (SDR0_MFR) */
1308#define SDR0_MFR 0x4300
1309#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */
1310#define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx FIFO bits 64:127 */
1311#define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx FIFO bits 0:63 */
1312#define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx FIFO bits 64:127 */
1313#define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx FIFO bits 0:63 */
1314#define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx FIFO bits 64:127 */
1315#define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx FIFO bits 0:63 */
1316#define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx FIFO bits 64:127 */
1317#define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx FIFO bits 0:63 */
1318#define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx FIFO bits 64:127 */
1319#define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx FIFO bits 0:63 */
1320#define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx FIFO bits 64:127 */
1321#define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx FIFO bits 0:63 */
1322#define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx FIFO bits 64:127 */
1323#define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx FIFO bits 0:63 */
1324#define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx FIFO bits 64:127 */
1325#define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx FIFO bits 0:63 */
1326#define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx FIFO bits 64:127 */
1327#define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx FIFO bits 0:63 */
1328#define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx FIFO bits 64:127 */
1329
1330/* EMACx TX Status Register (SDR0_EMACxTXST)*/
1331#define SDR0_EMAC0TXST 0x4400
1332#define SDR0_EMAC1TXST 0x4401
1333#define SDR0_EMAC2TXST 0x4402
1334#define SDR0_EMAC3TXST 0x4403
1335
1336#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */
1337#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */
1338#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */
1339#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */
1340#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */
1341#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame */
1342#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */
1343#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */
1344#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */
1345#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */
1346#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */
1347#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */
1348#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */
1349#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */
1350#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */
1351#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */
1352#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */
1353#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */
1354#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */
1355#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */
1356#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */
1357#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */
1358#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */
1359#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */
1360
1361/* EMACx RX Status Register (SDR0_EMACxRXST)*/
1362#define SDR0_EMAC0RXST 0x4404
1363#define SDR0_EMAC1RXST 0x4405
1364#define SDR0_EMAC2RXST 0x4406
1365#define SDR0_EMAC3RXST 0x4407
1366
1367#define SDR0_EMACxRXST_FOR 0x20000000 /* RX FIFO overrun */
1368#define SDR0_EMACxRXST_BC 0x10000000 /* broadcast address */
1369#define SDR0_EMACxRXST_MC 0x08000000 /* multicast address */
1370#define SDR0_EMACxRXST_UC 0x04000000 /* unicast address */
1371#define SDR0_EMACxRXST_UPR_MASK 0x03800000 /* user priority field */
1372#define SDR0_EMACxRXST_UPR_ENCODE(n) ((((unsigned long)(n))&0x07)<<23)
1373#define SDR0_EMACxRXST_VLAN 0x00400000 /* RX VLAN tagged frame */
1374#define SDR0_EMACxRXST_LOOP 0x00200000 /* received in loop-back mode */
1375#define SDR0_EMACxRXST_UOP 0x00100000 /* RX unsupported opcode */
1376#define SDR0_EMACxRXST_CPF 0x00080000 /* RX control pause frame */
1377#define SDR0_EMACxRXST_CF 0x00040000 /* RX control frame*/
1378#define SDR0_EMACxRXST_MSIZ 0x00020000 /* 1024-MaxSize bytes recieved*/
1379#define SDR0_EMACxRXST_1023 0x00010000 /* 512-1023 bytes received */
1380#define SDR0_EMACxRXST_511 0x00008000 /* 128-511 bytes received */
1381#define SDR0_EMACxRXST_255 0x00004000 /* 128-255 bytes received */
1382#define SDR0_EMACxRXST_127 0x00002000 /* 65-127 bytes received */
1383#define SDR0_EMACxRXST_64 0x00001000 /* 64 bytes received */
1384#define SDR0_EMACxRXST_RUNT 0x00000800 /* runt frame */
1385#define SDR0_EMACxRXST_SEVT 0x00000400 /* short event */
1386#define SDR0_EMACxRXST_AERR 0x00000200 /* alignment error */
1387#define SDR0_EMACxRXST_SERR 0x00000100 /* received with symbol error */
1388#define SDR0_EMACxRXST_BURST 0x00000040 /* received burst */
1389#define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */
1390#define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */
1391#define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */
1392#define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal EMAC receive error */
1393#define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */
1394#define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */
1395
1396/* EMACx TX Status Register (SDR0_EMACxREJCNT)*/
1397#define SDR0_EMAC0REJCNT 0x4408
1398#define SDR0_EMAC1REJCNT 0x4409
1399#define SDR0_EMAC2REJCNT 0x440A
1400#define SDR0_EMAC3REJCNT 0x440B
1401
1402#define SDR0_DDR0 0x00E1
1403#define SDR0_DDR0_DPLLRST 0x80000000
1404#define SDR0_DDR0_DDRM_MASK 0x60000000
1405#define SDR0_DDR0_DDRM_DDR1 0x20000000
1406#define SDR0_DDR0_DDRM_DDR2 0x40000000
1407#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
1408#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
1409#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
1410#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
Stefan Roese41712b42008-03-05 12:31:53 +0100[diff] [blame]1411
1412#define AHB_TOP 0xA4
1413#define AHB_BOT 0xA5
Stefan Roese745d8a02008-06-28 14:56:17 +0200[diff] [blame]1414#define SDR0_AHB_CFG 0x370
1415#define SDR0_USB2HOST_CFG 0x371
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]1416#endif /* CONFIG_460EX || CONFIG_460GT */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]1417
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]1418#define SDR0_SDCS_SDD (0x80000000 >> 31)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1419
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]1420#if defined(CONFIG_440GP)
1421#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
1422#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
1423#endif /* defined(CONFIG_440GP) */
1424#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
1425#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
1426#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
1427#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1428#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1429 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]1430#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
1431#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
1432#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1433
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1434#define SDR0_UARTX_UXICS_MASK 0xF0000000
1435#define SDR0_UARTX_UXICS_PLB 0x20000000
1436#define SDR0_UARTX_UXEC_MASK 0x00800000
1437#define SDR0_UARTX_UXEC_INT 0x00000000
1438#define SDR0_UARTX_UXEC_EXT 0x00800000
1439#define SDR0_UARTX_UXDTE_MASK 0x00400000
1440#define SDR0_UARTX_UXDTE_DISABLE 0x00000000
1441#define SDR0_UARTX_UXDTE_ENABLE 0x00400000
1442#define SDR0_UARTX_UXDRE_MASK 0x00200000
1443#define SDR0_UARTX_UXDRE_DISABLE 0x00000000
1444#define SDR0_UARTX_UXDRE_ENABLE 0x00200000
1445#define SDR0_UARTX_UXDC_MASK 0x00100000
1446#define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000
1447#define SDR0_UARTX_UXDC_CLEARED 0x00100000
1448#define SDR0_UARTX_UXDIV_MASK 0x000000FF
1449#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
1450#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1451
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1452#define SDR0_CPU440_EARV_MASK 0x30000000
1453#define SDR0_CPU440_EARV_EBC 0x10000000
1454#define SDR0_CPU440_EARV_PCI 0x20000000
1455#define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
1456#define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
1457#define SDR0_CPU440_NTO1_MASK 0x00000002
1458#define SDR0_CPU440_NTO1_NTOP 0x00000000
1459#define SDR0_CPU440_NTO1_NTO1 0x00000002
1460#define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
1461#define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1462
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1463#define SDR0_XCR_PAE_MASK 0x80000000
1464#define SDR0_XCR_PAE_DISABLE 0x00000000
1465#define SDR0_XCR_PAE_ENABLE 0x80000000
1466#define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1467#define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1468#define SDR0_XCR_PHCE_MASK 0x40000000
1469#define SDR0_XCR_PHCE_DISABLE 0x00000000
1470#define SDR0_XCR_PHCE_ENABLE 0x40000000
1471#define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1472#define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1473#define SDR0_XCR_PISE_MASK 0x20000000
1474#define SDR0_XCR_PISE_DISABLE 0x00000000
1475#define SDR0_XCR_PISE_ENABLE 0x20000000
1476#define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1477#define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1478#define SDR0_XCR_PCWE_MASK 0x10000000
1479#define SDR0_XCR_PCWE_DISABLE 0x00000000
1480#define SDR0_XCR_PCWE_ENABLE 0x10000000
1481#define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
1482#define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
1483#define SDR0_XCR_PPIM_MASK 0x0F000000
1484#define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
1485#define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1486#define SDR0_XCR_PR64E_MASK 0x00800000
1487#define SDR0_XCR_PR64E_DISABLE 0x00000000
1488#define SDR0_XCR_PR64E_ENABLE 0x00800000
1489#define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
1490#define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
1491#define SDR0_XCR_PXFS_MASK 0x00600000
1492#define SDR0_XCR_PXFS_HIGH 0x00000000
1493#define SDR0_XCR_PXFS_MED 0x00200000
1494#define SDR0_XCR_PXFS_LOW 0x00400000
1495#define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
1496#define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
1497#define SDR0_XCR_PDM_MASK 0x00000040
1498#define SDR0_XCR_PDM_MULTIPOINT 0x00000000
1499#define SDR0_XCR_PDM_P2P 0x00000040
1500#define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19)
1501#define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1502
1503#define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1504#define SDR0_PFC0_GEIE_MASK 0x00003E00
1505#define SDR0_PFC0_GEIE_TRE 0x00003E00
1506#define SDR0_PFC0_GEIE_NOTRE 0x00000000
1507#define SDR0_PFC0_TRE_MASK 0x00000100
1508#define SDR0_PFC0_TRE_DISABLE 0x00000000
1509#define SDR0_PFC0_TRE_ENABLE 0x00000100
1510#define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
1511#define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1512
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1513#define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000
1514#define SDR0_PFC1_EPS_MASK 0x01C00000
1515#define SDR0_PFC1_EPS_GROUP0 0x00000000
1516#define SDR0_PFC1_EPS_GROUP1 0x00400000
1517#define SDR0_PFC1_EPS_GROUP2 0x00800000
1518#define SDR0_PFC1_EPS_GROUP3 0x00C00000
1519#define SDR0_PFC1_EPS_GROUP4 0x01000000
1520#define SDR0_PFC1_EPS_GROUP5 0x01400000
1521#define SDR0_PFC1_EPS_GROUP6 0x01800000
1522#define SDR0_PFC1_EPS_GROUP7 0x01C00000
1523#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
1524#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
1525#define SDR0_PFC1_RMII_MASK 0x00200000
1526#define SDR0_PFC1_RMII_100MBIT 0x00000000
1527#define SDR0_PFC1_RMII_10MBIT 0x00200000
1528#define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21)
1529#define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
1530#define SDR0_PFC1_CTEMS_MASK 0x00100000
1531#define SDR0_PFC1_CTEMS_EMS 0x00000000
1532#define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1533
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1534#define SDR0_MFR_TAH0_MASK 0x80000000
1535#define SDR0_MFR_TAH0_ENABLE 0x00000000
1536#define SDR0_MFR_TAH0_DISABLE 0x80000000
1537#define SDR0_MFR_TAH1_MASK 0x40000000
1538#define SDR0_MFR_TAH1_ENABLE 0x00000000
1539#define SDR0_MFR_TAH1_DISABLE 0x40000000
1540#define SDR0_MFR_PCM_MASK 0x20000000
1541#define SDR0_MFR_PCM_PPC440GX 0x00000000
1542#define SDR0_MFR_PCM_PPC440GP 0x20000000
1543#define SDR0_MFR_ECS_MASK 0x10000000
1544#define SDR0_MFR_ECS_INTERNAL 0x10000000
1545
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1546#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
1547#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
1548#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
1549#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
1550#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
1551#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
1552#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
1553#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
1554#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
1555#define SDR0_MFR_ERRATA3_EN0 0x00800000
1556#define SDR0_MFR_ERRATA3_EN1 0x00400000
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1557#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1558#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
1559#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1560#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
1561#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
1562#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1563#endif
1564
1565#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1566#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
1567#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
1568#define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29)
1569#define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07)
1570#endif
1571
1572#define SDR0_MFR_ECS_MASK 0x10000000
1573#define SDR0_MFR_ECS_INTERNAL 0x10000000
1574
1575#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1576#define SDR0_SRST0 0x200
1577#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
1578#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
1579#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
1580#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
1581#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
1582#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
1583#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
1584#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
1585#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
1586#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
1587#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
1588#define SDR0_SRST0_PCI 0x00100000 /* PCI */
1589#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
1590#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
1591#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
1592#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
1593#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
1594#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
1595#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
1596#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
1597#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
1598#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
1599#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
1600#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
1601#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
1602#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
1603#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
1604#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
1605#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
1606#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */
1607#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */
1608
1609#define SDR0_SRST1 0x201
1610#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
1611#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
1612#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
1613#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
1614#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
1615#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
1616#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
1617#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
1618#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
1619#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
1620#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */
1621#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
1622#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
1623#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
1624#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
1625#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
1626#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
1627#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
1628#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
1629#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
1630
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]1631#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1632
1633#define SDR0_SRST0 0x0200
1634#define SDR0_SRST SDR0_SRST0 /* for compatability reasons */
1635#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
1636#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
1637#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
1638#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
1639#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
1640#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
1641#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
1642#define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */
1643#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */
1644#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
1645#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
1646#define SDR0_SRST0_PCI 0x00100000 /* PCI */
1647#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
1648#define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */
1649#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/
1650#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/
1651#define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/
1652#define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/
1653#define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/
1654#define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/
1655#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/transmitter 2 */
1656#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
1657#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
1658#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */
1659#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/transmitter 3 */
1660#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */
1661
1662#define SDR0_SRST1 0x201
1663#define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */
1664#define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */
1665#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */
1666#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */
1667#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */
1668#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access controller 0 */
1669#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access controller 1 */
1670#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access controller 2 */
1671#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access controller 3 */
1672#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */
1673#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */
1674#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */
1675#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */
1676#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */
1677#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */
1678#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and serdes */
1679#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */
1680#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */
1681#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */
1682#define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */
1683#define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */
1684#define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */
1685#define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */
1686#define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */
1687#define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */
1688#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */
1689#define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */
1690#define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */
1691#define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */
1692#define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */
1693#define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */
1694#define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */
1695
1696#define SDR0_PCI0 0x1c0 /* PCI Configuration Register */
1697
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1698#else
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1699
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1700#define SDR0_SRST_BGO 0x80000000
1701#define SDR0_SRST_PLB 0x40000000
1702#define SDR0_SRST_EBC 0x20000000
1703#define SDR0_SRST_OPB 0x10000000
1704#define SDR0_SRST_UART0 0x08000000
1705#define SDR0_SRST_UART1 0x04000000
1706#define SDR0_SRST_IIC0 0x02000000
1707#define SDR0_SRST_IIC1 0x01000000
1708#define SDR0_SRST_GPIO 0x00800000
1709#define SDR0_SRST_GPT 0x00400000
1710#define SDR0_SRST_DMC 0x00200000
1711#define SDR0_SRST_PCI 0x00100000
1712#define SDR0_SRST_EMAC0 0x00080000
1713#define SDR0_SRST_EMAC1 0x00040000
1714#define SDR0_SRST_CPM 0x00020000
1715#define SDR0_SRST_IMU 0x00010000
1716#define SDR0_SRST_UIC01 0x00008000
1717#define SDR0_SRST_UICB2 0x00004000
1718#define SDR0_SRST_SRAM 0x00002000
1719#define SDR0_SRST_EBM 0x00001000
1720#define SDR0_SRST_BGI 0x00000800
1721#define SDR0_SRST_DMA 0x00000400
1722#define SDR0_SRST_DMAC 0x00000200
1723#define SDR0_SRST_MAL 0x00000100
1724#define SDR0_SRST_ZMII 0x00000080
1725#define SDR0_SRST_GPTR 0x00000040
1726#define SDR0_SRST_PPM 0x00000020
1727#define SDR0_SRST_EMAC2 0x00000010
1728#define SDR0_SRST_EMAC3 0x00000008
1729#define SDR0_SRST_RGMII 0x00000001
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1730
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1731#endif
1732
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1733/*-----------------------------------------------------------------------------+
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1734| Clocking
1735+-----------------------------------------------------------------------------*/
Feng Kan96e5fc02008-07-08 22:48:07 -0700[diff] [blame]1736#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1737 defined(CONFIG_460SX)
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]1738#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
1739#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
1740#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
1741#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
1742#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */
1743#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
1744#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
1745#elif !defined (CONFIG_440GX) && \
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1746 !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
1747 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
1748 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]1749#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
1750#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
1751#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
1752#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
1753#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
1754#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
1755#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
1756#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
1757#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
1758#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
1759#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
1760#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1761
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]1762#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
1763#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
1764#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
1765#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
Stefan Roese846b0dd2005-08-08 12:42:22 +0200[diff] [blame]1766#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]1767#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
1768#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
1769#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
1770#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
1771#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
1772#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
1773#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
1774#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
1775#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
1776
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1777#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
1778#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
1779#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
1780#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
1781#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
1782#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
1783
1784#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
1785#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
1786#define PRADV_MASK 0x07000000 /* Primary Divisor A */
1787#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
1788#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
1789
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]1790#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
1791#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
1792#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
1793#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
1794
1795/* Strap 1 Register */
1796#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
1797#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
1798#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
1799#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
1800#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
1801#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
1802#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
1803#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
1804#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
1805#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
1806#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
1807#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
1808#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
1809#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
1810#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
1811#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
1812#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
1813#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
Stefan Roese846b0dd2005-08-08 12:42:22 +0200[diff] [blame]1814#endif /* CONFIG_440GX */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1815
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1816#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
Stefan Roese26173fc2008-06-30 14:11:07 +0200[diff] [blame]1817#define CPR0_ICFG_RLI_MASK 0x80000000
1818#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
1819#define CPR0_PERD_PERDV0_MASK 0x07000000
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1820#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1821
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1822/*-----------------------------------------------------------------------------
1823| IIC Register Offsets
1824'----------------------------------------------------------------------------*/
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1825#define IICMDBUF 0x00
1826#define IICSDBUF 0x02
1827#define IICLMADR 0x04
1828#define IICHMADR 0x05
1829#define IICCNTL 0x06
1830#define IICMDCNTL 0x07
1831#define IICSTS 0x08
1832#define IICEXTSTS 0x09
1833#define IICLSADR 0x0A
1834#define IICHSADR 0x0B
1835#define IICCLKDIV 0x0C
1836#define IICINTRMSK 0x0D
1837#define IICXFRCNT 0x0E
1838#define IICXTCNTLSS 0x0F
1839#define IICDIRECTCNTL 0x10
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1840
1841/*-----------------------------------------------------------------------------
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1842| PCI Internal Registers et. al. (accessed via plb)
1843+----------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]1844#define PCIX0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000)
1845#define PCIX0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004)
1846#define PCIX0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000)
1847#define PCIX0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1848
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1849#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1850 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1851
1852/* PCI Local Configuration Registers
1853 --------------------------------- */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]1854#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1855
1856/* PCI Master Local Configuration Registers */
1857#define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
1858#define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
1859#define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
1860#define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
1861#define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
1862#define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
1863#define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
1864#define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
1865#define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
1866#define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
1867#define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
1868#define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
1869
1870/* PCI Target Local Configuration Registers */
1871#define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
1872#define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
1873#define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
1874#define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
1875
1876#else
1877
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1878#define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
1879#define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
1880#define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
1881#define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS )
1882#define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID )
1883#define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE)
1884#define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
1885#define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
1886#define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE )
1887#define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST )
1888#define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
1889#define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
1890#define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
1891#define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
1892#define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
1893#define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
1894#define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
1895#define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
1896#define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
1897#define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
1898#define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
1899#define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 )
1900#define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 )
1901#define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 )
1902#define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
1903#define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
1904#define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT )
1905#define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT )
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1906
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1907#define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040)
1908#define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1909
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1910#define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068)
1911#define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c)
1912#define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070)
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1913#define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074)
1914#define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1915#define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c)
1916#define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080)
1917#define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084)
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1918#define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088)
1919#define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1920#define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1921
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1922#define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098)
1923#define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c)
1924#define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0)
1925#define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4)
1926#define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8)
1927#define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac)
1928#define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0)
1929#define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4)
1930#define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1931
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1932#define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1933
Stefan Roese846b0dd2005-08-08 12:42:22 +0200[diff] [blame]1934#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1935
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1936#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1937
1938/* USB2.0 Device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]1939#define USB2D0_BASE CONFIG_SYS_USB2D0_BASE
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1940
1941#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
1942
1943#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
1944#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */
1945#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */
1946#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
1947#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
1948#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
1949#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
1950#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
1951#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
1952#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
1953#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
1954#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
1955#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
1956#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
1957#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
1958#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
1959#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
1960#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
1961#endif
1962
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1963/******************************************************************************
1964 * GPIO macro register defines
1965 ******************************************************************************/
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100[diff] [blame]1966#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
Feng Kan96e5fc02008-07-08 22:48:07 -0700[diff] [blame]1967 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1968 defined(CONFIG_460SX)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]1969#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000700)
Stefan Roesea4c8d132006-06-02 16:18:04 +0200[diff] [blame]1970
1971#define GPIO0_OR (GPIO0_BASE+0x0)
1972#define GPIO0_TCR (GPIO0_BASE+0x4)
1973#define GPIO0_ODR (GPIO0_BASE+0x18)
1974#define GPIO0_IR (GPIO0_BASE+0x1C)
Stefan Roese5568e612005-11-22 13:20:42 +0100[diff] [blame]1975#endif /* CONFIG_440GP */
1976
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1977#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]1978 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1979 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]1980#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00)
1981#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1982
Stefan Roesea4c8d132006-06-02 16:18:04 +0200[diff] [blame]1983#define GPIO0_OR (GPIO0_BASE+0x0)
1984#define GPIO0_TCR (GPIO0_BASE+0x4)
1985#define GPIO0_OSRL (GPIO0_BASE+0x8)
1986#define GPIO0_OSRH (GPIO0_BASE+0xC)
1987#define GPIO0_TSRL (GPIO0_BASE+0x10)
1988#define GPIO0_TSRH (GPIO0_BASE+0x14)
1989#define GPIO0_ODR (GPIO0_BASE+0x18)
1990#define GPIO0_IR (GPIO0_BASE+0x1C)
1991#define GPIO0_RR1 (GPIO0_BASE+0x20)
1992#define GPIO0_RR2 (GPIO0_BASE+0x24)
1993#define GPIO0_RR3 (GPIO0_BASE+0x28)
1994#define GPIO0_ISR1L (GPIO0_BASE+0x30)
1995#define GPIO0_ISR1H (GPIO0_BASE+0x34)
1996#define GPIO0_ISR2L (GPIO0_BASE+0x38)
1997#define GPIO0_ISR2H (GPIO0_BASE+0x3C)
1998#define GPIO0_ISR3L (GPIO0_BASE+0x40)
1999#define GPIO0_ISR3H (GPIO0_BASE+0x44)
2000
2001#define GPIO1_OR (GPIO1_BASE+0x0)
2002#define GPIO1_TCR (GPIO1_BASE+0x4)
2003#define GPIO1_OSRL (GPIO1_BASE+0x8)
2004#define GPIO1_OSRH (GPIO1_BASE+0xC)
2005#define GPIO1_TSRL (GPIO1_BASE+0x10)
2006#define GPIO1_TSRH (GPIO1_BASE+0x14)
2007#define GPIO1_ODR (GPIO1_BASE+0x18)
2008#define GPIO1_IR (GPIO1_BASE+0x1C)
2009#define GPIO1_RR1 (GPIO1_BASE+0x20)
2010#define GPIO1_RR2 (GPIO1_BASE+0x24)
2011#define GPIO1_RR3 (GPIO1_BASE+0x28)
2012#define GPIO1_ISR1L (GPIO1_BASE+0x30)
2013#define GPIO1_ISR1H (GPIO1_BASE+0x34)
2014#define GPIO1_ISR2L (GPIO1_BASE+0x38)
2015#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
2016#define GPIO1_ISR3L (GPIO1_BASE+0x40)
2017#define GPIO1_ISR3H (GPIO1_BASE+0x44)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]2018#endif
2019
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]2020#ifndef __ASSEMBLY__
2021
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]2022#endif /* _ASMLANGUAGE */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]2023
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]2024#endif /* __PPC440_H__ */