| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright(c) 2003 Motorola Inc. |
| 3 | * Xianghua Xiao (x.xiao@motorola.com) |
| 4 | */ |
| 5 | |
| 6 | #ifndef __MPC85xx_H__ |
| 7 | #define __MPC85xx_H__ |
| 8 | |
| 9 | #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ |
| 10 | |
| 11 | #if defined(CONFIG_E500) |
| 12 | #include <e500.h> |
| 13 | #endif |
| 14 | |
| 15 | #if defined(CONFIG_DDR_ECC) |
| 16 | void dma_init(void); |
| 17 | uint dma_check(void); |
| 18 | int dma_xfer(void *dest, uint count, void *src); |
| 19 | #endif |
| 20 | /*----------------------------------------------------------------------- |
| 21 | * SCCR - System Clock Control Register 9-8 |
| 22 | */ |
| 23 | #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ |
| 24 | #define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */ |
| 25 | #define SCCR_DFBRG_SHIFT 0 |
| 26 | |
| 27 | #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ |
| 28 | #define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/ |
| 29 | #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ |
| 30 | #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ |
| 31 | |
| 32 | #endif /* __MPC85xx_H__ */ |