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wdenk71f95112003-06-15 22:40:42 +00001/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00002 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05003 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Thomas Chouabe2c932011-04-19 03:48:31 +000017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk71f95112003-06-15 22:40:42 +000018 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef _MMC_H_
27#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000028
Andy Fleming272cc702008-10-30 16:41:01 -050029#include <linux/list.h>
30
31#define SD_VERSION_SD 0x20000
32#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
33#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
34#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
35#define MMC_VERSION_MMC 0x10000
36#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
37#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
38#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
39#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
40#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
41#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
42
43#define MMC_MODE_HS 0x001
44#define MMC_MODE_HS_52MHz 0x010
45#define MMC_MODE_4BIT 0x100
46#define MMC_MODE_8BIT 0x200
Thomas Choud52ebf12010-12-24 13:12:21 +000047#define MMC_MODE_SPI 0x400
Andy Fleming272cc702008-10-30 16:41:01 -050048
49#define SD_DATA_4BIT 0x00040000
50
Albin Tonnerre79b91de2009-08-22 14:21:53 +020051#define IS_SD(x) (x->version & SD_VERSION_SD)
Andy Fleming272cc702008-10-30 16:41:01 -050052
53#define MMC_DATA_READ 1
54#define MMC_DATA_WRITE 2
55
56#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
57#define UNUSABLE_ERR -17 /* Unusable Card */
58#define COMM_ERR -18 /* Communications Error */
59#define TIMEOUT -19
60
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020061#define MMC_CMD_GO_IDLE_STATE 0
62#define MMC_CMD_SEND_OP_COND 1
63#define MMC_CMD_ALL_SEND_CID 2
64#define MMC_CMD_SET_RELATIVE_ADDR 3
65#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050066#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020067#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050068#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020069#define MMC_CMD_SEND_CSD 9
70#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -050071#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020072#define MMC_CMD_SEND_STATUS 13
73#define MMC_CMD_SET_BLOCKLEN 16
74#define MMC_CMD_READ_SINGLE_BLOCK 17
75#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Andy Fleming272cc702008-10-30 16:41:01 -050076#define MMC_CMD_WRITE_SINGLE_BLOCK 24
77#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020078#define MMC_CMD_APP_CMD 55
Thomas Choud52ebf12010-12-24 13:12:21 +000079#define MMC_CMD_SPI_READ_OCR 58
80#define MMC_CMD_SPI_CRC_ON_OFF 59
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020081
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020082#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -050083#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020084#define SD_CMD_SEND_IF_COND 8
85
86#define SD_CMD_APP_SET_BUS_WIDTH 6
87#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -050088#define SD_CMD_APP_SEND_SCR 51
89
90/* SCR definitions in different words */
91#define SD_HIGHSPEED_BUSY 0x00020000
92#define SD_HIGHSPEED_SUPPORTED 0x00020000
93
94#define MMC_HS_TIMING 0x00000100
95#define MMC_HS_52MHZ 0x2
96
Thomas Chouabe2c932011-04-19 03:48:31 +000097#define OCR_BUSY 0x80000000
98#define OCR_HCS 0x40000000
Raffaele Recalcati31cacba2011-03-11 02:01:13 +000099#define OCR_VOLTAGE_MASK 0x007FFF80
100#define OCR_ACCESS_MODE 0x60000000
Andy Fleming272cc702008-10-30 16:41:01 -0500101
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000102#define MMC_STATUS_MASK (~0x0206BF7F)
Thomas Chouabe2c932011-04-19 03:48:31 +0000103#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
104#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Choued018b22011-04-19 03:48:32 +0000105#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000106
Andy Fleming272cc702008-10-30 16:41:01 -0500107#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
108#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
109#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
110#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
111#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
112#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
113#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
114#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
115#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
116#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
117#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
118#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
119#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
120#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
121#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
122#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
123#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
124
125#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
126#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
127 addressed by index which are
128 1 in value field */
129#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
130 addressed by index, which are
131 1 in value field */
132#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
133
134#define SD_SWITCH_CHECK 0
135#define SD_SWITCH_SWITCH 1
136
137/*
138 * EXT_CSD fields
139 */
140
141#define EXT_CSD_BUS_WIDTH 183 /* R/W */
142#define EXT_CSD_HS_TIMING 185 /* R/W */
143#define EXT_CSD_CARD_TYPE 196 /* RO */
144#define EXT_CSD_REV 192 /* RO */
145#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
146
147/*
148 * EXT_CSD field definitions
149 */
150
Thomas Chouabe2c932011-04-19 03:48:31 +0000151#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
152#define EXT_CSD_CMD_SET_SECURE (1 << 1)
153#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Fleming272cc702008-10-30 16:41:01 -0500154
Thomas Chouabe2c932011-04-19 03:48:31 +0000155#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
156#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Andy Fleming272cc702008-10-30 16:41:01 -0500157
158#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
159#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
160#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200161
Andy Fleming1de97f92008-10-30 16:31:39 -0500162#define R1_ILLEGAL_COMMAND (1 << 22)
163#define R1_APP_CMD (1 << 5)
164
Andy Fleming272cc702008-10-30 16:41:01 -0500165#define MMC_RSP_PRESENT (1 << 0)
Thomas Chouabe2c932011-04-19 03:48:31 +0000166#define MMC_RSP_136 (1 << 1) /* 136 bit response */
167#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
168#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
169#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Fleming272cc702008-10-30 16:41:01 -0500170
Thomas Chouabe2c932011-04-19 03:48:31 +0000171#define MMC_RSP_NONE (0)
172#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500173#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
174 MMC_RSP_BUSY)
Thomas Chouabe2c932011-04-19 03:48:31 +0000175#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
176#define MMC_RSP_R3 (MMC_RSP_PRESENT)
177#define MMC_RSP_R4 (MMC_RSP_PRESENT)
178#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
179#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
180#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500181
wdenk71f95112003-06-15 22:40:42 +0000182
Andy Fleming1de97f92008-10-30 16:31:39 -0500183struct mmc_cid {
184 unsigned long psn;
185 unsigned short oid;
186 unsigned char mid;
187 unsigned char prv;
188 unsigned char mdt;
189 char pnm[7];
190};
191
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200192/*
193 * WARNING!
194 *
195 * This structure is used by atmel_mci.c only.
196 * It works for the AVR32 architecture but NOT
197 * for ARM/AT91 architectures.
198 * Its use is highly depreciated.
199 * After the atmel_mci.c driver for AVR32 has
200 * been replaced this structure will be removed.
201 */
Andy Fleming1de97f92008-10-30 16:31:39 -0500202struct mmc_csd
203{
204 u8 csd_structure:2,
205 spec_vers:4,
206 rsvd1:2;
207 u8 taac;
208 u8 nsac;
209 u8 tran_speed;
210 u16 ccc:12,
211 read_bl_len:4;
212 u64 read_bl_partial:1,
213 write_blk_misalign:1,
214 read_blk_misalign:1,
215 dsr_imp:1,
216 rsvd2:2,
217 c_size:12,
218 vdd_r_curr_min:3,
219 vdd_r_curr_max:3,
220 vdd_w_curr_min:3,
221 vdd_w_curr_max:3,
222 c_size_mult:3,
223 sector_size:5,
224 erase_grp_size:5,
225 wp_grp_size:5,
226 wp_grp_enable:1,
227 default_ecc:2,
228 r2w_factor:3,
229 write_bl_len:4,
230 write_bl_partial:1,
231 rsvd3:5;
232 u8 file_format_grp:1,
233 copy:1,
234 perm_write_protect:1,
235 tmp_write_protect:1,
236 file_format:2,
237 ecc:2;
238 u8 crc:7;
239 u8 one:1;
240};
241
Andy Fleming272cc702008-10-30 16:41:01 -0500242struct mmc_cmd {
243 ushort cmdidx;
244 uint resp_type;
245 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530246 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500247 uint flags;
248};
249
250struct mmc_data {
251 union {
252 char *dest;
253 const char *src; /* src buffers don't get written to */
254 };
255 uint flags;
256 uint blocks;
257 uint blocksize;
258};
259
260struct mmc {
261 struct list_head link;
262 char name[32];
263 void *priv;
264 uint voltages;
265 uint version;
266 uint f_min;
267 uint f_max;
268 int high_capacity;
269 uint bus_width;
270 uint clock;
271 uint card_caps;
272 uint host_caps;
273 uint ocr;
274 uint scr[2];
275 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530276 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500277 ushort rca;
278 uint tran_speed;
279 uint read_bl_len;
280 uint write_bl_len;
281 u64 capacity;
282 block_dev_desc_t block_dev;
283 int (*send_cmd)(struct mmc *mmc,
284 struct mmc_cmd *cmd, struct mmc_data *data);
285 void (*set_ios)(struct mmc *mmc);
286 int (*init)(struct mmc *mmc);
Sandeep Paulraj57418d22010-12-20 20:01:21 -0500287 uint b_max;
Andy Fleming272cc702008-10-30 16:41:01 -0500288};
289
290int mmc_register(struct mmc *mmc);
291int mmc_initialize(bd_t *bis);
292int mmc_init(struct mmc *mmc);
293int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Jerry Huang4a6ee172010-11-25 17:06:07 +0000294void mmc_set_clock(struct mmc *mmc, uint clock);
Andy Fleming272cc702008-10-30 16:41:01 -0500295struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700296int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500297void print_mmc_devices(char separator);
Lei Wenea6ebe22011-05-02 16:26:25 +0000298int get_mmc_num(void);
Stefano Babic11fdade2010-02-05 15:04:43 +0100299int board_mmc_getcd(u8 *cd, struct mmc *mmc);
Andy Fleming272cc702008-10-30 16:41:01 -0500300
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200301#ifdef CONFIG_GENERIC_MMC
302int atmel_mci_init(void *regs);
Thomas Choud52ebf12010-12-24 13:12:21 +0000303#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
304struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200305#else
Andy Fleming272cc702008-10-30 16:41:01 -0500306int mmc_legacy_init(int verbose);
307#endif
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200308
wdenk71f95112003-06-15 22:40:42 +0000309#endif /* _MMC_H_ */