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gerrit.nordix.org / fdio / vpp / 31a367417e1ac5e60d1d39001293a12e332e492f / . / dpdk / dpdk-16.04_patches / 0017-NXP-DPAA2-Poll-Mode-Driver-Support.patch
blob: 2553997c7b874f1ac81112480da1052b9615f7e4 [file] [log] [blame]
Sachinbd05e172016-06-17 14:18:19 +0530[diff] [blame]1From b8d83a0825f2d7d0d626c00f79de7b415f8dc344 Mon Sep 17 00:00:00 2001
2From: Sachin Saxena <sachin.saxena@nxp.com>
3Date: Fri, 17 Jun 2016 12:32:28 +0530
4Subject: [PATCH 17/17] NXP DPAA2 Poll Mode Driver Support
5
6 Upstreaming of DPAA2 driver changes is in progress.This patch will
7 temporary add the support in VPP in built DPDK.
8
9 Two types of changes:
10 1. Driver specfic independent files. No impact on any other functionality.
11 2. Changes in common EAL framework. These changes are done in compile time DPAA2
12 specific flag, so no impact is expected on other existing features if not
13 compiling for DPAA2.
14
15Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com>
16---
17 config/defconfig_arm64-dpaa2-linuxapp-gcc | 61 +
18 drivers/net/Makefile | 1 +
19 drivers/net/dpaa2/Makefile | 102 +
20 drivers/net/dpaa2/dpaa2_logs.h | 77 +
21 drivers/net/dpaa2/mc/dpaiop.c | 457 ++++
22 drivers/net/dpaa2/mc/dpbp.c | 432 ++++
23 drivers/net/dpaa2/mc/dpci.c | 501 ++++
24 drivers/net/dpaa2/mc/dpcon.c | 401 +++
25 drivers/net/dpaa2/mc/dpdbg.c | 547 +++++
26 drivers/net/dpaa2/mc/dpdcei.c | 449 ++++
27 drivers/net/dpaa2/mc/dpdmai.c | 452 ++++
28 drivers/net/dpaa2/mc/dpdmux.c | 567 +++++
29 drivers/net/dpaa2/mc/dpio.c | 468 ++++
30 drivers/net/dpaa2/mc/dpmac.c | 422 ++++
31 drivers/net/dpaa2/mc/dpmcp.c | 312 +++
32 drivers/net/dpaa2/mc/dpmng.c | 58 +
33 drivers/net/dpaa2/mc/dpni.c | 1907 +++++++++++++++
34 drivers/net/dpaa2/mc/dprc.c | 786 ++++++
35 drivers/net/dpaa2/mc/dprtc.c | 509 ++++
36 drivers/net/dpaa2/mc/dpseci.c | 502 ++++
37 drivers/net/dpaa2/mc/dpsw.c | 1639 +++++++++++++
38 drivers/net/dpaa2/mc/fsl_dpaiop.h | 494 ++++
39 drivers/net/dpaa2/mc/fsl_dpaiop_cmd.h | 190 ++
40 drivers/net/dpaa2/mc/fsl_dpbp.h | 438 ++++
41 drivers/net/dpaa2/mc/fsl_dpbp_cmd.h | 172 ++
42 drivers/net/dpaa2/mc/fsl_dpci.h | 594 +++++
43 drivers/net/dpaa2/mc/fsl_dpci_cmd.h | 200 ++
44 drivers/net/dpaa2/mc/fsl_dpcon.h | 407 +++
45 drivers/net/dpaa2/mc/fsl_dpcon_cmd.h | 162 ++
46 drivers/net/dpaa2/mc/fsl_dpdbg.h | 635 +++++
47 drivers/net/dpaa2/mc/fsl_dpdbg_cmd.h | 249 ++
48 drivers/net/dpaa2/mc/fsl_dpdcei.h | 515 ++++
49 drivers/net/dpaa2/mc/fsl_dpdcei_cmd.h | 182 ++
50 drivers/net/dpaa2/mc/fsl_dpdmai.h | 521 ++++
51 drivers/net/dpaa2/mc/fsl_dpdmai_cmd.h | 191 ++
52 drivers/net/dpaa2/mc/fsl_dpdmux.h | 724 ++++++
53 drivers/net/dpaa2/mc/fsl_dpdmux_cmd.h | 256 ++
54 drivers/net/dpaa2/mc/fsl_dpio.h | 460 ++++
55 drivers/net/dpaa2/mc/fsl_dpio_cmd.h | 184 ++
56 drivers/net/dpaa2/mc/fsl_dpkg.h | 174 ++
57 drivers/net/dpaa2/mc/fsl_dpmac.h | 593 +++++
58 drivers/net/dpaa2/mc/fsl_dpmac_cmd.h | 195 ++
59 drivers/net/dpaa2/mc/fsl_dpmcp.h | 332 +++
60 drivers/net/dpaa2/mc/fsl_dpmcp_cmd.h | 135 +
61 drivers/net/dpaa2/mc/fsl_dpmng.h | 74 +
62 drivers/net/dpaa2/mc/fsl_dpmng_cmd.h | 46 +
63 drivers/net/dpaa2/mc/fsl_dpni.h | 2581 ++++++++++++++++++++
64 drivers/net/dpaa2/mc/fsl_dpni_cmd.h | 1058 ++++++++
65 drivers/net/dpaa2/mc/fsl_dprc.h | 1032 ++++++++
66 drivers/net/dpaa2/mc/fsl_dprc_cmd.h | 755 ++++++
67 drivers/net/dpaa2/mc/fsl_dprtc.h | 434 ++++
68 drivers/net/dpaa2/mc/fsl_dprtc_cmd.h | 181 ++
69 drivers/net/dpaa2/mc/fsl_dpseci.h | 647 +++++
70 drivers/net/dpaa2/mc/fsl_dpseci_cmd.h | 241 ++
71 drivers/net/dpaa2/mc/fsl_dpsw.h | 2164 ++++++++++++++++
72 drivers/net/dpaa2/mc/fsl_dpsw_cmd.h | 916 +++++++
73 drivers/net/dpaa2/mc/fsl_mc_cmd.h | 221 ++
74 drivers/net/dpaa2/mc/fsl_mc_sys.h | 95 +
75 drivers/net/dpaa2/mc/fsl_net.h | 480 ++++
76 drivers/net/dpaa2/mc/mc_sys.c | 129 +
77 drivers/net/dpaa2/qbman/driver/qbman_debug.c | 926 +++++++
78 drivers/net/dpaa2/qbman/driver/qbman_debug.h | 140 ++
79 drivers/net/dpaa2/qbman/driver/qbman_portal.c | 1407 +++++++++++
80 drivers/net/dpaa2/qbman/driver/qbman_portal.h | 266 ++
81 drivers/net/dpaa2/qbman/driver/qbman_private.h | 165 ++
82 drivers/net/dpaa2/qbman/driver/qbman_sys.h | 367 +++
83 drivers/net/dpaa2/qbman/driver/qbman_sys_decl.h | 68 +
84 drivers/net/dpaa2/qbman/include/compat.h | 597 +++++
85 .../dpaa2/qbman/include/drivers/fsl_qbman_base.h | 151 ++
86 .../dpaa2/qbman/include/drivers/fsl_qbman_portal.h | 1089 +++++++++
87 drivers/net/dpaa2/rte_eth_dpaa2_pvt.h | 313 +++
88 drivers/net/dpaa2/rte_eth_dpbp.c | 430 ++++
89 drivers/net/dpaa2/rte_eth_dpio.c | 339 +++
90 drivers/net/dpaa2/rte_eth_dpni.c | 2230 +++++++++++++++++
91 drivers/net/dpaa2/rte_eth_dpni_annot.h | 311 +++
92 drivers/net/dpaa2/rte_pmd_dpaa2_version.map | 4 +
93 lib/librte_eal/common/eal_private.h | 12 +
94 lib/librte_eal/linuxapp/eal/Makefile | 11 +
95 lib/librte_eal/linuxapp/eal/eal.c | 10 +
96 lib/librte_eal/linuxapp/eal/eal_soc.c | 84 +
97 lib/librte_eal/linuxapp/eal/eal_vfio_fsl_mc.c | 653 +++++
98 lib/librte_eal/linuxapp/eal/eal_vfio_fsl_mc.h | 102 +
99 lib/librte_mbuf/Makefile | 4 +
100 lib/librte_mbuf/rte_mbuf.c | 67 +
101 lib/librte_mempool/Makefile | 4 +
102 lib/librte_mempool/rte_mempool.c | 13 +
103 lib/librte_mempool/rte_mempool.h | 30 +-
104 mk/machine/dpaa2/rte.vars.mk | 60 +
105 mk/rte.app.mk | 1 +
106 89 files changed, 39560 insertions(+), 1 deletion(-)
107 create mode 100644 config/defconfig_arm64-dpaa2-linuxapp-gcc
108 create mode 100644 drivers/net/dpaa2/Makefile
109 create mode 100644 drivers/net/dpaa2/dpaa2_logs.h
110 create mode 100644 drivers/net/dpaa2/mc/dpaiop.c
111 create mode 100644 drivers/net/dpaa2/mc/dpbp.c
112 create mode 100644 drivers/net/dpaa2/mc/dpci.c
113 create mode 100644 drivers/net/dpaa2/mc/dpcon.c
114 create mode 100644 drivers/net/dpaa2/mc/dpdbg.c
115 create mode 100644 drivers/net/dpaa2/mc/dpdcei.c
116 create mode 100644 drivers/net/dpaa2/mc/dpdmai.c
117 create mode 100644 drivers/net/dpaa2/mc/dpdmux.c
118 create mode 100644 drivers/net/dpaa2/mc/dpio.c
119 create mode 100644 drivers/net/dpaa2/mc/dpmac.c
120 create mode 100644 drivers/net/dpaa2/mc/dpmcp.c
121 create mode 100644 drivers/net/dpaa2/mc/dpmng.c
122 create mode 100644 drivers/net/dpaa2/mc/dpni.c
123 create mode 100644 drivers/net/dpaa2/mc/dprc.c
124 create mode 100644 drivers/net/dpaa2/mc/dprtc.c
125 create mode 100644 drivers/net/dpaa2/mc/dpseci.c
126 create mode 100644 drivers/net/dpaa2/mc/dpsw.c
127 create mode 100644 drivers/net/dpaa2/mc/fsl_dpaiop.h
128 create mode 100644 drivers/net/dpaa2/mc/fsl_dpaiop_cmd.h
129 create mode 100644 drivers/net/dpaa2/mc/fsl_dpbp.h
130 create mode 100644 drivers/net/dpaa2/mc/fsl_dpbp_cmd.h
131 create mode 100644 drivers/net/dpaa2/mc/fsl_dpci.h
132 create mode 100644 drivers/net/dpaa2/mc/fsl_dpci_cmd.h
133 create mode 100644 drivers/net/dpaa2/mc/fsl_dpcon.h
134 create mode 100644 drivers/net/dpaa2/mc/fsl_dpcon_cmd.h
135 create mode 100644 drivers/net/dpaa2/mc/fsl_dpdbg.h
136 create mode 100644 drivers/net/dpaa2/mc/fsl_dpdbg_cmd.h
137 create mode 100644 drivers/net/dpaa2/mc/fsl_dpdcei.h
138 create mode 100644 drivers/net/dpaa2/mc/fsl_dpdcei_cmd.h
139 create mode 100644 drivers/net/dpaa2/mc/fsl_dpdmai.h
140 create mode 100644 drivers/net/dpaa2/mc/fsl_dpdmai_cmd.h
141 create mode 100644 drivers/net/dpaa2/mc/fsl_dpdmux.h
142 create mode 100644 drivers/net/dpaa2/mc/fsl_dpdmux_cmd.h
143 create mode 100644 drivers/net/dpaa2/mc/fsl_dpio.h
144 create mode 100644 drivers/net/dpaa2/mc/fsl_dpio_cmd.h
145 create mode 100644 drivers/net/dpaa2/mc/fsl_dpkg.h
146 create mode 100644 drivers/net/dpaa2/mc/fsl_dpmac.h
147 create mode 100644 drivers/net/dpaa2/mc/fsl_dpmac_cmd.h
148 create mode 100644 drivers/net/dpaa2/mc/fsl_dpmcp.h
149 create mode 100644 drivers/net/dpaa2/mc/fsl_dpmcp_cmd.h
150 create mode 100644 drivers/net/dpaa2/mc/fsl_dpmng.h
151 create mode 100644 drivers/net/dpaa2/mc/fsl_dpmng_cmd.h
152 create mode 100644 drivers/net/dpaa2/mc/fsl_dpni.h
153 create mode 100644 drivers/net/dpaa2/mc/fsl_dpni_cmd.h
154 create mode 100644 drivers/net/dpaa2/mc/fsl_dprc.h
155 create mode 100644 drivers/net/dpaa2/mc/fsl_dprc_cmd.h
156 create mode 100644 drivers/net/dpaa2/mc/fsl_dprtc.h
157 create mode 100644 drivers/net/dpaa2/mc/fsl_dprtc_cmd.h
158 create mode 100644 drivers/net/dpaa2/mc/fsl_dpseci.h
159 create mode 100644 drivers/net/dpaa2/mc/fsl_dpseci_cmd.h
160 create mode 100644 drivers/net/dpaa2/mc/fsl_dpsw.h
161 create mode 100644 drivers/net/dpaa2/mc/fsl_dpsw_cmd.h
162 create mode 100644 drivers/net/dpaa2/mc/fsl_mc_cmd.h
163 create mode 100644 drivers/net/dpaa2/mc/fsl_mc_sys.h
164 create mode 100644 drivers/net/dpaa2/mc/fsl_net.h
165 create mode 100644 drivers/net/dpaa2/mc/mc_sys.c
166 create mode 100644 drivers/net/dpaa2/qbman/driver/qbman_debug.c
167 create mode 100644 drivers/net/dpaa2/qbman/driver/qbman_debug.h
168 create mode 100644 drivers/net/dpaa2/qbman/driver/qbman_portal.c
169 create mode 100644 drivers/net/dpaa2/qbman/driver/qbman_portal.h
170 create mode 100644 drivers/net/dpaa2/qbman/driver/qbman_private.h
171 create mode 100644 drivers/net/dpaa2/qbman/driver/qbman_sys.h
172 create mode 100644 drivers/net/dpaa2/qbman/driver/qbman_sys_decl.h
173 create mode 100644 drivers/net/dpaa2/qbman/include/compat.h
174 create mode 100644 drivers/net/dpaa2/qbman/include/drivers/fsl_qbman_base.h
175 create mode 100644 drivers/net/dpaa2/qbman/include/drivers/fsl_qbman_portal.h
176 create mode 100644 drivers/net/dpaa2/rte_eth_dpaa2_pvt.h
177 create mode 100644 drivers/net/dpaa2/rte_eth_dpbp.c
178 create mode 100644 drivers/net/dpaa2/rte_eth_dpio.c
179 create mode 100644 drivers/net/dpaa2/rte_eth_dpni.c
180 create mode 100644 drivers/net/dpaa2/rte_eth_dpni_annot.h
181 create mode 100644 drivers/net/dpaa2/rte_pmd_dpaa2_version.map
182 create mode 100644 lib/librte_eal/linuxapp/eal/eal_soc.c
183 create mode 100644 lib/librte_eal/linuxapp/eal/eal_vfio_fsl_mc.c
184 create mode 100644 lib/librte_eal/linuxapp/eal/eal_vfio_fsl_mc.h
185 create mode 100644 mk/machine/dpaa2/rte.vars.mk
186
187diff --git a/config/defconfig_arm64-dpaa2-linuxapp-gcc b/config/defconfig_arm64-dpaa2-linuxapp-gcc
188new file mode 100644
189index 0000000..fafbef4
190--- /dev/null
191+++ b/config/defconfig_arm64-dpaa2-linuxapp-gcc
192@@ -0,0 +1,61 @@
193+# BSD LICENSE
194+#
195+# Copyright(c) 2016 Freescale Semiconductor, Inc. All rights reserved.
196+#
197+# Redistribution and use in source and binary forms, with or without
198+# modification, are permitted provided that the following conditions
199+# are met:
200+#
201+# * Redistributions of source code must retain the above copyright
202+# notice, this list of conditions and the following disclaimer.
203+# * Redistributions in binary form must reproduce the above copyright
204+# notice, this list of conditions and the following disclaimer in
205+# the documentation and/or other materials provided with the
206+# distribution.
207+# * Neither the name of Freescale Semiconductor nor the names of its
208+# contributors may be used to endorse or promote products derived
209+# from this software without specific prior written permission.
210+#
211+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
212+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
213+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
214+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
215+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
216+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
217+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
218+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
219+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
220+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
221+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
222+#
223+
224+#include "defconfig_arm64-armv8a-linuxapp-gcc"
225+
226+# NXP (Freescale) - Soc Architecture with WRIOP and QBMAN support
227+CONFIG_RTE_MACHINE="dpaa2"
228+CONFIG_RTE_ARCH_ARM_TUNE="cortex-a57+fp+simd"
229+
230+#
231+# Compile Environment Abstraction Layer
232+#
233+CONFIG_RTE_MAX_LCORE=8
234+CONFIG_RTE_MAX_NUMA_NODES=1
235+
236+# Compile software PMD backed by FSL DPAA2 files
237+#
238+CONFIG_RTE_LIBRTE_DPAA2_PMD=y
239+CONFIG_RTE_LIBRTE_DPAA2_USE_PHYS_IOVA=n
240+CONFIG_RTE_LIBRTE_DPAA2_DEBUG_INIT=n
241+CONFIG_RTE_LIBRTE_DPAA2_DEBUG_DRIVER=n
242+CONFIG_RTE_LIBRTE_ETHDEV_DEBUG=n
243+
244+CONFIG_RTE_LIBRTE_PMD_BOND=y
245+CONFIG_RTE_CACHE_LINE_SIZE=128
246+CONFIG_RTE_EAL_IGB_UIO=n
247+CONFIG_RTE_LIBRTE_KNI=n
248+
249+#FSL DPAA2 caam driver
250+CONFIG_RTE_LIBRTE_PMD_DPAA2_CAAM=n
251+CONFIG_RTE_LIBRTE_DPAA2_CAAM_DEBUG_INIT=n
252+CONFIG_RTE_LIBRTE_DPAA2_CAAM_DEBUG_DRIVER=n
253+CONFIG_RTE_LIBRTE_DPAA2_CAAM_DEBUG_RX=n
254diff --git a/drivers/net/Makefile b/drivers/net/Makefile
255index 3386a67..ed10351 100644
256--- a/drivers/net/Makefile
257+++ b/drivers/net/Makefile
258@@ -52,6 +52,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_SZEDATA2) += szedata2
259 DIRS-$(CONFIG_RTE_LIBRTE_VIRTIO_PMD) += virtio
260 DIRS-$(CONFIG_RTE_LIBRTE_VMXNET3_PMD) += vmxnet3
261 DIRS-$(CONFIG_RTE_LIBRTE_PMD_XENVIRT) += xenvirt
262+DIRS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += dpaa2
263
264 ifeq ($(CONFIG_RTE_LIBRTE_VHOST),y)
265 DIRS-$(CONFIG_RTE_LIBRTE_PMD_VHOST) += vhost
266diff --git a/drivers/net/dpaa2/Makefile b/drivers/net/dpaa2/Makefile
267new file mode 100644
268index 0000000..3cf1782
269--- /dev/null
270+++ b/drivers/net/dpaa2/Makefile
271@@ -0,0 +1,102 @@
272+# BSD LICENSE
273+#
274+# Copyright (c) 2014 Freescale Semiconductor, Inc. All rights reserved.
275+#
276+# Redistribution and use in source and binary forms, with or without
277+# modification, are permitted provided that the following conditions
278+# are met:
279+#
280+# * Redistributions of source code must retain the above copyright
281+# notice, this list of conditions and the following disclaimer.
282+# * Redistributions in binary form must reproduce the above copyright
283+# notice, this list of conditions and the following disclaimer in
284+# the documentation and/or other materials provided with the
285+# distribution.
286+# * Neither the name of Freescale Semiconductor nor the names of its
287+# contributors may be used to endorse or promote products derived
288+# from this software without specific prior written permission.
289+#
290+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
291+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
292+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
293+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
294+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
295+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
296+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
297+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
298+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
299+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
300+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
301+
302+include $(RTE_SDK)/mk/rte.vars.mk
303+
304+#
305+# library name
306+#
307+LIB = librte_pmd_dpaa2.a
308+
309+ifeq ($(CONFIG_RTE_LIBRTE_DPAA2_DEBUG_INIT),y)
310+CFLAGS += -O0 -g
311+CFLAGS += "-Wno-error"
312+else
313+CFLAGS += -O3 -g
314+CFLAGS += $(WERROR_FLAGS)
315+endif
316+CFLAGS +=-Wno-strict-aliasing
317+CFLAGS +=-Wno-missing-prototypes
318+CFLAGS +=-Wno-missing-declarations
319+CFLAGS +=-Wno-unused-function
320+
321+CFLAGS += -I$(RTE_SDK)/drivers/net/dpaa2/mc
322+CFLAGS += -I$(RTE_SDK)/drivers/net/dpaa2/qbman/include
323+CFLAGS += -I$(RTE_SDK)/drivers/net/dpaa2/qbman/include/drivers
324+CFLAGS += -I$(RTE_SDK)/drivers/net/dpaa2/driver/
325+CFLAGS += -I$(RTE_SDK)/lib/librte_eal/common/include
326+CFLAGS += -I$(RTE_SDK)/lib/librte_ether
327+CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal
328+
329+EXPORT_MAP := rte_pmd_dpaa2_version.map
330+
331+LIBABIVER := 1
332+#
333+# all source are stored in SRCS-y
334+#
335+SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += \
336+ mc/dprc.c \
337+ mc/dprtc.o \
338+ mc/dpaiop.c \
339+ mc/dpdbg.o \
340+ mc/dpdcei.c \
341+ mc/dpdmai.c \
342+ mc/dpmac.c \
343+ mc/dpmcp.c \
344+ mc/dpbp.c \
345+ mc/dpio.c \
346+ mc/dpni.c \
347+ mc/dpsw.c \
348+ mc/dpci.c \
349+ mc/dpcon.c \
350+ mc/dpseci.c \
351+ mc/dpmng.c \
352+ mc/dpdmux.c \
353+ mc/mc_sys.c
354+
355+#
356+# all source are stored in SRCS-y
357+#
358+SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += \
359+ qbman/driver/qbman_portal.c \
360+ qbman/driver/qbman_debug.c
361+
362+SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += rte_eth_dpni.c
363+SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += rte_eth_dpio.c
364+SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += rte_eth_dpbp.c
365+
366+#
367+# Export include files
368+#
369+SYMLINK-y-include +=
370+
371+# this lib depends upon:
372+DEPDIRS-y += lib/librte_eal
373+include $(RTE_SDK)/mk/rte.lib.mk
374diff --git a/drivers/net/dpaa2/dpaa2_logs.h b/drivers/net/dpaa2/dpaa2_logs.h
375new file mode 100644
376index 0000000..319786a
377--- /dev/null
378+++ b/drivers/net/dpaa2/dpaa2_logs.h
379@@ -0,0 +1,77 @@
380+/*-
381+ * BSD LICENSE
382+ *
383+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
384+ *
385+ * Redistribution and use in source and binary forms, with or without
386+ * modification, are permitted provided that the following conditions
387+ * are met:
388+ *
389+ * * Redistributions of source code must retain the above copyright
390+ * notice, this list of conditions and the following disclaimer.
391+ * * Redistributions in binary form must reproduce the above copyright
392+ * notice, this list of conditions and the following disclaimer in
393+ * the documentation and/or other materials provided with the
394+ * distribution.
395+ * * Neither the name of Freescale Semiconductor, Inc nor the names of its
396+ * contributors may be used to endorse or promote products derived
397+ * from this software without specific prior written permission.
398+ *
399+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
400+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
401+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
402+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
403+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
404+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
405+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
406+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
407+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
408+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
409+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
410+ */
411+
412+
413+#ifndef _DPAA2_LOGS_H_
414+#define _DPAA2_LOGS_H_
415+
416+#define PMD_INIT_LOG(level, fmt, args...) \
417+ RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ##args)
418+
419+#ifdef RTE_LIBRTE_DPAA2_DEBUG_INIT
420+#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, " >>")
421+#else
422+#define PMD_INIT_FUNC_TRACE() do { } while (0)
423+#endif
424+
425+#ifdef RTE_LIBRTE_DPAA2_DEBUG_RX
426+#define PMD_RX_LOG(level, fmt, args...) \
427+ RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
428+#else
429+#define PMD_RX_LOG(level, fmt, args...) do { } while(0)
430+#endif
431+
432+#ifdef RTE_LIBRTE_DPAA2_DEBUG_TX
433+#define PMD_TX_LOG(level, fmt, args...) \
434+ RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
435+#else
436+#define PMD_TX_LOG(level, fmt, args...) do { } while(0)
437+#endif
438+
439+#ifdef RTE_LIBRTE_DPAA2_DEBUG_TX_FREE
440+#define PMD_TX_FREE_LOG(level, fmt, args...) \
441+ RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
442+#else
443+#define PMD_TX_FREE_LOG(level, fmt, args...) do { } while(0)
444+#endif
445+
446+#ifdef RTE_LIBRTE_DPAA2_DEBUG_DRIVER
447+#define PMD_DRV_LOG_RAW(level, fmt, args...) \
448+ RTE_LOG(level, PMD, "%s(): " fmt, __func__, ## args)
449+#else
450+#define PMD_DRV_LOG_RAW(level, fmt, args...) do { } while (0)
451+#endif
452+
453+#define PMD_DRV_LOG(level, fmt, args...) \
454+ PMD_DRV_LOG_RAW(level, fmt "\n", ## args)
455+
456+#endif /* _DPAA2_LOGS_H_ */
457diff --git a/drivers/net/dpaa2/mc/dpaiop.c b/drivers/net/dpaa2/mc/dpaiop.c
458new file mode 100644
459index 0000000..7c1ecff
460--- /dev/null
461+++ b/drivers/net/dpaa2/mc/dpaiop.c
462@@ -0,0 +1,457 @@
463+/* Copyright 2013-2015 Freescale Semiconductor Inc.
464+ *
465+ * Redistribution and use in source and binary forms, with or without
466+ * modification, are permitted provided that the following conditions are met:
467+ * * Redistributions of source code must retain the above copyright
468+ * notice, this list of conditions and the following disclaimer.
469+ * * Redistributions in binary form must reproduce the above copyright
470+ * notice, this list of conditions and the following disclaimer in the
471+ * documentation and/or other materials provided with the distribution.
472+ * * Neither the name of the above-listed copyright holders nor the
473+ * names of any contributors may be used to endorse or promote products
474+ * derived from this software without specific prior written permission.
475+ *
476+ *
477+ * ALTERNATIVELY, this software may be distributed under the terms of the
478+ * GNU General Public License ("GPL") as published by the Free Software
479+ * Foundation, either version 2 of that License or (at your option) any
480+ * later version.
481+ *
482+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
483+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
484+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
485+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
486+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
487+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
488+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
489+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
490+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
491+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
492+ * POSSIBILITY OF SUCH DAMAGE.
493+ */
494+#include <fsl_mc_sys.h>
495+#include <fsl_mc_cmd.h>
496+#include <fsl_dpaiop.h>
497+#include <fsl_dpaiop_cmd.h>
498+
499+int dpaiop_open(struct fsl_mc_io *mc_io,
500+ uint32_t cmd_flags,
501+ int dpaiop_id,
502+ uint16_t *token)
503+{
504+ struct mc_command cmd = { 0 };
505+ int err;
506+
507+ /* prepare command */
508+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_OPEN,
509+ cmd_flags,
510+ 0);
511+ DPAIOP_CMD_OPEN(cmd, dpaiop_id);
512+
513+ /* send command to mc*/
514+ err = mc_send_command(mc_io, &cmd);
515+ if (err)
516+ return err;
517+
518+ /* retrieve response parameters */
519+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
520+
521+ return err;
522+}
523+
524+int dpaiop_close(struct fsl_mc_io *mc_io,
525+ uint32_t cmd_flags,
526+ uint16_t token)
527+{
528+ struct mc_command cmd = { 0 };
529+
530+ /* prepare command */
531+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_CLOSE, cmd_flags,
532+ token);
533+
534+ /* send command to mc*/
535+ return mc_send_command(mc_io, &cmd);
536+}
537+
538+int dpaiop_create(struct fsl_mc_io *mc_io,
539+ uint32_t cmd_flags,
540+ const struct dpaiop_cfg *cfg,
541+ uint16_t *token)
542+{
543+ struct mc_command cmd = { 0 };
544+ int err;
545+
546+ (void)(cfg); /* unused */
547+
548+ /* prepare command */
549+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_CREATE,
550+ cmd_flags,
551+ 0);
552+ DPAIOP_CMD_CREATE(cmd, cfg);
553+
554+ /* send command to mc*/
555+ err = mc_send_command(mc_io, &cmd);
556+ if (err)
557+ return err;
558+
559+ /* retrieve response parameters */
560+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
561+
562+ return 0;
563+}
564+
565+int dpaiop_destroy(struct fsl_mc_io *mc_io,
566+ uint32_t cmd_flags,
567+ uint16_t token)
568+{
569+ struct mc_command cmd = { 0 };
570+
571+ /* prepare command */
572+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_DESTROY,
573+ cmd_flags,
574+ token);
575+
576+ /* send command to mc*/
577+ return mc_send_command(mc_io, &cmd);
578+}
579+
580+int dpaiop_reset(struct fsl_mc_io *mc_io,
581+ uint32_t cmd_flags,
582+ uint16_t token)
583+{
584+ struct mc_command cmd = { 0 };
585+
586+ /* prepare command */
587+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_RESET,
588+ cmd_flags,
589+ token);
590+
591+ /* send command to mc*/
592+ return mc_send_command(mc_io, &cmd);
593+}
594+
595+int dpaiop_set_irq(struct fsl_mc_io *mc_io,
596+ uint32_t cmd_flags,
597+ uint16_t token,
598+ uint8_t irq_index,
599+ struct dpaiop_irq_cfg *irq_cfg)
600+{
601+ struct mc_command cmd = { 0 };
602+
603+ /* prepare command */
604+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_SET_IRQ,
605+ cmd_flags,
606+ token);
607+
608+ DPAIOP_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
609+
610+ /* send command to mc*/
611+ return mc_send_command(mc_io, &cmd);
612+}
613+
614+int dpaiop_get_irq(struct fsl_mc_io *mc_io,
615+ uint32_t cmd_flags,
616+ uint16_t token,
617+ uint8_t irq_index,
618+ int *type,
619+ struct dpaiop_irq_cfg *irq_cfg)
620+{
621+ struct mc_command cmd = { 0 };
622+ int err;
623+
624+ /* prepare command */
625+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_GET_IRQ,
626+ cmd_flags,
627+ token);
628+
629+ DPAIOP_CMD_GET_IRQ(cmd, irq_index);
630+
631+ /* send command to mc*/
632+ err = mc_send_command(mc_io, &cmd);
633+ if (err)
634+ return err;
635+
636+ /* retrieve response parameters */
637+ DPAIOP_RSP_GET_IRQ(cmd, *type, irq_cfg);
638+
639+ return 0;
640+}
641+
642+int dpaiop_set_irq_enable(struct fsl_mc_io *mc_io,
643+ uint32_t cmd_flags,
644+ uint16_t token,
645+ uint8_t irq_index,
646+ uint8_t en)
647+{
648+ struct mc_command cmd = { 0 };
649+
650+ /* prepare command */
651+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_SET_IRQ_ENABLE,
652+ cmd_flags,
653+ token);
654+
655+ DPAIOP_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
656+
657+ /* send command to mc*/
658+ return mc_send_command(mc_io, &cmd);
659+}
660+
661+int dpaiop_get_irq_enable(struct fsl_mc_io *mc_io,
662+ uint32_t cmd_flags,
663+ uint16_t token,
664+ uint8_t irq_index,
665+ uint8_t *en)
666+{
667+ struct mc_command cmd = { 0 };
668+ int err;
669+
670+ /* prepare command */
671+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_GET_IRQ_ENABLE,
672+ cmd_flags,
673+ token);
674+
675+ DPAIOP_CMD_GET_IRQ_ENABLE(cmd, irq_index);
676+
677+ /* send command to mc*/
678+ err = mc_send_command(mc_io, &cmd);
679+ if (err)
680+ return err;
681+
682+ /* retrieve response parameters */
683+ DPAIOP_RSP_GET_IRQ_ENABLE(cmd, *en);
684+
685+ return 0;
686+}
687+
688+int dpaiop_set_irq_mask(struct fsl_mc_io *mc_io,
689+ uint32_t cmd_flags,
690+ uint16_t token,
691+ uint8_t irq_index,
692+ uint32_t mask)
693+{
694+ struct mc_command cmd = { 0 };
695+
696+ /* prepare command */
697+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_SET_IRQ_MASK,
698+ cmd_flags,
699+ token);
700+
701+ DPAIOP_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
702+
703+ /* send command to mc*/
704+ return mc_send_command(mc_io, &cmd);
705+}
706+
707+int dpaiop_get_irq_mask(struct fsl_mc_io *mc_io,
708+ uint32_t cmd_flags,
709+ uint16_t token,
710+ uint8_t irq_index,
711+ uint32_t *mask)
712+{
713+ struct mc_command cmd = { 0 };
714+ int err;
715+
716+ /* prepare command */
717+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_GET_IRQ_MASK,
718+ cmd_flags,
719+ token);
720+
721+ DPAIOP_CMD_GET_IRQ_MASK(cmd, irq_index);
722+
723+ /* send command to mc*/
724+ err = mc_send_command(mc_io, &cmd);
725+ if (err)
726+ return err;
727+
728+ /* retrieve response parameters */
729+ DPAIOP_RSP_GET_IRQ_MASK(cmd, *mask);
730+
731+ return 0;
732+}
733+
734+int dpaiop_get_irq_status(struct fsl_mc_io *mc_io,
735+ uint32_t cmd_flags,
736+ uint16_t token,
737+ uint8_t irq_index,
738+ uint32_t *status)
739+{
740+ struct mc_command cmd = { 0 };
741+ int err;
742+
743+ /* prepare command */
744+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_GET_IRQ_STATUS,
745+ cmd_flags,
746+ token);
747+ DPAIOP_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
748+
749+ /* send command to mc*/
750+ err = mc_send_command(mc_io, &cmd);
751+ if (err)
752+ return err;
753+
754+ /* retrieve response parameters */
755+ DPAIOP_RSP_GET_IRQ_STATUS(cmd, *status);
756+
757+ return 0;
758+}
759+
760+int dpaiop_clear_irq_status(struct fsl_mc_io *mc_io,
761+ uint32_t cmd_flags,
762+ uint16_t token,
763+ uint8_t irq_index,
764+ uint32_t status)
765+{
766+ struct mc_command cmd = { 0 };
767+
768+ /* prepare command */
769+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_CLEAR_IRQ_STATUS,
770+ cmd_flags,
771+ token);
772+ DPAIOP_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
773+
774+ /* send command to mc*/
775+ return mc_send_command(mc_io, &cmd);
776+}
777+
778+int dpaiop_get_attributes(struct fsl_mc_io *mc_io,
779+ uint32_t cmd_flags,
780+ uint16_t token,
781+ struct dpaiop_attr *attr)
782+{
783+ struct mc_command cmd = { 0 };
784+ int err;
785+
786+ /* prepare command */
787+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_GET_ATTR,
788+ cmd_flags,
789+ token);
790+
791+ /* send command to mc*/
792+ err = mc_send_command(mc_io, &cmd);
793+ if (err)
794+ return err;
795+
796+ /* retrieve response parameters */
797+ DPAIOP_RSP_GET_ATTRIBUTES(cmd, attr);
798+
799+ return 0;
800+}
801+
802+int dpaiop_load(struct fsl_mc_io *mc_io,
803+ uint32_t cmd_flags,
804+ uint16_t token,
805+ struct dpaiop_load_cfg *cfg)
806+{
807+ struct mc_command cmd = { 0 };
808+
809+ /* prepare command */
810+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_LOAD,
811+ cmd_flags,
812+ token);
813+ DPAIOP_CMD_LOAD(cmd, cfg);
814+
815+ /* send command to mc*/
816+ return mc_send_command(mc_io, &cmd);
817+}
818+
819+int dpaiop_run(struct fsl_mc_io *mc_io,
820+ uint32_t cmd_flags,
821+ uint16_t token,
822+ const struct dpaiop_run_cfg *cfg)
823+{
824+ struct mc_command cmd = { 0 };
825+
826+ /* prepare command */
827+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_RUN,
828+ cmd_flags,
829+ token);
830+ DPAIOP_CMD_RUN(cmd, cfg);
831+
832+ /* send command to mc*/
833+ return mc_send_command(mc_io, &cmd);
834+}
835+
836+int dpaiop_get_sl_version(struct fsl_mc_io *mc_io,
837+ uint32_t cmd_flags,
838+ uint16_t token,
839+ struct dpaiop_sl_version *version)
840+{
841+ struct mc_command cmd = { 0 };
842+ int err;
843+
844+ /* prepare command */
845+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_GET_SL_VERSION,
846+ cmd_flags,
847+ token);
848+
849+ /* send command to mc*/
850+ err = mc_send_command(mc_io, &cmd);
851+ if (err)
852+ return err;
853+
854+ /* retrieve response parameters */
855+ DPAIOP_RSP_GET_SL_VERSION(cmd, version);
856+
857+ return 0;
858+}
859+
860+int dpaiop_get_state(struct fsl_mc_io *mc_io,
861+ uint32_t cmd_flags,
862+ uint16_t token,
863+ uint32_t *state)
864+{
865+ struct mc_command cmd = { 0 };
866+ int err;
867+
868+ /* prepare command */
869+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_GET_STATE,
870+ cmd_flags,
871+ token);
872+
873+ /* send command to mc*/
874+ err = mc_send_command(mc_io, &cmd);
875+ if (err)
876+ return err;
877+
878+ /* retrieve response parameters */
879+ DPAIOP_RSP_GET_STATE(cmd, *state);
880+
881+ return 0;
882+}
883+
884+int dpaiop_set_time_of_day(struct fsl_mc_io *mc_io,
885+ uint32_t cmd_flags,
886+ uint16_t token,
887+ uint64_t time_of_day)
888+{
889+ struct mc_command cmd = { 0 };
890+
891+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_SET_TIME_OF_DAY,
892+ cmd_flags,
893+ token);
894+
895+ DPAIOP_CMD_SET_TIME_OF_DAY(cmd, time_of_day);
896+
897+ return mc_send_command(mc_io, &cmd);
898+}
899+
900+int dpaiop_get_time_of_day(struct fsl_mc_io *mc_io,
901+ uint32_t cmd_flags,
902+ uint16_t token,
903+ uint64_t *time_of_day)
904+{
905+ struct mc_command cmd = { 0 };
906+ int err;
907+
908+ cmd.header = mc_encode_cmd_header(DPAIOP_CMDID_GET_TIME_OF_DAY,
909+ cmd_flags,
910+ token);
911+
912+ err = mc_send_command(mc_io, &cmd);
913+ if (err)
914+ return err;
915+
916+ DPAIOP_RSP_GET_TIME_OF_DAY(cmd, *time_of_day);
917+
918+ return 0;
919+}
920diff --git a/drivers/net/dpaa2/mc/dpbp.c b/drivers/net/dpaa2/mc/dpbp.c
921new file mode 100644
922index 0000000..87899b8
923--- /dev/null
924+++ b/drivers/net/dpaa2/mc/dpbp.c
925@@ -0,0 +1,432 @@
926+/* Copyright 2013-2015 Freescale Semiconductor Inc.
927+ *
928+ * Redistribution and use in source and binary forms, with or without
929+ * modification, are permitted provided that the following conditions are met:
930+ * * Redistributions of source code must retain the above copyright
931+ * notice, this list of conditions and the following disclaimer.
932+ * * Redistributions in binary form must reproduce the above copyright
933+ * notice, this list of conditions and the following disclaimer in the
934+ * documentation and/or other materials provided with the distribution.
935+ * * Neither the name of the above-listed copyright holders nor the
936+ * names of any contributors may be used to endorse or promote products
937+ * derived from this software without specific prior written permission.
938+ *
939+ *
940+ * ALTERNATIVELY, this software may be distributed under the terms of the
941+ * GNU General Public License ("GPL") as published by the Free Software
942+ * Foundation, either version 2 of that License or (at your option) any
943+ * later version.
944+ *
945+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
946+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
947+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
948+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
949+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
950+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
951+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
952+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
953+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
954+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
955+ * POSSIBILITY OF SUCH DAMAGE.
956+ */
957+#include <fsl_mc_sys.h>
958+#include <fsl_mc_cmd.h>
959+#include <fsl_dpbp.h>
960+#include <fsl_dpbp_cmd.h>
961+
962+int dpbp_open(struct fsl_mc_io *mc_io,
963+ uint32_t cmd_flags,
964+ int dpbp_id,
965+ uint16_t *token)
966+{
967+ struct mc_command cmd = { 0 };
968+ int err;
969+
970+ /* prepare command */
971+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_OPEN,
972+ cmd_flags,
973+ 0);
974+ DPBP_CMD_OPEN(cmd, dpbp_id);
975+
976+ /* send command to mc*/
977+ err = mc_send_command(mc_io, &cmd);
978+ if (err)
979+ return err;
980+
981+ /* retrieve response parameters */
982+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
983+
984+ return err;
985+}
986+
987+int dpbp_close(struct fsl_mc_io *mc_io,
988+ uint32_t cmd_flags,
989+ uint16_t token)
990+{
991+ struct mc_command cmd = { 0 };
992+
993+ /* prepare command */
994+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLOSE, cmd_flags,
995+ token);
996+
997+ /* send command to mc*/
998+ return mc_send_command(mc_io, &cmd);
999+}
1000+
1001+int dpbp_create(struct fsl_mc_io *mc_io,
1002+ uint32_t cmd_flags,
1003+ const struct dpbp_cfg *cfg,
1004+ uint16_t *token)
1005+{
1006+ struct mc_command cmd = { 0 };
1007+ int err;
1008+
1009+ (void)(cfg); /* unused */
1010+
1011+ /* prepare command */
1012+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE,
1013+ cmd_flags,
1014+ 0);
1015+
1016+ /* send command to mc*/
1017+ err = mc_send_command(mc_io, &cmd);
1018+ if (err)
1019+ return err;
1020+
1021+ /* retrieve response parameters */
1022+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
1023+
1024+ return 0;
1025+}
1026+
1027+int dpbp_destroy(struct fsl_mc_io *mc_io,
1028+ uint32_t cmd_flags,
1029+ uint16_t token)
1030+{
1031+ struct mc_command cmd = { 0 };
1032+
1033+ /* prepare command */
1034+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY,
1035+ cmd_flags,
1036+ token);
1037+
1038+ /* send command to mc*/
1039+ return mc_send_command(mc_io, &cmd);
1040+}
1041+
1042+int dpbp_enable(struct fsl_mc_io *mc_io,
1043+ uint32_t cmd_flags,
1044+ uint16_t token)
1045+{
1046+ struct mc_command cmd = { 0 };
1047+
1048+ /* prepare command */
1049+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_ENABLE, cmd_flags,
1050+ token);
1051+
1052+ /* send command to mc*/
1053+ return mc_send_command(mc_io, &cmd);
1054+}
1055+
1056+int dpbp_disable(struct fsl_mc_io *mc_io,
1057+ uint32_t cmd_flags,
1058+ uint16_t token)
1059+{
1060+ struct mc_command cmd = { 0 };
1061+
1062+ /* prepare command */
1063+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_DISABLE,
1064+ cmd_flags,
1065+ token);
1066+
1067+ /* send command to mc*/
1068+ return mc_send_command(mc_io, &cmd);
1069+}
1070+
1071+int dpbp_is_enabled(struct fsl_mc_io *mc_io,
1072+ uint32_t cmd_flags,
1073+ uint16_t token,
1074+ int *en)
1075+{
1076+ struct mc_command cmd = { 0 };
1077+ int err;
1078+ /* prepare command */
1079+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_IS_ENABLED, cmd_flags,
1080+ token);
1081+
1082+ /* send command to mc*/
1083+ err = mc_send_command(mc_io, &cmd);
1084+ if (err)
1085+ return err;
1086+
1087+ /* retrieve response parameters */
1088+ DPBP_RSP_IS_ENABLED(cmd, *en);
1089+
1090+ return 0;
1091+}
1092+
1093+int dpbp_reset(struct fsl_mc_io *mc_io,
1094+ uint32_t cmd_flags,
1095+ uint16_t token)
1096+{
1097+ struct mc_command cmd = { 0 };
1098+
1099+ /* prepare command */
1100+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_RESET,
1101+ cmd_flags,
1102+ token);
1103+
1104+ /* send command to mc*/
1105+ return mc_send_command(mc_io, &cmd);
1106+}
1107+
1108+int dpbp_set_irq(struct fsl_mc_io *mc_io,
1109+ uint32_t cmd_flags,
1110+ uint16_t token,
1111+ uint8_t irq_index,
1112+ struct dpbp_irq_cfg *irq_cfg)
1113+{
1114+ struct mc_command cmd = { 0 };
1115+
1116+ /* prepare command */
1117+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ,
1118+ cmd_flags,
1119+ token);
1120+
1121+ DPBP_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
1122+
1123+ /* send command to mc*/
1124+ return mc_send_command(mc_io, &cmd);
1125+}
1126+
1127+int dpbp_get_irq(struct fsl_mc_io *mc_io,
1128+ uint32_t cmd_flags,
1129+ uint16_t token,
1130+ uint8_t irq_index,
1131+ int *type,
1132+ struct dpbp_irq_cfg *irq_cfg)
1133+{
1134+ struct mc_command cmd = { 0 };
1135+ int err;
1136+
1137+ /* prepare command */
1138+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ,
1139+ cmd_flags,
1140+ token);
1141+
1142+ DPBP_CMD_GET_IRQ(cmd, irq_index);
1143+
1144+ /* send command to mc*/
1145+ err = mc_send_command(mc_io, &cmd);
1146+ if (err)
1147+ return err;
1148+
1149+ /* retrieve response parameters */
1150+ DPBP_RSP_GET_IRQ(cmd, *type, irq_cfg);
1151+
1152+ return 0;
1153+}
1154+
1155+int dpbp_set_irq_enable(struct fsl_mc_io *mc_io,
1156+ uint32_t cmd_flags,
1157+ uint16_t token,
1158+ uint8_t irq_index,
1159+ uint8_t en)
1160+{
1161+ struct mc_command cmd = { 0 };
1162+
1163+ /* prepare command */
1164+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ_ENABLE,
1165+ cmd_flags,
1166+ token);
1167+
1168+ DPBP_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
1169+
1170+ /* send command to mc*/
1171+ return mc_send_command(mc_io, &cmd);
1172+}
1173+
1174+int dpbp_get_irq_enable(struct fsl_mc_io *mc_io,
1175+ uint32_t cmd_flags,
1176+ uint16_t token,
1177+ uint8_t irq_index,
1178+ uint8_t *en)
1179+{
1180+ struct mc_command cmd = { 0 };
1181+ int err;
1182+
1183+ /* prepare command */
1184+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_ENABLE,
1185+ cmd_flags,
1186+ token);
1187+
1188+ DPBP_CMD_GET_IRQ_ENABLE(cmd, irq_index);
1189+
1190+ /* send command to mc*/
1191+ err = mc_send_command(mc_io, &cmd);
1192+ if (err)
1193+ return err;
1194+
1195+ /* retrieve response parameters */
1196+ DPBP_RSP_GET_IRQ_ENABLE(cmd, *en);
1197+
1198+ return 0;
1199+}
1200+
1201+int dpbp_set_irq_mask(struct fsl_mc_io *mc_io,
1202+ uint32_t cmd_flags,
1203+ uint16_t token,
1204+ uint8_t irq_index,
1205+ uint32_t mask)
1206+{
1207+ struct mc_command cmd = { 0 };
1208+
1209+ /* prepare command */
1210+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ_MASK,
1211+ cmd_flags,
1212+ token);
1213+
1214+ DPBP_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
1215+
1216+ /* send command to mc*/
1217+ return mc_send_command(mc_io, &cmd);
1218+}
1219+
1220+int dpbp_get_irq_mask(struct fsl_mc_io *mc_io,
1221+ uint32_t cmd_flags,
1222+ uint16_t token,
1223+ uint8_t irq_index,
1224+ uint32_t *mask)
1225+{
1226+ struct mc_command cmd = { 0 };
1227+ int err;
1228+
1229+ /* prepare command */
1230+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_MASK,
1231+ cmd_flags,
1232+ token);
1233+
1234+ DPBP_CMD_GET_IRQ_MASK(cmd, irq_index);
1235+
1236+ /* send command to mc*/
1237+ err = mc_send_command(mc_io, &cmd);
1238+ if (err)
1239+ return err;
1240+
1241+ /* retrieve response parameters */
1242+ DPBP_RSP_GET_IRQ_MASK(cmd, *mask);
1243+
1244+ return 0;
1245+}
1246+
1247+int dpbp_get_irq_status(struct fsl_mc_io *mc_io,
1248+ uint32_t cmd_flags,
1249+ uint16_t token,
1250+ uint8_t irq_index,
1251+ uint32_t *status)
1252+{
1253+ struct mc_command cmd = { 0 };
1254+ int err;
1255+
1256+ /* prepare command */
1257+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_STATUS,
1258+ cmd_flags,
1259+ token);
1260+
1261+ DPBP_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
1262+
1263+ /* send command to mc*/
1264+ err = mc_send_command(mc_io, &cmd);
1265+ if (err)
1266+ return err;
1267+
1268+ /* retrieve response parameters */
1269+ DPBP_RSP_GET_IRQ_STATUS(cmd, *status);
1270+
1271+ return 0;
1272+}
1273+
1274+int dpbp_clear_irq_status(struct fsl_mc_io *mc_io,
1275+ uint32_t cmd_flags,
1276+ uint16_t token,
1277+ uint8_t irq_index,
1278+ uint32_t status)
1279+{
1280+ struct mc_command cmd = { 0 };
1281+
1282+ /* prepare command */
1283+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLEAR_IRQ_STATUS,
1284+ cmd_flags,
1285+ token);
1286+
1287+ DPBP_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
1288+
1289+ /* send command to mc*/
1290+ return mc_send_command(mc_io, &cmd);
1291+}
1292+
1293+int dpbp_get_attributes(struct fsl_mc_io *mc_io,
1294+ uint32_t cmd_flags,
1295+ uint16_t token,
1296+ struct dpbp_attr *attr)
1297+{
1298+ struct mc_command cmd = { 0 };
1299+ int err;
1300+
1301+ /* prepare command */
1302+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_ATTR,
1303+ cmd_flags,
1304+ token);
1305+
1306+ /* send command to mc*/
1307+ err = mc_send_command(mc_io, &cmd);
1308+ if (err)
1309+ return err;
1310+
1311+ /* retrieve response parameters */
1312+ DPBP_RSP_GET_ATTRIBUTES(cmd, attr);
1313+
1314+ return 0;
1315+}
1316+
1317+int dpbp_set_notifications(struct fsl_mc_io *mc_io,
1318+ uint32_t cmd_flags,
1319+ uint16_t token,
1320+ struct dpbp_notification_cfg *cfg)
1321+{
1322+ struct mc_command cmd = { 0 };
1323+
1324+ /* prepare command */
1325+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_NOTIFICATIONS,
1326+ cmd_flags,
1327+ token);
1328+
1329+ DPBP_CMD_SET_NOTIFICATIONS(cmd, cfg);
1330+
1331+ /* send command to mc*/
1332+ return mc_send_command(mc_io, &cmd);
1333+}
1334+
1335+int dpbp_get_notifications(struct fsl_mc_io *mc_io,
1336+ uint32_t cmd_flags,
1337+ uint16_t token,
1338+ struct dpbp_notification_cfg *cfg)
1339+{
1340+ struct mc_command cmd = { 0 };
1341+ int err;
1342+
1343+ /* prepare command */
1344+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_NOTIFICATIONS,
1345+ cmd_flags,
1346+ token);
1347+
1348+ /* send command to mc*/
1349+ err = mc_send_command(mc_io, &cmd);
1350+ if (err)
1351+ return err;
1352+
1353+ /* retrieve response parameters */
1354+ DPBP_CMD_GET_NOTIFICATIONS(cmd, cfg);
1355+
1356+ return 0;
1357+}
1358diff --git a/drivers/net/dpaa2/mc/dpci.c b/drivers/net/dpaa2/mc/dpci.c
1359new file mode 100644
1360index 0000000..2ec02a1
1361--- /dev/null
1362+++ b/drivers/net/dpaa2/mc/dpci.c
1363@@ -0,0 +1,501 @@
1364+/* Copyright 2013-2015 Freescale Semiconductor Inc.
1365+ *
1366+ * Redistribution and use in source and binary forms, with or without
1367+ * modification, are permitted provided that the following conditions are met:
1368+ * * Redistributions of source code must retain the above copyright
1369+ * notice, this list of conditions and the following disclaimer.
1370+ * * Redistributions in binary form must reproduce the above copyright
1371+ * notice, this list of conditions and the following disclaimer in the
1372+ * documentation and/or other materials provided with the distribution.
1373+ * * Neither the name of the above-listed copyright holders nor the
1374+ * names of any contributors may be used to endorse or promote products
1375+ * derived from this software without specific prior written permission.
1376+ *
1377+ *
1378+ * ALTERNATIVELY, this software may be distributed under the terms of the
1379+ * GNU General Public License ("GPL") as published by the Free Software
1380+ * Foundation, either version 2 of that License or (at your option) any
1381+ * later version.
1382+ *
1383+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1384+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1385+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1386+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
1387+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1388+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1389+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1390+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1391+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1392+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
1393+ * POSSIBILITY OF SUCH DAMAGE.
1394+ */
1395+#include <fsl_mc_sys.h>
1396+#include <fsl_mc_cmd.h>
1397+#include <fsl_dpci.h>
1398+#include <fsl_dpci_cmd.h>
1399+
1400+int dpci_open(struct fsl_mc_io *mc_io,
1401+ uint32_t cmd_flags,
1402+ int dpci_id,
1403+ uint16_t *token)
1404+{
1405+ struct mc_command cmd = { 0 };
1406+ int err;
1407+
1408+ /* prepare command */
1409+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_OPEN,
1410+ cmd_flags,
1411+ 0);
1412+ DPCI_CMD_OPEN(cmd, dpci_id);
1413+
1414+ /* send command to mc*/
1415+ err = mc_send_command(mc_io, &cmd);
1416+ if (err)
1417+ return err;
1418+
1419+ /* retrieve response parameters */
1420+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
1421+
1422+ return 0;
1423+}
1424+
1425+int dpci_close(struct fsl_mc_io *mc_io,
1426+ uint32_t cmd_flags,
1427+ uint16_t token)
1428+{
1429+ struct mc_command cmd = { 0 };
1430+
1431+ /* prepare command */
1432+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_CLOSE,
1433+ cmd_flags,
1434+ token);
1435+
1436+ /* send command to mc*/
1437+ return mc_send_command(mc_io, &cmd);
1438+}
1439+
1440+int dpci_create(struct fsl_mc_io *mc_io,
1441+ uint32_t cmd_flags,
1442+ const struct dpci_cfg *cfg,
1443+ uint16_t *token)
1444+{
1445+ struct mc_command cmd = { 0 };
1446+ int err;
1447+
1448+ /* prepare command */
1449+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_CREATE,
1450+ cmd_flags,
1451+ 0);
1452+ DPCI_CMD_CREATE(cmd, cfg);
1453+
1454+ /* send command to mc*/
1455+ err = mc_send_command(mc_io, &cmd);
1456+ if (err)
1457+ return err;
1458+
1459+ /* retrieve response parameters */
1460+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
1461+
1462+ return 0;
1463+}
1464+
1465+int dpci_destroy(struct fsl_mc_io *mc_io,
1466+ uint32_t cmd_flags,
1467+ uint16_t token)
1468+{
1469+ struct mc_command cmd = { 0 };
1470+
1471+ /* prepare command */
1472+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_DESTROY,
1473+ cmd_flags,
1474+ token);
1475+
1476+ /* send command to mc*/
1477+ return mc_send_command(mc_io, &cmd);
1478+}
1479+
1480+int dpci_enable(struct fsl_mc_io *mc_io,
1481+ uint32_t cmd_flags,
1482+ uint16_t token)
1483+{
1484+ struct mc_command cmd = { 0 };
1485+
1486+ /* prepare command */
1487+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_ENABLE,
1488+ cmd_flags,
1489+ token);
1490+
1491+ /* send command to mc*/
1492+ return mc_send_command(mc_io, &cmd);
1493+}
1494+
1495+int dpci_disable(struct fsl_mc_io *mc_io,
1496+ uint32_t cmd_flags,
1497+ uint16_t token)
1498+{
1499+ struct mc_command cmd = { 0 };
1500+
1501+ /* prepare command */
1502+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_DISABLE,
1503+ cmd_flags,
1504+ token);
1505+
1506+ /* send command to mc*/
1507+ return mc_send_command(mc_io, &cmd);
1508+}
1509+
1510+int dpci_is_enabled(struct fsl_mc_io *mc_io,
1511+ uint32_t cmd_flags,
1512+ uint16_t token,
1513+ int *en)
1514+{
1515+ struct mc_command cmd = { 0 };
1516+ int err;
1517+ /* prepare command */
1518+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_IS_ENABLED, cmd_flags,
1519+ token);
1520+
1521+ /* send command to mc*/
1522+ err = mc_send_command(mc_io, &cmd);
1523+ if (err)
1524+ return err;
1525+
1526+ /* retrieve response parameters */
1527+ DPCI_RSP_IS_ENABLED(cmd, *en);
1528+
1529+ return 0;
1530+}
1531+
1532+int dpci_reset(struct fsl_mc_io *mc_io,
1533+ uint32_t cmd_flags,
1534+ uint16_t token)
1535+{
1536+ struct mc_command cmd = { 0 };
1537+
1538+ /* prepare command */
1539+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_RESET,
1540+ cmd_flags,
1541+ token);
1542+
1543+ /* send command to mc*/
1544+ return mc_send_command(mc_io, &cmd);
1545+}
1546+
1547+int dpci_set_irq(struct fsl_mc_io *mc_io,
1548+ uint32_t cmd_flags,
1549+ uint16_t token,
1550+ uint8_t irq_index,
1551+ struct dpci_irq_cfg *irq_cfg)
1552+{
1553+ struct mc_command cmd = { 0 };
1554+
1555+ /* prepare command */
1556+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_SET_IRQ,
1557+ cmd_flags,
1558+ token);
1559+ DPCI_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
1560+
1561+ /* send command to mc*/
1562+ return mc_send_command(mc_io, &cmd);
1563+}
1564+
1565+int dpci_get_irq(struct fsl_mc_io *mc_io,
1566+ uint32_t cmd_flags,
1567+ uint16_t token,
1568+ uint8_t irq_index,
1569+ int *type,
1570+ struct dpci_irq_cfg *irq_cfg)
1571+{
1572+ struct mc_command cmd = { 0 };
1573+ int err;
1574+
1575+ /* prepare command */
1576+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_IRQ,
1577+ cmd_flags,
1578+ token);
1579+ DPCI_CMD_GET_IRQ(cmd, irq_index);
1580+
1581+ /* send command to mc*/
1582+ err = mc_send_command(mc_io, &cmd);
1583+ if (err)
1584+ return err;
1585+
1586+ /* retrieve response parameters */
1587+ DPCI_RSP_GET_IRQ(cmd, *type, irq_cfg);
1588+
1589+ return 0;
1590+}
1591+
1592+int dpci_set_irq_enable(struct fsl_mc_io *mc_io,
1593+ uint32_t cmd_flags,
1594+ uint16_t token,
1595+ uint8_t irq_index,
1596+ uint8_t en)
1597+{
1598+ struct mc_command cmd = { 0 };
1599+
1600+ /* prepare command */
1601+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_SET_IRQ_ENABLE,
1602+ cmd_flags,
1603+ token);
1604+ DPCI_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
1605+
1606+ /* send command to mc*/
1607+ return mc_send_command(mc_io, &cmd);
1608+}
1609+
1610+int dpci_get_irq_enable(struct fsl_mc_io *mc_io,
1611+ uint32_t cmd_flags,
1612+ uint16_t token,
1613+ uint8_t irq_index,
1614+ uint8_t *en)
1615+{
1616+ struct mc_command cmd = { 0 };
1617+ int err;
1618+
1619+ /* prepare command */
1620+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_IRQ_ENABLE,
1621+ cmd_flags,
1622+ token);
1623+ DPCI_CMD_GET_IRQ_ENABLE(cmd, irq_index);
1624+
1625+ /* send command to mc*/
1626+ err = mc_send_command(mc_io, &cmd);
1627+ if (err)
1628+ return err;
1629+
1630+ /* retrieve response parameters */
1631+ DPCI_RSP_GET_IRQ_ENABLE(cmd, *en);
1632+
1633+ return 0;
1634+}
1635+
1636+int dpci_set_irq_mask(struct fsl_mc_io *mc_io,
1637+ uint32_t cmd_flags,
1638+ uint16_t token,
1639+ uint8_t irq_index,
1640+ uint32_t mask)
1641+{
1642+ struct mc_command cmd = { 0 };
1643+
1644+ /* prepare command */
1645+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_SET_IRQ_MASK,
1646+ cmd_flags,
1647+ token);
1648+ DPCI_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
1649+
1650+ /* send command to mc*/
1651+ return mc_send_command(mc_io, &cmd);
1652+}
1653+
1654+int dpci_get_irq_mask(struct fsl_mc_io *mc_io,
1655+ uint32_t cmd_flags,
1656+ uint16_t token,
1657+ uint8_t irq_index,
1658+ uint32_t *mask)
1659+{
1660+ struct mc_command cmd = { 0 };
1661+ int err;
1662+
1663+ /* prepare command */
1664+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_IRQ_MASK,
1665+ cmd_flags,
1666+ token);
1667+ DPCI_CMD_GET_IRQ_MASK(cmd, irq_index);
1668+
1669+ /* send command to mc*/
1670+ err = mc_send_command(mc_io, &cmd);
1671+ if (err)
1672+ return err;
1673+
1674+ /* retrieve response parameters */
1675+ DPCI_RSP_GET_IRQ_MASK(cmd, *mask);
1676+
1677+ return 0;
1678+}
1679+
1680+int dpci_get_irq_status(struct fsl_mc_io *mc_io,
1681+ uint32_t cmd_flags,
1682+ uint16_t token,
1683+ uint8_t irq_index,
1684+ uint32_t *status)
1685+{
1686+ struct mc_command cmd = { 0 };
1687+ int err;
1688+
1689+ /* prepare command */
1690+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_IRQ_STATUS,
1691+ cmd_flags,
1692+ token);
1693+ DPCI_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
1694+
1695+ /* send command to mc*/
1696+ err = mc_send_command(mc_io, &cmd);
1697+ if (err)
1698+ return err;
1699+
1700+ /* retrieve response parameters */
1701+ DPCI_RSP_GET_IRQ_STATUS(cmd, *status);
1702+
1703+ return 0;
1704+}
1705+
1706+int dpci_clear_irq_status(struct fsl_mc_io *mc_io,
1707+ uint32_t cmd_flags,
1708+ uint16_t token,
1709+ uint8_t irq_index,
1710+ uint32_t status)
1711+{
1712+ struct mc_command cmd = { 0 };
1713+
1714+ /* prepare command */
1715+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_CLEAR_IRQ_STATUS,
1716+ cmd_flags,
1717+ token);
1718+ DPCI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
1719+
1720+ /* send command to mc*/
1721+ return mc_send_command(mc_io, &cmd);
1722+}
1723+
1724+int dpci_get_attributes(struct fsl_mc_io *mc_io,
1725+ uint32_t cmd_flags,
1726+ uint16_t token,
1727+ struct dpci_attr *attr)
1728+{
1729+ struct mc_command cmd = { 0 };
1730+ int err;
1731+
1732+ /* prepare command */
1733+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_ATTR,
1734+ cmd_flags,
1735+ token);
1736+
1737+ /* send command to mc*/
1738+ err = mc_send_command(mc_io, &cmd);
1739+ if (err)
1740+ return err;
1741+
1742+ /* retrieve response parameters */
1743+ DPCI_RSP_GET_ATTR(cmd, attr);
1744+
1745+ return 0;
1746+}
1747+
1748+int dpci_get_peer_attributes(struct fsl_mc_io *mc_io,
1749+ uint32_t cmd_flags,
1750+ uint16_t token,
1751+ struct dpci_peer_attr *attr)
1752+{
1753+ struct mc_command cmd = { 0 };
1754+ int err;
1755+
1756+ /* prepare command */
1757+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_PEER_ATTR,
1758+ cmd_flags,
1759+ token);
1760+
1761+ /* send command to mc*/
1762+ err = mc_send_command(mc_io, &cmd);
1763+ if (err)
1764+ return err;
1765+
1766+ /* retrieve response parameters */
1767+ DPCI_RSP_GET_PEER_ATTR(cmd, attr);
1768+
1769+ return 0;
1770+}
1771+
1772+int dpci_get_link_state(struct fsl_mc_io *mc_io,
1773+ uint32_t cmd_flags,
1774+ uint16_t token,
1775+ int *up)
1776+{
1777+ struct mc_command cmd = { 0 };
1778+ int err;
1779+
1780+ /* prepare command */
1781+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_LINK_STATE,
1782+ cmd_flags,
1783+ token);
1784+
1785+ /* send command to mc*/
1786+ err = mc_send_command(mc_io, &cmd);
1787+ if (err)
1788+ return err;
1789+
1790+ /* retrieve response parameters */
1791+ DPCI_RSP_GET_LINK_STATE(cmd, *up);
1792+
1793+ return 0;
1794+}
1795+
1796+int dpci_set_rx_queue(struct fsl_mc_io *mc_io,
1797+ uint32_t cmd_flags,
1798+ uint16_t token,
1799+ uint8_t priority,
1800+ const struct dpci_rx_queue_cfg *cfg)
1801+{
1802+ struct mc_command cmd = { 0 };
1803+
1804+ /* prepare command */
1805+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_SET_RX_QUEUE,
1806+ cmd_flags,
1807+ token);
1808+ DPCI_CMD_SET_RX_QUEUE(cmd, priority, cfg);
1809+
1810+ /* send command to mc*/
1811+ return mc_send_command(mc_io, &cmd);
1812+}
1813+
1814+int dpci_get_rx_queue(struct fsl_mc_io *mc_io,
1815+ uint32_t cmd_flags,
1816+ uint16_t token,
1817+ uint8_t priority,
1818+ struct dpci_rx_queue_attr *attr)
1819+{
1820+ struct mc_command cmd = { 0 };
1821+ int err;
1822+
1823+ /* prepare command */
1824+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_RX_QUEUE,
1825+ cmd_flags,
1826+ token);
1827+ DPCI_CMD_GET_RX_QUEUE(cmd, priority);
1828+
1829+ /* send command to mc*/
1830+ err = mc_send_command(mc_io, &cmd);
1831+ if (err)
1832+ return err;
1833+
1834+ /* retrieve response parameters */
1835+ DPCI_RSP_GET_RX_QUEUE(cmd, attr);
1836+
1837+ return 0;
1838+}
1839+
1840+int dpci_get_tx_queue(struct fsl_mc_io *mc_io,
1841+ uint32_t cmd_flags,
1842+ uint16_t token,
1843+ uint8_t priority,
1844+ struct dpci_tx_queue_attr *attr)
1845+{
1846+ struct mc_command cmd = { 0 };
1847+ int err;
1848+
1849+ /* prepare command */
1850+ cmd.header = mc_encode_cmd_header(DPCI_CMDID_GET_TX_QUEUE,
1851+ cmd_flags,
1852+ token);
1853+ DPCI_CMD_GET_TX_QUEUE(cmd, priority);
1854+
1855+ /* send command to mc*/
1856+ err = mc_send_command(mc_io, &cmd);
1857+ if (err)
1858+ return err;
1859+
1860+ /* retrieve response parameters */
1861+ DPCI_RSP_GET_TX_QUEUE(cmd, attr);
1862+
1863+ return 0;
1864+}
1865diff --git a/drivers/net/dpaa2/mc/dpcon.c b/drivers/net/dpaa2/mc/dpcon.c
1866new file mode 100644
1867index 0000000..396303d
1868--- /dev/null
1869+++ b/drivers/net/dpaa2/mc/dpcon.c
1870@@ -0,0 +1,401 @@
1871+/* Copyright 2013-2015 Freescale Semiconductor Inc.
1872+ *
1873+ * Redistribution and use in source and binary forms, with or without
1874+ * modification, are permitted provided that the following conditions are met:
1875+ * * Redistributions of source code must retain the above copyright
1876+ * notice, this list of conditions and the following disclaimer.
1877+ * * Redistributions in binary form must reproduce the above copyright
1878+ * notice, this list of conditions and the following disclaimer in the
1879+ * documentation and/or other materials provided with the distribution.
1880+ * * Neither the name of the above-listed copyright holders nor the
1881+ * names of any contributors may be used to endorse or promote products
1882+ * derived from this software without specific prior written permission.
1883+ *
1884+ *
1885+ * ALTERNATIVELY, this software may be distributed under the terms of the
1886+ * GNU General Public License ("GPL") as published by the Free Software
1887+ * Foundation, either version 2 of that License or (at your option) any
1888+ * later version.
1889+ *
1890+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1891+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1892+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1893+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
1894+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1895+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1896+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1897+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1898+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1899+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
1900+ * POSSIBILITY OF SUCH DAMAGE.
1901+ */
1902+#include <fsl_mc_sys.h>
1903+#include <fsl_mc_cmd.h>
1904+#include <fsl_dpcon.h>
1905+#include <fsl_dpcon_cmd.h>
1906+
1907+int dpcon_open(struct fsl_mc_io *mc_io,
1908+ uint32_t cmd_flags,
1909+ int dpcon_id,
1910+ uint16_t *token)
1911+{
1912+ struct mc_command cmd = { 0 };
1913+ int err;
1914+
1915+ /* prepare command */
1916+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_OPEN,
1917+ cmd_flags,
1918+ 0);
1919+ DPCON_CMD_OPEN(cmd, dpcon_id);
1920+
1921+ /* send command to mc*/
1922+ err = mc_send_command(mc_io, &cmd);
1923+ if (err)
1924+ return err;
1925+
1926+ /* retrieve response parameters */
1927+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
1928+
1929+ return 0;
1930+}
1931+
1932+int dpcon_close(struct fsl_mc_io *mc_io,
1933+ uint32_t cmd_flags,
1934+ uint16_t token)
1935+{
1936+ struct mc_command cmd = { 0 };
1937+
1938+ /* prepare command */
1939+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLOSE,
1940+ cmd_flags,
1941+ token);
1942+
1943+ /* send command to mc*/
1944+ return mc_send_command(mc_io, &cmd);
1945+}
1946+
1947+int dpcon_create(struct fsl_mc_io *mc_io,
1948+ uint32_t cmd_flags,
1949+ const struct dpcon_cfg *cfg,
1950+ uint16_t *token)
1951+{
1952+ struct mc_command cmd = { 0 };
1953+ int err;
1954+
1955+ /* prepare command */
1956+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_CREATE,
1957+ cmd_flags,
1958+ 0);
1959+ DPCON_CMD_CREATE(cmd, cfg);
1960+
1961+ /* send command to mc*/
1962+ err = mc_send_command(mc_io, &cmd);
1963+ if (err)
1964+ return err;
1965+
1966+ /* retrieve response parameters */
1967+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
1968+
1969+ return 0;
1970+}
1971+
1972+int dpcon_destroy(struct fsl_mc_io *mc_io,
1973+ uint32_t cmd_flags,
1974+ uint16_t token)
1975+{
1976+ struct mc_command cmd = { 0 };
1977+
1978+ /* prepare command */
1979+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_DESTROY,
1980+ cmd_flags,
1981+ token);
1982+
1983+ /* send command to mc*/
1984+ return mc_send_command(mc_io, &cmd);
1985+}
1986+
1987+int dpcon_enable(struct fsl_mc_io *mc_io,
1988+ uint32_t cmd_flags,
1989+ uint16_t token)
1990+{
1991+ struct mc_command cmd = { 0 };
1992+
1993+ /* prepare command */
1994+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_ENABLE,
1995+ cmd_flags,
1996+ token);
1997+
1998+ /* send command to mc*/
1999+ return mc_send_command(mc_io, &cmd);
2000+}
2001+
2002+int dpcon_disable(struct fsl_mc_io *mc_io,
2003+ uint32_t cmd_flags,
2004+ uint16_t token)
2005+{
2006+ struct mc_command cmd = { 0 };
2007+
2008+ /* prepare command */
2009+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_DISABLE,
2010+ cmd_flags,
2011+ token);
2012+
2013+ /* send command to mc*/
2014+ return mc_send_command(mc_io, &cmd);
2015+}
2016+
2017+int dpcon_is_enabled(struct fsl_mc_io *mc_io,
2018+ uint32_t cmd_flags,
2019+ uint16_t token,
2020+ int *en)
2021+{
2022+ struct mc_command cmd = { 0 };
2023+ int err;
2024+ /* prepare command */
2025+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_IS_ENABLED,
2026+ cmd_flags,
2027+ token);
2028+
2029+ /* send command to mc*/
2030+ err = mc_send_command(mc_io, &cmd);
2031+ if (err)
2032+ return err;
2033+
2034+ /* retrieve response parameters */
2035+ DPCON_RSP_IS_ENABLED(cmd, *en);
2036+
2037+ return 0;
2038+}
2039+
2040+int dpcon_reset(struct fsl_mc_io *mc_io,
2041+ uint32_t cmd_flags,
2042+ uint16_t token)
2043+{
2044+ struct mc_command cmd = { 0 };
2045+
2046+ /* prepare command */
2047+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_RESET,
2048+ cmd_flags, token);
2049+
2050+ /* send command to mc*/
2051+ return mc_send_command(mc_io, &cmd);
2052+}
2053+
2054+int dpcon_set_irq(struct fsl_mc_io *mc_io,
2055+ uint32_t cmd_flags,
2056+ uint16_t token,
2057+ uint8_t irq_index,
2058+ struct dpcon_irq_cfg *irq_cfg)
2059+{
2060+ struct mc_command cmd = { 0 };
2061+
2062+ /* prepare command */
2063+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_IRQ,
2064+ cmd_flags,
2065+ token);
2066+ DPCON_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
2067+
2068+ /* send command to mc*/
2069+ return mc_send_command(mc_io, &cmd);
2070+}
2071+
2072+int dpcon_get_irq(struct fsl_mc_io *mc_io,
2073+ uint32_t cmd_flags,
2074+ uint16_t token,
2075+ uint8_t irq_index,
2076+ int *type,
2077+ struct dpcon_irq_cfg *irq_cfg)
2078+{
2079+ struct mc_command cmd = { 0 };
2080+ int err;
2081+
2082+ /* prepare command */
2083+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_IRQ,
2084+ cmd_flags,
2085+ token);
2086+ DPCON_CMD_GET_IRQ(cmd, irq_index);
2087+
2088+ /* send command to mc*/
2089+ err = mc_send_command(mc_io, &cmd);
2090+ if (err)
2091+ return err;
2092+
2093+ /* retrieve response parameters */
2094+ DPCON_RSP_GET_IRQ(cmd, *type, irq_cfg);
2095+
2096+ return 0;
2097+}
2098+
2099+int dpcon_set_irq_enable(struct fsl_mc_io *mc_io,
2100+ uint32_t cmd_flags,
2101+ uint16_t token,
2102+ uint8_t irq_index,
2103+ uint8_t en)
2104+{
2105+ struct mc_command cmd = { 0 };
2106+
2107+ /* prepare command */
2108+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_IRQ_ENABLE,
2109+ cmd_flags,
2110+ token);
2111+ DPCON_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
2112+
2113+ /* send command to mc*/
2114+ return mc_send_command(mc_io, &cmd);
2115+}
2116+
2117+int dpcon_get_irq_enable(struct fsl_mc_io *mc_io,
2118+ uint32_t cmd_flags,
2119+ uint16_t token,
2120+ uint8_t irq_index,
2121+ uint8_t *en)
2122+{
2123+ struct mc_command cmd = { 0 };
2124+ int err;
2125+
2126+ /* prepare command */
2127+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_IRQ_ENABLE,
2128+ cmd_flags,
2129+ token);
2130+ DPCON_CMD_GET_IRQ_ENABLE(cmd, irq_index);
2131+
2132+ /* send command to mc*/
2133+ err = mc_send_command(mc_io, &cmd);
2134+ if (err)
2135+ return err;
2136+
2137+ /* retrieve response parameters */
2138+ DPCON_RSP_GET_IRQ_ENABLE(cmd, *en);
2139+
2140+ return 0;
2141+}
2142+
2143+int dpcon_set_irq_mask(struct fsl_mc_io *mc_io,
2144+ uint32_t cmd_flags,
2145+ uint16_t token,
2146+ uint8_t irq_index,
2147+ uint32_t mask)
2148+{
2149+ struct mc_command cmd = { 0 };
2150+
2151+ /* prepare command */
2152+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_IRQ_MASK,
2153+ cmd_flags,
2154+ token);
2155+ DPCON_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
2156+
2157+ /* send command to mc*/
2158+ return mc_send_command(mc_io, &cmd);
2159+}
2160+
2161+int dpcon_get_irq_mask(struct fsl_mc_io *mc_io,
2162+ uint32_t cmd_flags,
2163+ uint16_t token,
2164+ uint8_t irq_index,
2165+ uint32_t *mask)
2166+{
2167+ struct mc_command cmd = { 0 };
2168+ int err;
2169+
2170+ /* prepare command */
2171+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_IRQ_MASK,
2172+ cmd_flags,
2173+ token);
2174+ DPCON_CMD_GET_IRQ_MASK(cmd, irq_index);
2175+
2176+ /* send command to mc*/
2177+ err = mc_send_command(mc_io, &cmd);
2178+ if (err)
2179+ return err;
2180+
2181+ /* retrieve response parameters */
2182+ DPCON_RSP_GET_IRQ_MASK(cmd, *mask);
2183+
2184+ return 0;
2185+}
2186+
2187+int dpcon_get_irq_status(struct fsl_mc_io *mc_io,
2188+ uint32_t cmd_flags,
2189+ uint16_t token,
2190+ uint8_t irq_index,
2191+ uint32_t *status)
2192+{
2193+ struct mc_command cmd = { 0 };
2194+ int err;
2195+
2196+ /* prepare command */
2197+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_IRQ_STATUS,
2198+ cmd_flags,
2199+ token);
2200+ DPCON_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
2201+
2202+ /* send command to mc*/
2203+ err = mc_send_command(mc_io, &cmd);
2204+ if (err)
2205+ return err;
2206+
2207+ /* retrieve response parameters */
2208+ DPCON_RSP_GET_IRQ_STATUS(cmd, *status);
2209+
2210+ return 0;
2211+}
2212+
2213+int dpcon_clear_irq_status(struct fsl_mc_io *mc_io,
2214+ uint32_t cmd_flags,
2215+ uint16_t token,
2216+ uint8_t irq_index,
2217+ uint32_t status)
2218+{
2219+ struct mc_command cmd = { 0 };
2220+
2221+ /* prepare command */
2222+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLEAR_IRQ_STATUS,
2223+ cmd_flags,
2224+ token);
2225+ DPCON_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
2226+
2227+ /* send command to mc*/
2228+ return mc_send_command(mc_io, &cmd);
2229+}
2230+
2231+int dpcon_get_attributes(struct fsl_mc_io *mc_io,
2232+ uint32_t cmd_flags,
2233+ uint16_t token,
2234+ struct dpcon_attr *attr)
2235+{
2236+ struct mc_command cmd = { 0 };
2237+ int err;
2238+
2239+ /* prepare command */
2240+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_ATTR,
2241+ cmd_flags,
2242+ token);
2243+
2244+ /* send command to mc*/
2245+ err = mc_send_command(mc_io, &cmd);
2246+ if (err)
2247+ return err;
2248+
2249+ /* retrieve response parameters */
2250+ DPCON_RSP_GET_ATTR(cmd, attr);
2251+
2252+ return 0;
2253+}
2254+
2255+int dpcon_set_notification(struct fsl_mc_io *mc_io,
2256+ uint32_t cmd_flags,
2257+ uint16_t token,
2258+ struct dpcon_notification_cfg *cfg)
2259+{
2260+ struct mc_command cmd = { 0 };
2261+
2262+ /* prepare command */
2263+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_NOTIFICATION,
2264+ cmd_flags,
2265+ token);
2266+ DPCON_CMD_SET_NOTIFICATION(cmd, cfg);
2267+
2268+ /* send command to mc*/
2269+ return mc_send_command(mc_io, &cmd);
2270+}
2271+
2272diff --git a/drivers/net/dpaa2/mc/dpdbg.c b/drivers/net/dpaa2/mc/dpdbg.c
2273new file mode 100644
2274index 0000000..6f2a08d
2275--- /dev/null
2276+++ b/drivers/net/dpaa2/mc/dpdbg.c
2277@@ -0,0 +1,547 @@
2278+/* Copyright 2013-2015 Freescale Semiconductor Inc.
2279+ *
2280+ * Redistribution and use in source and binary forms, with or without
2281+ * modification, are permitted provided that the following conditions are met:
2282+ * * Redistributions of source code must retain the above copyright
2283+ * notice, this list of conditions and the following disclaimer.
2284+ * * Redistributions in binary form must reproduce the above copyright
2285+ * notice, this list of conditions and the following disclaimer in the
2286+ * documentation and/or other materials provided with the distribution.
2287+ * * Neither the name of the above-listed copyright holders nor the
2288+ * names of any contributors may be used to endorse or promote products
2289+ * derived from this software without specific prior written permission.
2290+ *
2291+ *
2292+ * ALTERNATIVELY, this software may be distributed under the terms of the
2293+ * GNU General Public License ("GPL") as published by the Free Software
2294+ * Foundation, either version 2 of that License or (at your option) any
2295+ * later version.
2296+ *
2297+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
2298+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2299+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2300+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
2301+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2302+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2303+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2304+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2305+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2306+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2307+ * POSSIBILITY OF SUCH DAMAGE.
2308+ */
2309+#include <fsl_mc_sys.h>
2310+#include <fsl_mc_cmd.h>
2311+#include <fsl_dpdbg.h>
2312+#include <fsl_dpdbg_cmd.h>
2313+
2314+int dpdbg_open(struct fsl_mc_io *mc_io,
2315+ uint32_t cmd_flags,
2316+ int dpdbg_id,
2317+ uint16_t *token)
2318+{
2319+ struct mc_command cmd = { 0 };
2320+ int err;
2321+
2322+ /* prepare command */
2323+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_OPEN,
2324+ cmd_flags,
2325+ 0);
2326+ DPDBG_CMD_OPEN(cmd, dpdbg_id);
2327+
2328+ /* send command to mc*/
2329+ err = mc_send_command(mc_io, &cmd);
2330+ if (err)
2331+ return err;
2332+
2333+ /* retrieve response parameters */
2334+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
2335+
2336+ return err;
2337+}
2338+
2339+int dpdbg_close(struct fsl_mc_io *mc_io,
2340+ uint32_t cmd_flags,
2341+ uint16_t token)
2342+{
2343+ struct mc_command cmd = { 0 };
2344+
2345+ /* prepare command */
2346+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_CLOSE, cmd_flags,
2347+ token);
2348+
2349+ /* send command to mc*/
2350+ return mc_send_command(mc_io, &cmd);
2351+}
2352+
2353+int dpdbg_get_attributes(struct fsl_mc_io *mc_io,
2354+ uint32_t cmd_flags,
2355+ uint16_t token,
2356+ struct dpdbg_attr *attr)
2357+{
2358+ struct mc_command cmd = { 0 };
2359+ int err;
2360+
2361+ /* prepare command */
2362+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_GET_ATTR,
2363+ cmd_flags,
2364+ token);
2365+
2366+ /* send command to mc*/
2367+ err = mc_send_command(mc_io, &cmd);
2368+ if (err)
2369+ return err;
2370+
2371+ /* retrieve response parameters */
2372+ DPDBG_RSP_GET_ATTRIBUTES(cmd, attr);
2373+
2374+ return 0;
2375+}
2376+
2377+int dpdbg_get_dpni_info(struct fsl_mc_io *mc_io,
2378+ uint32_t cmd_flags,
2379+ uint16_t token,
2380+ int dpni_id,
2381+ struct dpdbg_dpni_info *info)
2382+{
2383+ struct mc_command cmd = { 0 };
2384+ int err;
2385+
2386+ /* prepare command */
2387+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_GET_DPNI_INFO,
2388+ cmd_flags,
2389+ token);
2390+ DPDBG_CMD_GET_DPNI_INFO(cmd, dpni_id);
2391+
2392+ /* send command to mc*/
2393+ err = mc_send_command(mc_io, &cmd);
2394+ if (err)
2395+ return err;
2396+
2397+ /* retrieve response parameters */
2398+ DPDBG_RSP_GET_DPNI_INFO(cmd, info);
2399+
2400+ return 0;
2401+}
2402+
2403+int dpdbg_get_dpni_priv_tx_conf_fqid(struct fsl_mc_io *mc_io,
2404+ uint32_t cmd_flags,
2405+ uint16_t token,
2406+ int dpni_id,
2407+ uint8_t sender_id,
2408+ uint32_t *fqid)
2409+{
2410+ struct mc_command cmd = { 0 };
2411+ int err;
2412+
2413+ /* prepare command */
2414+ cmd.header = mc_encode_cmd_header(
2415+ DPDBG_CMDID_GET_DPNI_PRIV_TX_CONF_FQID,
2416+ cmd_flags,
2417+ token);
2418+ DPDBG_CMD_GET_DPNI_PRIV_TX_CONF_FQID(cmd, dpni_id, sender_id);
2419+
2420+ /* send command to mc*/
2421+ err = mc_send_command(mc_io, &cmd);
2422+ if (err)
2423+ return err;
2424+
2425+ /* retrieve response parameters */
2426+ DPDBG_RSP_GET_DPNI_PRIV_TX_CONF_FQID(cmd, *fqid);
2427+
2428+ return 0;
2429+}
2430+
2431+int dpdbg_get_dpcon_info(struct fsl_mc_io *mc_io,
2432+ uint32_t cmd_flags,
2433+ uint16_t token,
2434+ int dpcon_id,
2435+ struct dpdbg_dpcon_info *info)
2436+{
2437+ struct mc_command cmd = { 0 };
2438+ int err;
2439+
2440+ /* prepare command */
2441+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_GET_DPCON_INFO,
2442+ cmd_flags,
2443+ token);
2444+ DPDBG_CMD_GET_DPCON_INFO(cmd, dpcon_id);
2445+
2446+ /* send command to mc*/
2447+ err = mc_send_command(mc_io, &cmd);
2448+ if (err)
2449+ return err;
2450+
2451+ /* retrieve response parameters */
2452+ DPDBG_RSP_GET_DPCON_INFO(cmd, info);
2453+
2454+ return 0;
2455+}
2456+
2457+int dpdbg_get_dpbp_info(struct fsl_mc_io *mc_io,
2458+ uint32_t cmd_flags,
2459+ uint16_t token,
2460+ int dpbp_id,
2461+ struct dpdbg_dpbp_info *info)
2462+{
2463+ struct mc_command cmd = { 0 };
2464+ int err;
2465+
2466+ /* prepare command */
2467+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_GET_DPBP_INFO,
2468+ cmd_flags,
2469+ token);
2470+ DPDBG_CMD_GET_DPBP_INFO(cmd, dpbp_id);
2471+
2472+ /* send command to mc*/
2473+ err = mc_send_command(mc_io, &cmd);
2474+ if (err)
2475+ return err;
2476+
2477+ /* retrieve response parameters */
2478+ DPDBG_RSP_GET_DPBP_INFO(cmd, info);
2479+
2480+ return 0;
2481+}
2482+
2483+int dpdbg_get_dpci_fqid(struct fsl_mc_io *mc_io,
2484+ uint32_t cmd_flags,
2485+ uint16_t token,
2486+ int dpci_id,
2487+ uint8_t priority,
2488+ uint32_t *fqid)
2489+{
2490+ struct mc_command cmd = { 0 };
2491+ int err;
2492+
2493+ /* prepare command */
2494+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_GET_DPBP_INFO,
2495+ cmd_flags,
2496+ token);
2497+ DPDBG_CMD_GET_DPCI_FQID(cmd, dpci_id, priority);
2498+
2499+ /* send command to mc*/
2500+ err = mc_send_command(mc_io, &cmd);
2501+ if (err)
2502+ return err;
2503+
2504+ /* retrieve response parameters */
2505+ DPDBG_RSP_GET_DPCI_FQID(cmd, *fqid);
2506+
2507+ return 0;
2508+}
2509+
2510+int dpdbg_prepare_ctlu_global_rule(struct dpkg_profile_cfg *dpkg_rule,
2511+ uint8_t *rule_buf)
2512+{
2513+ int i, j;
2514+ int offset = 0;
2515+ int param = 1;
2516+ uint64_t *params = (uint64_t *)rule_buf;
2517+
2518+ if (!rule_buf || !dpkg_rule)
2519+ return -EINVAL;
2520+
2521+ params[0] |= mc_enc(0, 8, dpkg_rule->num_extracts);
2522+ params[0] = cpu_to_le64(params[0]);
2523+
2524+ if (dpkg_rule->num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS)
2525+ return -EINVAL;
2526+
2527+ for (i = 0; i < dpkg_rule->num_extracts; i++) {
2528+ switch (dpkg_rule->extracts[i].type) {
2529+ case DPKG_EXTRACT_FROM_HDR:
2530+ params[param] |= mc_enc(0, 8,
2531+ dpkg_rule->extracts[i].extract.from_hdr.prot);
2532+ params[param] |= mc_enc(8, 4,
2533+ dpkg_rule->extracts[i].extract.from_hdr.type);
2534+ params[param] |= mc_enc(16, 8,
2535+ dpkg_rule->extracts[i].extract.from_hdr.size);
2536+ params[param] |= mc_enc(24, 8,
2537+ dpkg_rule->extracts[i].extract.from_hdr.offset);
2538+ params[param] |= mc_enc(32, 32,
2539+ dpkg_rule->extracts[i].extract.from_hdr.field);
2540+ params[param] = cpu_to_le64(params[param]);
2541+ param++;
2542+ params[param] |= mc_enc(0, 8,
2543+ dpkg_rule->extracts[i].extract.
2544+ from_hdr.hdr_index);
2545+ break;
2546+ case DPKG_EXTRACT_FROM_DATA:
2547+ params[param] |= mc_enc(16, 8,
2548+ dpkg_rule->extracts[i].extract.from_data.size);
2549+ params[param] |= mc_enc(24, 8,
2550+ dpkg_rule->extracts[i].extract.
2551+ from_data.offset);
2552+ params[param] = cpu_to_le64(params[param]);
2553+ param++;
2554+ break;
2555+ case DPKG_EXTRACT_FROM_PARSE:
2556+ params[param] |= mc_enc(16, 8,
2557+ dpkg_rule->extracts[i].extract.from_parse.size);
2558+ params[param] |= mc_enc(24, 8,
2559+ dpkg_rule->extracts[i].extract.
2560+ from_parse.offset);
2561+ params[param] = cpu_to_le64(params[param]);
2562+ param++;
2563+ break;
2564+ default:
2565+ return -EINVAL;
2566+ }
2567+ params[param] |= mc_enc(
2568+ 24, 8, dpkg_rule->extracts[i].num_of_byte_masks);
2569+ params[param] |= mc_enc(32, 4, dpkg_rule->extracts[i].type);
2570+ params[param] = cpu_to_le64(params[param]);
2571+ param++;
2572+ for (offset = 0, j = 0;
2573+ j < DPKG_NUM_OF_MASKS;
2574+ offset += 16, j++) {
2575+ params[param] |= mc_enc(
2576+ (offset), 8,
2577+ dpkg_rule->extracts[i].masks[j].mask);
2578+ params[param] |= mc_enc(
2579+ (offset + 8), 8,
2580+ dpkg_rule->extracts[i].masks[j].offset);
2581+ }
2582+ params[param] = cpu_to_le64(params[param]);
2583+ param++;
2584+ }
2585+ return 0;
2586+}
2587+
2588+int dpdbg_set_ctlu_global_marking(struct fsl_mc_io *mc_io,
2589+ uint32_t cmd_flags,
2590+ uint16_t token,
2591+ uint8_t marking,
2592+ struct dpdbg_rule_cfg *cfg)
2593+{
2594+ struct mc_command cmd = { 0 };
2595+
2596+ /* prepare command */
2597+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_SET_CTLU_GLOBAL_MARKING,
2598+ cmd_flags,
2599+ token);
2600+ DPDBG_CMD_SET_CTLU_GLOBAL_MARKING(cmd, marking, cfg);
2601+
2602+ /* send command to mc*/
2603+ return mc_send_command(mc_io, &cmd);
2604+}
2605+
2606+int dpdbg_set_dpni_rx_marking(struct fsl_mc_io *mc_io,
2607+ uint32_t cmd_flags,
2608+ uint16_t token,
2609+ int dpni_id,
2610+ struct dpdbg_dpni_rx_marking_cfg *cfg)
2611+{
2612+ struct mc_command cmd = { 0 };
2613+
2614+ /* prepare command */
2615+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_SET_DPNI_RX_MARKING,
2616+ cmd_flags,
2617+ token);
2618+ DPDBG_CMD_SET_DPNI_RX_MARKING(cmd, dpni_id, cfg);
2619+
2620+ /* send command to mc*/
2621+ return mc_send_command(mc_io, &cmd);
2622+}
2623+
2624+int dpdbg_set_dpni_tx_conf_marking(struct fsl_mc_io *mc_io,
2625+ uint32_t cmd_flags,
2626+ uint16_t token,
2627+ int dpni_id,
2628+ uint16_t sender_id,
2629+ uint8_t marking)
2630+{
2631+ struct mc_command cmd = { 0 };
2632+
2633+ /* prepare command */
2634+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_SET_DPNI_TX_CONF_MARKING,
2635+ cmd_flags,
2636+ token);
2637+ DPDBG_CMD_SET_DPNI_TX_CONF_MARKING(cmd, dpni_id, sender_id, marking);
2638+
2639+ /* send command to mc*/
2640+ return mc_send_command(mc_io, &cmd);
2641+}
2642+
2643+int dpdbg_set_dpio_marking(struct fsl_mc_io *mc_io,
2644+ uint32_t cmd_flags,
2645+ uint16_t token,
2646+ int dpio_id,
2647+ uint8_t marking)
2648+{
2649+ struct mc_command cmd = { 0 };
2650+
2651+ /* prepare command */
2652+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_SET_DPIO_MARKING,
2653+ cmd_flags,
2654+ token);
2655+ DPDBG_CMD_SET_DPIO_MARKING(cmd, dpio_id, marking);
2656+
2657+ /* send command to mc*/
2658+ return mc_send_command(mc_io, &cmd);
2659+}
2660+
2661+int dpdbg_set_ctlu_global_trace(struct fsl_mc_io *mc_io,
2662+ uint32_t cmd_flags,
2663+ uint16_t token,
2664+ struct dpdbg_rule_cfg *cfg)
2665+{
2666+ struct mc_command cmd = { 0 };
2667+
2668+ /* prepare command */
2669+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_SET_CTLU_GLOBAL_TRACE,
2670+ cmd_flags,
2671+ token);
2672+ DPDBG_CMD_SET_CTLU_GLOBAL_TRACE(cmd, cfg);
2673+
2674+ /* send command to mc*/
2675+ return mc_send_command(mc_io, &cmd);
2676+}
2677+
2678+int dpdbg_set_dpio_trace(struct fsl_mc_io *mc_io,
2679+ uint32_t cmd_flags,
2680+ uint16_t token,
2681+ int dpio_id,
2682+ struct dpdbg_dpio_trace_cfg
2683+ trace_point[DPDBG_NUM_OF_DPIO_TRACE_POINTS])
2684+{
2685+ struct mc_command cmd = { 0 };
2686+
2687+ /* prepare command */
2688+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_SET_DPIO_TRACE,
2689+ cmd_flags,
2690+ token);
2691+ DPDBG_CMD_SET_DPIO_TRACE(cmd, dpio_id, trace_point);
2692+
2693+ /* send command to mc*/
2694+ return mc_send_command(mc_io, &cmd);
2695+}
2696+
2697+int dpdbg_set_dpni_rx_trace(struct fsl_mc_io *mc_io,
2698+ uint32_t cmd_flags,
2699+ uint16_t token,
2700+ int dpni_id,
2701+ struct dpdbg_dpni_rx_trace_cfg *trace_cfg)
2702+{
2703+ struct mc_command cmd = { 0 };
2704+
2705+ /* prepare command */
2706+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_SET_DPNI_RX_TRACE,
2707+ cmd_flags,
2708+ token);
2709+ DPDBG_CMD_SET_DPNI_RX_TRACE(cmd, dpni_id, trace_cfg);
2710+
2711+ /* send command to mc*/
2712+ return mc_send_command(mc_io, &cmd);
2713+}
2714+
2715+int dpdbg_set_dpni_tx_trace(struct fsl_mc_io *mc_io,
2716+ uint32_t cmd_flags,
2717+ uint16_t token,
2718+ int dpni_id,
2719+ uint16_t sender_id,
2720+ struct dpdbg_dpni_tx_trace_cfg *trace_cfg)
2721+{
2722+ struct mc_command cmd = { 0 };
2723+
2724+ /* prepare command */
2725+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_SET_DPNI_TX_TRACE,
2726+ cmd_flags,
2727+ token);
2728+ DPDBG_CMD_SET_DPNI_TX_TRACE(cmd, dpni_id, sender_id, trace_cfg);
2729+
2730+ /* send command to mc*/
2731+ return mc_send_command(mc_io, &cmd);
2732+}
2733+
2734+int dpdbg_set_dpcon_trace(struct fsl_mc_io *mc_io,
2735+ uint32_t cmd_flags,
2736+ uint16_t token,
2737+ int dpcon_id,
2738+ struct dpdbg_dpcon_trace_cfg
2739+ trace_point[DPDBG_NUM_OF_DPCON_TRACE_POINTS])
2740+{
2741+ struct mc_command cmd = { 0 };
2742+
2743+ /* prepare command */
2744+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_SET_DPCON_TRACE,
2745+ cmd_flags,
2746+ token);
2747+ DPDBG_CMD_SET_DPCON_TRACE(cmd, dpcon_id, trace_point);
2748+
2749+ /* send command to mc*/
2750+ return mc_send_command(mc_io, &cmd);
2751+}
2752+
2753+int dpdbg_set_dpseci_trace(struct fsl_mc_io *mc_io,
2754+ uint32_t cmd_flags,
2755+ uint16_t token,
2756+ int dpseci_id,
2757+ struct dpdbg_dpseci_trace_cfg
2758+ trace_point[DPDBG_NUM_OF_DPSECI_TRACE_POINTS])
2759+{
2760+ struct mc_command cmd = { 0 };
2761+
2762+ /* prepare command */
2763+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_SET_DPSECI_TRACE,
2764+ cmd_flags,
2765+ token);
2766+ DPDBG_CMD_SET_DPSECI_TRACE(cmd, dpseci_id, trace_point);
2767+
2768+ /* send command to mc*/
2769+ return mc_send_command(mc_io, &cmd);
2770+}
2771+
2772+int dpdbg_get_dpmac_counter(struct fsl_mc_io *mc_io,
2773+ uint32_t cmd_flags,
2774+ uint16_t token,
2775+ int dpmac_id,
2776+ enum dpmac_counter counter_type,
2777+ uint64_t *counter)
2778+{
2779+ struct mc_command cmd = { 0 };
2780+ int err;
2781+
2782+ /* prepare command */
2783+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_GET_DPMAC_COUNTER,
2784+ cmd_flags,
2785+ token);
2786+ DPDBG_CMD_GET_DPMAC_COUNTER(cmd, dpmac_id, counter_type);
2787+
2788+ /* send command to mc*/
2789+ err = mc_send_command(mc_io, &cmd);
2790+ if (err)
2791+ return err;
2792+
2793+ /* retrieve response parameters */
2794+ DPDBG_RSP_GET_DPMAC_COUNTER(cmd, *counter);
2795+
2796+ return 0;
2797+}
2798+
2799+int dpdbg_get_dpni_counter(struct fsl_mc_io *mc_io,
2800+ uint32_t cmd_flags,
2801+ uint16_t token,
2802+ int dpni_id,
2803+ enum dpni_counter counter_type,
2804+ uint64_t *counter)
2805+{
2806+ struct mc_command cmd = { 0 };
2807+ int err;
2808+
2809+ /* prepare command */
2810+ cmd.header = mc_encode_cmd_header(DPDBG_CMDID_GET_DPNI_COUNTER,
2811+ cmd_flags,
2812+ token);
2813+ DPDBG_CMD_GET_DPMAC_COUNTER(cmd, dpni_id, counter_type);
2814+
2815+ /* send command to mc*/
2816+ err = mc_send_command(mc_io, &cmd);
2817+ if (err)
2818+ return err;
2819+
2820+ /* retrieve response parameters */
2821+ DPDBG_RSP_GET_DPNI_COUNTER(cmd, *counter);
2822+
2823+ return 0;
2824+}
2825diff --git a/drivers/net/dpaa2/mc/dpdcei.c b/drivers/net/dpaa2/mc/dpdcei.c
2826new file mode 100644
2827index 0000000..a5c4c47
2828--- /dev/null
2829+++ b/drivers/net/dpaa2/mc/dpdcei.c
2830@@ -0,0 +1,449 @@
2831+/* Copyright 2013-2015 Freescale Semiconductor Inc.
2832+ *
2833+ * Redistribution and use in source and binary forms, with or without
2834+ * modification, are permitted provided that the following conditions are met:
2835+ * * Redistributions of source code must retain the above copyright
2836+ * notice, this list of conditions and the following disclaimer.
2837+ * * Redistributions in binary form must reproduce the above copyright
2838+ * notice, this list of conditions and the following disclaimer in the
2839+ * documentation and/or other materials provided with the distribution.
2840+ * * Neither the name of the above-listed copyright holders nor the
2841+ * names of any contributors may be used to endorse or promote products
2842+ * derived from this software without specific prior written permission.
2843+ *
2844+ *
2845+ * ALTERNATIVELY, this software may be distributed under the terms of the
2846+ * GNU General Public License ("GPL") as published by the Free Software
2847+ * Foundation, either version 2 of that License or (at your option) any
2848+ * later version.
2849+ *
2850+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
2851+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2852+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2853+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
2854+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2855+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2856+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2857+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2858+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2859+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2860+ * POSSIBILITY OF SUCH DAMAGE.
2861+ */
2862+#include <fsl_mc_sys.h>
2863+#include <fsl_mc_cmd.h>
2864+#include <fsl_dpdcei.h>
2865+#include <fsl_dpdcei_cmd.h>
2866+
2867+int dpdcei_open(struct fsl_mc_io *mc_io,
2868+ uint32_t cmd_flags,
2869+ int dpdcei_id,
2870+ uint16_t *token)
2871+{
2872+ struct mc_command cmd = { 0 };
2873+ int err;
2874+
2875+ /* prepare command */
2876+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_OPEN,
2877+ cmd_flags,
2878+ 0);
2879+ DPDCEI_CMD_OPEN(cmd, dpdcei_id);
2880+
2881+ /* send command to mc*/
2882+ err = mc_send_command(mc_io, &cmd);
2883+ if (err)
2884+ return err;
2885+
2886+ /* retrieve response parameters */
2887+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
2888+
2889+ return 0;
2890+}
2891+
2892+int dpdcei_close(struct fsl_mc_io *mc_io,
2893+ uint32_t cmd_flags,
2894+ uint16_t token)
2895+{
2896+ struct mc_command cmd = { 0 };
2897+
2898+ /* prepare command */
2899+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_CLOSE,
2900+ cmd_flags,
2901+ token);
2902+
2903+ /* send command to mc*/
2904+ return mc_send_command(mc_io, &cmd);
2905+}
2906+
2907+int dpdcei_create(struct fsl_mc_io *mc_io,
2908+ uint32_t cmd_flags,
2909+ const struct dpdcei_cfg *cfg,
2910+ uint16_t *token)
2911+{
2912+ struct mc_command cmd = { 0 };
2913+ int err;
2914+
2915+ /* prepare command */
2916+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_CREATE,
2917+ cmd_flags,
2918+ 0);
2919+ DPDCEI_CMD_CREATE(cmd, cfg);
2920+
2921+ /* send command to mc*/
2922+ err = mc_send_command(mc_io, &cmd);
2923+ if (err)
2924+ return err;
2925+
2926+ /* retrieve response parameters */
2927+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
2928+
2929+ return 0;
2930+}
2931+
2932+int dpdcei_destroy(struct fsl_mc_io *mc_io,
2933+ uint32_t cmd_flags,
2934+ uint16_t token)
2935+{
2936+ struct mc_command cmd = { 0 };
2937+
2938+ /* prepare command */
2939+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_DESTROY,
2940+ cmd_flags,
2941+ token);
2942+
2943+ /* send command to mc*/
2944+ return mc_send_command(mc_io, &cmd);
2945+}
2946+
2947+int dpdcei_enable(struct fsl_mc_io *mc_io,
2948+ uint32_t cmd_flags,
2949+ uint16_t token)
2950+{
2951+ struct mc_command cmd = { 0 };
2952+
2953+ /* prepare command */
2954+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_ENABLE,
2955+ cmd_flags,
2956+ token);
2957+
2958+ /* send command to mc*/
2959+ return mc_send_command(mc_io, &cmd);
2960+}
2961+
2962+int dpdcei_disable(struct fsl_mc_io *mc_io,
2963+ uint32_t cmd_flags,
2964+ uint16_t token)
2965+{
2966+ struct mc_command cmd = { 0 };
2967+
2968+ /* prepare command */
2969+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_DISABLE,
2970+ cmd_flags,
2971+ token);
2972+
2973+ /* send command to mc*/
2974+ return mc_send_command(mc_io, &cmd);
2975+}
2976+
2977+int dpdcei_is_enabled(struct fsl_mc_io *mc_io,
2978+ uint32_t cmd_flags,
2979+ uint16_t token,
2980+ int *en)
2981+{
2982+ struct mc_command cmd = { 0 };
2983+ int err;
2984+ /* prepare command */
2985+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_IS_ENABLED,
2986+ cmd_flags,
2987+ token);
2988+
2989+ /* send command to mc*/
2990+ err = mc_send_command(mc_io, &cmd);
2991+ if (err)
2992+ return err;
2993+
2994+ /* retrieve response parameters */
2995+ DPDCEI_RSP_IS_ENABLED(cmd, *en);
2996+
2997+ return 0;
2998+}
2999+
3000+int dpdcei_reset(struct fsl_mc_io *mc_io,
3001+ uint32_t cmd_flags,
3002+ uint16_t token)
3003+{
3004+ struct mc_command cmd = { 0 };
3005+
3006+ /* prepare command */
3007+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_RESET,
3008+ cmd_flags,
3009+ token);
3010+
3011+ /* send command to mc*/
3012+ return mc_send_command(mc_io, &cmd);
3013+}
3014+
3015+int dpdcei_get_irq(struct fsl_mc_io *mc_io,
3016+ uint32_t cmd_flags,
3017+ uint16_t token,
3018+ uint8_t irq_index,
3019+ int *type,
3020+ struct dpdcei_irq_cfg *irq_cfg)
3021+{
3022+ struct mc_command cmd = { 0 };
3023+ int err;
3024+
3025+ /* prepare command */
3026+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_GET_IRQ,
3027+ cmd_flags,
3028+ token);
3029+ DPDCEI_CMD_GET_IRQ(cmd, irq_index);
3030+
3031+ /* send command to mc*/
3032+ err = mc_send_command(mc_io, &cmd);
3033+ if (err)
3034+ return err;
3035+
3036+ /* retrieve response parameters */
3037+ DPDCEI_RSP_GET_IRQ(cmd, *type, irq_cfg);
3038+
3039+ return 0;
3040+}
3041+
3042+int dpdcei_set_irq(struct fsl_mc_io *mc_io,
3043+ uint32_t cmd_flags,
3044+ uint16_t token,
3045+ uint8_t irq_index,
3046+ struct dpdcei_irq_cfg *irq_cfg)
3047+{
3048+ struct mc_command cmd = { 0 };
3049+
3050+ /* prepare command */
3051+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_SET_IRQ,
3052+ cmd_flags,
3053+ token);
3054+ DPDCEI_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
3055+
3056+ /* send command to mc*/
3057+ return mc_send_command(mc_io, &cmd);
3058+}
3059+
3060+int dpdcei_get_irq_enable(struct fsl_mc_io *mc_io,
3061+ uint32_t cmd_flags,
3062+ uint16_t token,
3063+ uint8_t irq_index,
3064+ uint8_t *en)
3065+{
3066+ struct mc_command cmd = { 0 };
3067+ int err;
3068+
3069+ /* prepare command */
3070+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_GET_IRQ_ENABLE,
3071+ cmd_flags,
3072+ token);
3073+ DPDCEI_CMD_GET_IRQ_ENABLE(cmd, irq_index);
3074+
3075+ /* send command to mc*/
3076+ err = mc_send_command(mc_io, &cmd);
3077+ if (err)
3078+ return err;
3079+
3080+ /* retrieve response parameters */
3081+ DPDCEI_RSP_GET_IRQ_ENABLE(cmd, *en);
3082+
3083+ return 0;
3084+}
3085+
3086+int dpdcei_set_irq_enable(struct fsl_mc_io *mc_io,
3087+ uint32_t cmd_flags,
3088+ uint16_t token,
3089+ uint8_t irq_index,
3090+ uint8_t en)
3091+{
3092+ struct mc_command cmd = { 0 };
3093+
3094+ /* prepare command */
3095+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_SET_IRQ_ENABLE,
3096+ cmd_flags,
3097+ token);
3098+ DPDCEI_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
3099+
3100+ /* send command to mc*/
3101+ return mc_send_command(mc_io, &cmd);
3102+}
3103+
3104+int dpdcei_get_irq_mask(struct fsl_mc_io *mc_io,
3105+ uint32_t cmd_flags,
3106+ uint16_t token,
3107+ uint8_t irq_index,
3108+ uint32_t *mask)
3109+{
3110+ struct mc_command cmd = { 0 };
3111+ int err;
3112+
3113+ /* prepare command */
3114+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_GET_IRQ_MASK,
3115+ cmd_flags,
3116+ token);
3117+ DPDCEI_CMD_GET_IRQ_MASK(cmd, irq_index);
3118+
3119+ /* send command to mc*/
3120+ err = mc_send_command(mc_io, &cmd);
3121+ if (err)
3122+ return err;
3123+
3124+ /* retrieve response parameters */
3125+ DPDCEI_RSP_GET_IRQ_MASK(cmd, *mask);
3126+
3127+ return 0;
3128+}
3129+
3130+int dpdcei_set_irq_mask(struct fsl_mc_io *mc_io,
3131+ uint32_t cmd_flags,
3132+ uint16_t token,
3133+ uint8_t irq_index,
3134+ uint32_t mask)
3135+{
3136+ struct mc_command cmd = { 0 };
3137+
3138+ /* prepare command */
3139+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_SET_IRQ_MASK,
3140+ cmd_flags,
3141+ token);
3142+ DPDCEI_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
3143+
3144+ /* send command to mc*/
3145+ return mc_send_command(mc_io, &cmd);
3146+}
3147+
3148+int dpdcei_get_irq_status(struct fsl_mc_io *mc_io,
3149+ uint32_t cmd_flags,
3150+ uint16_t token,
3151+ uint8_t irq_index,
3152+ uint32_t *status)
3153+{
3154+ struct mc_command cmd = { 0 };
3155+ int err;
3156+
3157+ /* prepare command */
3158+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_GET_IRQ_STATUS,
3159+ cmd_flags,
3160+ token);
3161+ DPDCEI_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
3162+
3163+ /* send command to mc*/
3164+ err = mc_send_command(mc_io, &cmd);
3165+ if (err)
3166+ return err;
3167+
3168+ /* retrieve response parameters */
3169+ DPDCEI_RSP_GET_IRQ_STATUS(cmd, *status);
3170+
3171+ return 0;
3172+}
3173+
3174+int dpdcei_clear_irq_status(struct fsl_mc_io *mc_io,
3175+ uint32_t cmd_flags,
3176+ uint16_t token,
3177+ uint8_t irq_index,
3178+ uint32_t status)
3179+{
3180+ struct mc_command cmd = { 0 };
3181+
3182+ /* prepare command */
3183+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_CLEAR_IRQ_STATUS,
3184+ cmd_flags,
3185+ token);
3186+ DPDCEI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
3187+
3188+ /* send command to mc*/
3189+ return mc_send_command(mc_io, &cmd);
3190+}
3191+
3192+int dpdcei_get_attributes(struct fsl_mc_io *mc_io,
3193+ uint32_t cmd_flags,
3194+ uint16_t token,
3195+ struct dpdcei_attr *attr)
3196+{
3197+ struct mc_command cmd = { 0 };
3198+ int err;
3199+
3200+ /* prepare command */
3201+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_GET_ATTR,
3202+ cmd_flags,
3203+ token);
3204+
3205+ /* send command to mc*/
3206+ err = mc_send_command(mc_io, &cmd);
3207+ if (err)
3208+ return err;
3209+
3210+ /* retrieve response parameters */
3211+ DPDCEI_RSP_GET_ATTR(cmd, attr);
3212+
3213+ return 0;
3214+}
3215+
3216+int dpdcei_set_rx_queue(struct fsl_mc_io *mc_io,
3217+ uint32_t cmd_flags,
3218+ uint16_t token,
3219+ const struct dpdcei_rx_queue_cfg *cfg)
3220+{
3221+ struct mc_command cmd = { 0 };
3222+
3223+ /* prepare command */
3224+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_SET_RX_QUEUE,
3225+ cmd_flags,
3226+ token);
3227+ DPDCEI_CMD_SET_RX_QUEUE(cmd, cfg);
3228+
3229+ /* send command to mc*/
3230+ return mc_send_command(mc_io, &cmd);
3231+}
3232+
3233+int dpdcei_get_rx_queue(struct fsl_mc_io *mc_io,
3234+ uint32_t cmd_flags,
3235+ uint16_t token,
3236+ struct dpdcei_rx_queue_attr *attr)
3237+{
3238+ struct mc_command cmd = { 0 };
3239+ int err;
3240+
3241+ /* prepare command */
3242+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_GET_RX_QUEUE,
3243+ cmd_flags,
3244+ token);
3245+
3246+ /* send command to mc*/
3247+ err = mc_send_command(mc_io, &cmd);
3248+ if (err)
3249+ return err;
3250+
3251+ /* retrieve response parameters */
3252+ DPDCEI_RSP_GET_RX_QUEUE(cmd, attr);
3253+
3254+ return 0;
3255+}
3256+
3257+int dpdcei_get_tx_queue(struct fsl_mc_io *mc_io,
3258+ uint32_t cmd_flags,
3259+ uint16_t token,
3260+ struct dpdcei_tx_queue_attr *attr)
3261+{
3262+ struct mc_command cmd = { 0 };
3263+ int err;
3264+
3265+ /* prepare command */
3266+ cmd.header = mc_encode_cmd_header(DPDCEI_CMDID_GET_TX_QUEUE,
3267+ cmd_flags,
3268+ token);
3269+
3270+ /* send command to mc*/
3271+ err = mc_send_command(mc_io, &cmd);
3272+ if (err)
3273+ return err;
3274+
3275+ /* retrieve response parameters */
3276+ DPDCEI_RSP_GET_TX_QUEUE(cmd, attr);
3277+
3278+ return 0;
3279+}
3280diff --git a/drivers/net/dpaa2/mc/dpdmai.c b/drivers/net/dpaa2/mc/dpdmai.c
3281new file mode 100644
3282index 0000000..154d2c6
3283--- /dev/null
3284+++ b/drivers/net/dpaa2/mc/dpdmai.c
3285@@ -0,0 +1,452 @@
3286+/* Copyright 2013-2015 Freescale Semiconductor Inc.
3287+ *
3288+ * Redistribution and use in source and binary forms, with or without
3289+ * modification, are permitted provided that the following conditions are met:
3290+ * * Redistributions of source code must retain the above copyright
3291+ * notice, this list of conditions and the following disclaimer.
3292+ * * Redistributions in binary form must reproduce the above copyright
3293+ * notice, this list of conditions and the following disclaimer in the
3294+ * documentation and/or other materials provided with the distribution.
3295+ * * Neither the name of the above-listed copyright holders nor the
3296+ * names of any contributors may be used to endorse or promote products
3297+ * derived from this software without specific prior written permission.
3298+ *
3299+ *
3300+ * ALTERNATIVELY, this software may be distributed under the terms of the
3301+ * GNU General Public License ("GPL") as published by the Free Software
3302+ * Foundation, either version 2 of that License or (at your option) any
3303+ * later version.
3304+ *
3305+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
3306+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
3307+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
3308+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
3309+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
3310+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
3311+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
3312+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
3313+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
3314+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
3315+ * POSSIBILITY OF SUCH DAMAGE.
3316+ */
3317+#include <fsl_mc_sys.h>
3318+#include <fsl_mc_cmd.h>
3319+#include <fsl_dpdmai.h>
3320+#include <fsl_dpdmai_cmd.h>
3321+
3322+int dpdmai_open(struct fsl_mc_io *mc_io,
3323+ uint32_t cmd_flags,
3324+ int dpdmai_id,
3325+ uint16_t *token)
3326+{
3327+ struct mc_command cmd = { 0 };
3328+ int err;
3329+
3330+ /* prepare command */
3331+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN,
3332+ cmd_flags,
3333+ 0);
3334+ DPDMAI_CMD_OPEN(cmd, dpdmai_id);
3335+
3336+ /* send command to mc*/
3337+ err = mc_send_command(mc_io, &cmd);
3338+ if (err)
3339+ return err;
3340+
3341+ /* retrieve response parameters */
3342+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
3343+
3344+ return 0;
3345+}
3346+
3347+int dpdmai_close(struct fsl_mc_io *mc_io,
3348+ uint32_t cmd_flags,
3349+ uint16_t token)
3350+{
3351+ struct mc_command cmd = { 0 };
3352+
3353+ /* prepare command */
3354+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CLOSE,
3355+ cmd_flags, token);
3356+
3357+ /* send command to mc*/
3358+ return mc_send_command(mc_io, &cmd);
3359+}
3360+
3361+int dpdmai_create(struct fsl_mc_io *mc_io,
3362+ uint32_t cmd_flags,
3363+ const struct dpdmai_cfg *cfg,
3364+ uint16_t *token)
3365+{
3366+ struct mc_command cmd = { 0 };
3367+ int err;
3368+
3369+ /* prepare command */
3370+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CREATE,
3371+ cmd_flags,
3372+ 0);
3373+ DPDMAI_CMD_CREATE(cmd, cfg);
3374+
3375+ /* send command to mc*/
3376+ err = mc_send_command(mc_io, &cmd);
3377+ if (err)
3378+ return err;
3379+
3380+ /* retrieve response parameters */
3381+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
3382+
3383+ return 0;
3384+}
3385+
3386+int dpdmai_destroy(struct fsl_mc_io *mc_io,
3387+ uint32_t cmd_flags,
3388+ uint16_t token)
3389+{
3390+ struct mc_command cmd = { 0 };
3391+
3392+ /* prepare command */
3393+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_DESTROY,
3394+ cmd_flags,
3395+ token);
3396+
3397+ /* send command to mc*/
3398+ return mc_send_command(mc_io, &cmd);
3399+}
3400+
3401+int dpdmai_enable(struct fsl_mc_io *mc_io,
3402+ uint32_t cmd_flags,
3403+ uint16_t token)
3404+{
3405+ struct mc_command cmd = { 0 };
3406+
3407+ /* prepare command */
3408+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_ENABLE,
3409+ cmd_flags,
3410+ token);
3411+
3412+ /* send command to mc*/
3413+ return mc_send_command(mc_io, &cmd);
3414+}
3415+
3416+int dpdmai_disable(struct fsl_mc_io *mc_io,
3417+ uint32_t cmd_flags,
3418+ uint16_t token)
3419+{
3420+ struct mc_command cmd = { 0 };
3421+
3422+ /* prepare command */
3423+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_DISABLE,
3424+ cmd_flags,
3425+ token);
3426+
3427+ /* send command to mc*/
3428+ return mc_send_command(mc_io, &cmd);
3429+}
3430+
3431+int dpdmai_is_enabled(struct fsl_mc_io *mc_io,
3432+ uint32_t cmd_flags,
3433+ uint16_t token,
3434+ int *en)
3435+{
3436+ struct mc_command cmd = { 0 };
3437+ int err;
3438+ /* prepare command */
3439+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_IS_ENABLED,
3440+ cmd_flags,
3441+ token);
3442+
3443+ /* send command to mc*/
3444+ err = mc_send_command(mc_io, &cmd);
3445+ if (err)
3446+ return err;
3447+
3448+ /* retrieve response parameters */
3449+ DPDMAI_RSP_IS_ENABLED(cmd, *en);
3450+
3451+ return 0;
3452+}
3453+
3454+int dpdmai_reset(struct fsl_mc_io *mc_io,
3455+ uint32_t cmd_flags,
3456+ uint16_t token)
3457+{
3458+ struct mc_command cmd = { 0 };
3459+
3460+ /* prepare command */
3461+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_RESET,
3462+ cmd_flags,
3463+ token);
3464+
3465+ /* send command to mc*/
3466+ return mc_send_command(mc_io, &cmd);
3467+}
3468+
3469+int dpdmai_get_irq(struct fsl_mc_io *mc_io,
3470+ uint32_t cmd_flags,
3471+ uint16_t token,
3472+ uint8_t irq_index,
3473+ int *type,
3474+ struct dpdmai_irq_cfg *irq_cfg)
3475+{
3476+ struct mc_command cmd = { 0 };
3477+ int err;
3478+
3479+ /* prepare command */
3480+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_IRQ,
3481+ cmd_flags,
3482+ token);
3483+ DPDMAI_CMD_GET_IRQ(cmd, irq_index);
3484+
3485+ /* send command to mc*/
3486+ err = mc_send_command(mc_io, &cmd);
3487+ if (err)
3488+ return err;
3489+
3490+ /* retrieve response parameters */
3491+ DPDMAI_RSP_GET_IRQ(cmd, *type, irq_cfg);
3492+
3493+ return 0;
3494+}
3495+
3496+int dpdmai_set_irq(struct fsl_mc_io *mc_io,
3497+ uint32_t cmd_flags,
3498+ uint16_t token,
3499+ uint8_t irq_index,
3500+ struct dpdmai_irq_cfg *irq_cfg)
3501+{
3502+ struct mc_command cmd = { 0 };
3503+
3504+ /* prepare command */
3505+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_IRQ,
3506+ cmd_flags,
3507+ token);
3508+ DPDMAI_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
3509+
3510+ /* send command to mc*/
3511+ return mc_send_command(mc_io, &cmd);
3512+}
3513+
3514+int dpdmai_get_irq_enable(struct fsl_mc_io *mc_io,
3515+ uint32_t cmd_flags,
3516+ uint16_t token,
3517+ uint8_t irq_index,
3518+ uint8_t *en)
3519+{
3520+ struct mc_command cmd = { 0 };
3521+ int err;
3522+
3523+ /* prepare command */
3524+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_IRQ_ENABLE,
3525+ cmd_flags,
3526+ token);
3527+ DPDMAI_CMD_GET_IRQ_ENABLE(cmd, irq_index);
3528+
3529+ /* send command to mc*/
3530+ err = mc_send_command(mc_io, &cmd);
3531+ if (err)
3532+ return err;
3533+
3534+ /* retrieve response parameters */
3535+ DPDMAI_RSP_GET_IRQ_ENABLE(cmd, *en);
3536+
3537+ return 0;
3538+}
3539+
3540+int dpdmai_set_irq_enable(struct fsl_mc_io *mc_io,
3541+ uint32_t cmd_flags,
3542+ uint16_t token,
3543+ uint8_t irq_index,
3544+ uint8_t en)
3545+{
3546+ struct mc_command cmd = { 0 };
3547+
3548+ /* prepare command */
3549+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_IRQ_ENABLE,
3550+ cmd_flags,
3551+ token);
3552+ DPDMAI_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
3553+
3554+ /* send command to mc*/
3555+ return mc_send_command(mc_io, &cmd);
3556+}
3557+
3558+int dpdmai_get_irq_mask(struct fsl_mc_io *mc_io,
3559+ uint32_t cmd_flags,
3560+ uint16_t token,
3561+ uint8_t irq_index,
3562+ uint32_t *mask)
3563+{
3564+ struct mc_command cmd = { 0 };
3565+ int err;
3566+
3567+ /* prepare command */
3568+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_IRQ_MASK,
3569+ cmd_flags,
3570+ token);
3571+ DPDMAI_CMD_GET_IRQ_MASK(cmd, irq_index);
3572+
3573+ /* send command to mc*/
3574+ err = mc_send_command(mc_io, &cmd);
3575+ if (err)
3576+ return err;
3577+
3578+ /* retrieve response parameters */
3579+ DPDMAI_RSP_GET_IRQ_MASK(cmd, *mask);
3580+
3581+ return 0;
3582+}
3583+
3584+int dpdmai_set_irq_mask(struct fsl_mc_io *mc_io,
3585+ uint32_t cmd_flags,
3586+ uint16_t token,
3587+ uint8_t irq_index,
3588+ uint32_t mask)
3589+{
3590+ struct mc_command cmd = { 0 };
3591+
3592+ /* prepare command */
3593+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_IRQ_MASK,
3594+ cmd_flags,
3595+ token);
3596+ DPDMAI_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
3597+
3598+ /* send command to mc*/
3599+ return mc_send_command(mc_io, &cmd);
3600+}
3601+
3602+int dpdmai_get_irq_status(struct fsl_mc_io *mc_io,
3603+ uint32_t cmd_flags,
3604+ uint16_t token,
3605+ uint8_t irq_index,
3606+ uint32_t *status)
3607+{
3608+ struct mc_command cmd = { 0 };
3609+ int err;
3610+
3611+ /* prepare command */
3612+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_IRQ_STATUS,
3613+ cmd_flags,
3614+ token);
3615+ DPDMAI_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
3616+
3617+ /* send command to mc*/
3618+ err = mc_send_command(mc_io, &cmd);
3619+ if (err)
3620+ return err;
3621+
3622+ /* retrieve response parameters */
3623+ DPDMAI_RSP_GET_IRQ_STATUS(cmd, *status);
3624+
3625+ return 0;
3626+}
3627+
3628+int dpdmai_clear_irq_status(struct fsl_mc_io *mc_io,
3629+ uint32_t cmd_flags,
3630+ uint16_t token,
3631+ uint8_t irq_index,
3632+ uint32_t status)
3633+{
3634+ struct mc_command cmd = { 0 };
3635+
3636+ /* prepare command */
3637+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CLEAR_IRQ_STATUS,
3638+ cmd_flags,
3639+ token);
3640+ DPDMAI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
3641+
3642+ /* send command to mc*/
3643+ return mc_send_command(mc_io, &cmd);
3644+}
3645+
3646+int dpdmai_get_attributes(struct fsl_mc_io *mc_io,
3647+ uint32_t cmd_flags,
3648+ uint16_t token,
3649+ struct dpdmai_attr *attr)
3650+{
3651+ struct mc_command cmd = { 0 };
3652+ int err;
3653+
3654+ /* prepare command */
3655+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_ATTR,
3656+ cmd_flags,
3657+ token);
3658+
3659+ /* send command to mc*/
3660+ err = mc_send_command(mc_io, &cmd);
3661+ if (err)
3662+ return err;
3663+
3664+ /* retrieve response parameters */
3665+ DPDMAI_RSP_GET_ATTR(cmd, attr);
3666+
3667+ return 0;
3668+}
3669+
3670+int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io,
3671+ uint32_t cmd_flags,
3672+ uint16_t token,
3673+ uint8_t priority,
3674+ const struct dpdmai_rx_queue_cfg *cfg)
3675+{
3676+ struct mc_command cmd = { 0 };
3677+
3678+ /* prepare command */
3679+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_RX_QUEUE,
3680+ cmd_flags,
3681+ token);
3682+ DPDMAI_CMD_SET_RX_QUEUE(cmd, priority, cfg);
3683+
3684+ /* send command to mc*/
3685+ return mc_send_command(mc_io, &cmd);
3686+}
3687+
3688+int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io,
3689+ uint32_t cmd_flags,
3690+ uint16_t token,
3691+ uint8_t priority, struct dpdmai_rx_queue_attr *attr)
3692+{
3693+ struct mc_command cmd = { 0 };
3694+ int err;
3695+
3696+ /* prepare command */
3697+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_RX_QUEUE,
3698+ cmd_flags,
3699+ token);
3700+ DPDMAI_CMD_GET_RX_QUEUE(cmd, priority);
3701+
3702+ /* send command to mc*/
3703+ err = mc_send_command(mc_io, &cmd);
3704+ if (err)
3705+ return err;
3706+
3707+ /* retrieve response parameters */
3708+ DPDMAI_RSP_GET_RX_QUEUE(cmd, attr);
3709+
3710+ return 0;
3711+}
3712+
3713+int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io,
3714+ uint32_t cmd_flags,
3715+ uint16_t token,
3716+ uint8_t priority,
3717+ struct dpdmai_tx_queue_attr *attr)
3718+{
3719+ struct mc_command cmd = { 0 };
3720+ int err;
3721+
3722+ /* prepare command */
3723+ cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_TX_QUEUE,
3724+ cmd_flags,
3725+ token);
3726+ DPDMAI_CMD_GET_TX_QUEUE(cmd, priority);
3727+
3728+ /* send command to mc*/
3729+ err = mc_send_command(mc_io, &cmd);
3730+ if (err)
3731+ return err;
3732+
3733+ /* retrieve response parameters */
3734+ DPDMAI_RSP_GET_TX_QUEUE(cmd, attr);
3735+
3736+ return 0;
3737+}
3738diff --git a/drivers/net/dpaa2/mc/dpdmux.c b/drivers/net/dpaa2/mc/dpdmux.c
3739new file mode 100644
3740index 0000000..dc07608
3741--- /dev/null
3742+++ b/drivers/net/dpaa2/mc/dpdmux.c
3743@@ -0,0 +1,567 @@
3744+/* Copyright 2013-2015 Freescale Semiconductor Inc.
3745+ *
3746+ * Redistribution and use in source and binary forms, with or without
3747+ * modification, are permitted provided that the following conditions are met:
3748+ * * Redistributions of source code must retain the above copyright
3749+ * notice, this list of conditions and the following disclaimer.
3750+ * * Redistributions in binary form must reproduce the above copyright
3751+ * notice, this list of conditions and the following disclaimer in the
3752+ * documentation and/or other materials provided with the distribution.
3753+ * * Neither the name of the above-listed copyright holders nor the
3754+ * names of any contributors may be used to endorse or promote products
3755+ * derived from this software without specific prior written permission.
3756+ *
3757+ *
3758+ * ALTERNATIVELY, this software may be distributed under the terms of the
3759+ * GNU General Public License ("GPL") as published by the Free Software
3760+ * Foundation, either version 2 of that License or (at your option) any
3761+ * later version.
3762+ *
3763+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
3764+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
3765+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
3766+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
3767+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
3768+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
3769+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
3770+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
3771+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
3772+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
3773+ * POSSIBILITY OF SUCH DAMAGE.
3774+ */
3775+#include <fsl_mc_sys.h>
3776+#include <fsl_mc_cmd.h>
3777+#include <fsl_dpdmux.h>
3778+#include <fsl_dpdmux_cmd.h>
3779+
3780+int dpdmux_open(struct fsl_mc_io *mc_io,
3781+ uint32_t cmd_flags,
3782+ int dpdmux_id,
3783+ uint16_t *token)
3784+{
3785+ struct mc_command cmd = { 0 };
3786+ int err;
3787+
3788+ /* prepare command */
3789+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_OPEN,
3790+ cmd_flags,
3791+ 0);
3792+ DPDMUX_CMD_OPEN(cmd, dpdmux_id);
3793+
3794+ /* send command to mc*/
3795+ err = mc_send_command(mc_io, &cmd);
3796+ if (err)
3797+ return err;
3798+
3799+ /* retrieve response parameters */
3800+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
3801+
3802+ return 0;
3803+}
3804+
3805+int dpdmux_close(struct fsl_mc_io *mc_io,
3806+ uint32_t cmd_flags,
3807+ uint16_t token)
3808+{
3809+ struct mc_command cmd = { 0 };
3810+
3811+ /* prepare command */
3812+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_CLOSE,
3813+ cmd_flags,
3814+ token);
3815+
3816+ /* send command to mc*/
3817+ return mc_send_command(mc_io, &cmd);
3818+}
3819+
3820+int dpdmux_create(struct fsl_mc_io *mc_io,
3821+ uint32_t cmd_flags,
3822+ const struct dpdmux_cfg *cfg,
3823+ uint16_t *token)
3824+{
3825+ struct mc_command cmd = { 0 };
3826+ int err;
3827+
3828+ /* prepare command */
3829+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_CREATE,
3830+ cmd_flags,
3831+ 0);
3832+ DPDMUX_CMD_CREATE(cmd, cfg);
3833+
3834+ /* send command to mc*/
3835+ err = mc_send_command(mc_io, &cmd);
3836+ if (err)
3837+ return err;
3838+
3839+ /* retrieve response parameters */
3840+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
3841+
3842+ return 0;
3843+}
3844+
3845+int dpdmux_destroy(struct fsl_mc_io *mc_io,
3846+ uint32_t cmd_flags,
3847+ uint16_t token)
3848+{
3849+ struct mc_command cmd = { 0 };
3850+
3851+ /* prepare command */
3852+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_DESTROY,
3853+ cmd_flags,
3854+ token);
3855+
3856+ /* send command to mc*/
3857+ return mc_send_command(mc_io, &cmd);
3858+}
3859+
3860+int dpdmux_enable(struct fsl_mc_io *mc_io,
3861+ uint32_t cmd_flags,
3862+ uint16_t token)
3863+{
3864+ struct mc_command cmd = { 0 };
3865+
3866+ /* prepare command */
3867+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_ENABLE,
3868+ cmd_flags,
3869+ token);
3870+
3871+ /* send command to mc*/
3872+ return mc_send_command(mc_io, &cmd);
3873+}
3874+
3875+int dpdmux_disable(struct fsl_mc_io *mc_io,
3876+ uint32_t cmd_flags,
3877+ uint16_t token)
3878+{
3879+ struct mc_command cmd = { 0 };
3880+
3881+ /* prepare command */
3882+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_DISABLE,
3883+ cmd_flags,
3884+ token);
3885+
3886+ /* send command to mc*/
3887+ return mc_send_command(mc_io, &cmd);
3888+}
3889+
3890+int dpdmux_is_enabled(struct fsl_mc_io *mc_io,
3891+ uint32_t cmd_flags,
3892+ uint16_t token,
3893+ int *en)
3894+{
3895+ struct mc_command cmd = { 0 };
3896+ int err;
3897+ /* prepare command */
3898+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IS_ENABLED,
3899+ cmd_flags,
3900+ token);
3901+
3902+ /* send command to mc*/
3903+ err = mc_send_command(mc_io, &cmd);
3904+ if (err)
3905+ return err;
3906+
3907+ /* retrieve response parameters */
3908+ DPDMUX_RSP_IS_ENABLED(cmd, *en);
3909+
3910+ return 0;
3911+}
3912+
3913+int dpdmux_reset(struct fsl_mc_io *mc_io,
3914+ uint32_t cmd_flags,
3915+ uint16_t token)
3916+{
3917+ struct mc_command cmd = { 0 };
3918+
3919+ /* prepare command */
3920+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_RESET,
3921+ cmd_flags,
3922+ token);
3923+
3924+ /* send command to mc*/
3925+ return mc_send_command(mc_io, &cmd);
3926+}
3927+
3928+int dpdmux_set_irq(struct fsl_mc_io *mc_io,
3929+ uint32_t cmd_flags,
3930+ uint16_t token,
3931+ uint8_t irq_index,
3932+ struct dpdmux_irq_cfg *irq_cfg)
3933+{
3934+ struct mc_command cmd = { 0 };
3935+
3936+ /* prepare command */
3937+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_IRQ,
3938+ cmd_flags,
3939+ token);
3940+ DPDMUX_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
3941+
3942+ /* send command to mc*/
3943+ return mc_send_command(mc_io, &cmd);
3944+}
3945+
3946+int dpdmux_get_irq(struct fsl_mc_io *mc_io,
3947+ uint32_t cmd_flags,
3948+ uint16_t token,
3949+ uint8_t irq_index,
3950+ int *type,
3951+ struct dpdmux_irq_cfg *irq_cfg)
3952+{
3953+ struct mc_command cmd = { 0 };
3954+ int err;
3955+
3956+ /* prepare command */
3957+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ,
3958+ cmd_flags,
3959+ token);
3960+ DPDMUX_CMD_GET_IRQ(cmd, irq_index);
3961+
3962+ /* send command to mc*/
3963+ err = mc_send_command(mc_io, &cmd);
3964+ if (err)
3965+ return err;
3966+
3967+ /* retrieve response parameters */
3968+ DPDMUX_RSP_GET_IRQ(cmd, *type, irq_cfg);
3969+
3970+ return 0;
3971+}
3972+
3973+int dpdmux_set_irq_enable(struct fsl_mc_io *mc_io,
3974+ uint32_t cmd_flags,
3975+ uint16_t token,
3976+ uint8_t irq_index,
3977+ uint8_t en)
3978+{
3979+ struct mc_command cmd = { 0 };
3980+
3981+ /* prepare command */
3982+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_IRQ_ENABLE,
3983+ cmd_flags,
3984+ token);
3985+ DPDMUX_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
3986+
3987+ /* send command to mc*/
3988+ return mc_send_command(mc_io, &cmd);
3989+}
3990+
3991+int dpdmux_get_irq_enable(struct fsl_mc_io *mc_io,
3992+ uint32_t cmd_flags,
3993+ uint16_t token,
3994+ uint8_t irq_index,
3995+ uint8_t *en)
3996+{
3997+ struct mc_command cmd = { 0 };
3998+ int err;
3999+
4000+ /* prepare command */
4001+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ_ENABLE,
4002+ cmd_flags,
4003+ token);
4004+ DPDMUX_CMD_GET_IRQ_ENABLE(cmd, irq_index);
4005+
4006+ /* send command to mc*/
4007+ err = mc_send_command(mc_io, &cmd);
4008+ if (err)
4009+ return err;
4010+
4011+ /* retrieve response parameters */
4012+ DPDMUX_RSP_GET_IRQ_ENABLE(cmd, *en);
4013+
4014+ return 0;
4015+}
4016+
4017+int dpdmux_set_irq_mask(struct fsl_mc_io *mc_io,
4018+ uint32_t cmd_flags,
4019+ uint16_t token,
4020+ uint8_t irq_index,
4021+ uint32_t mask)
4022+{
4023+ struct mc_command cmd = { 0 };
4024+
4025+ /* prepare command */
4026+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_IRQ_MASK,
4027+ cmd_flags,
4028+ token);
4029+ DPDMUX_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
4030+
4031+ /* send command to mc*/
4032+ return mc_send_command(mc_io, &cmd);
4033+}
4034+
4035+int dpdmux_get_irq_mask(struct fsl_mc_io *mc_io,
4036+ uint32_t cmd_flags,
4037+ uint16_t token,
4038+ uint8_t irq_index,
4039+ uint32_t *mask)
4040+{
4041+ struct mc_command cmd = { 0 };
4042+ int err;
4043+
4044+ /* prepare command */
4045+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ_MASK,
4046+ cmd_flags,
4047+ token);
4048+ DPDMUX_CMD_GET_IRQ_MASK(cmd, irq_index);
4049+
4050+ /* send command to mc*/
4051+ err = mc_send_command(mc_io, &cmd);
4052+ if (err)
4053+ return err;
4054+
4055+ /* retrieve response parameters */
4056+ DPDMUX_RSP_GET_IRQ_MASK(cmd, *mask);
4057+
4058+ return 0;
4059+}
4060+
4061+int dpdmux_get_irq_status(struct fsl_mc_io *mc_io,
4062+ uint32_t cmd_flags,
4063+ uint16_t token,
4064+ uint8_t irq_index,
4065+ uint32_t *status)
4066+{
4067+ struct mc_command cmd = { 0 };
4068+ int err;
4069+
4070+ /* prepare command */
4071+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ_STATUS,
4072+ cmd_flags,
4073+ token);
4074+ DPDMUX_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
4075+
4076+ /* send command to mc*/
4077+ err = mc_send_command(mc_io, &cmd);
4078+ if (err)
4079+ return err;
4080+
4081+ /* retrieve response parameters */
4082+ DPDMUX_RSP_GET_IRQ_STATUS(cmd, *status);
4083+
4084+ return 0;
4085+}
4086+
4087+int dpdmux_clear_irq_status(struct fsl_mc_io *mc_io,
4088+ uint32_t cmd_flags,
4089+ uint16_t token,
4090+ uint8_t irq_index,
4091+ uint32_t status)
4092+{
4093+ struct mc_command cmd = { 0 };
4094+
4095+ /* prepare command */
4096+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_CLEAR_IRQ_STATUS,
4097+ cmd_flags,
4098+ token);
4099+ DPDMUX_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
4100+
4101+ /* send command to mc*/
4102+ return mc_send_command(mc_io, &cmd);
4103+}
4104+
4105+int dpdmux_get_attributes(struct fsl_mc_io *mc_io,
4106+ uint32_t cmd_flags,
4107+ uint16_t token,
4108+ struct dpdmux_attr *attr)
4109+{
4110+ struct mc_command cmd = { 0 };
4111+ int err;
4112+
4113+ /* prepare command */
4114+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_ATTR,
4115+ cmd_flags,
4116+ token);
4117+
4118+ /* send command to mc*/
4119+ err = mc_send_command(mc_io, &cmd);
4120+ if (err)
4121+ return err;
4122+
4123+ /* retrieve response parameters */
4124+ DPDMUX_RSP_GET_ATTR(cmd, attr);
4125+
4126+ return 0;
4127+}
4128+
4129+int dpdmux_ul_set_max_frame_length(struct fsl_mc_io *mc_io,
4130+ uint32_t cmd_flags,
4131+ uint16_t token,
4132+ uint16_t max_frame_length)
4133+{
4134+ struct mc_command cmd = { 0 };
4135+
4136+ /* prepare command */
4137+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_UL_SET_MAX_FRAME_LENGTH,
4138+ cmd_flags,
4139+ token);
4140+ DPDMUX_CMD_UL_SET_MAX_FRAME_LENGTH(cmd, max_frame_length);
4141+
4142+ /* send command to mc*/
4143+ return mc_send_command(mc_io, &cmd);
4144+}
4145+
4146+int dpdmux_ul_reset_counters(struct fsl_mc_io *mc_io,
4147+ uint32_t cmd_flags,
4148+ uint16_t token)
4149+{
4150+ struct mc_command cmd = { 0 };
4151+
4152+ /* prepare command */
4153+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_UL_RESET_COUNTERS,
4154+ cmd_flags,
4155+ token);
4156+
4157+ /* send command to mc*/
4158+ return mc_send_command(mc_io, &cmd);
4159+}
4160+
4161+int dpdmux_if_set_accepted_frames(struct fsl_mc_io *mc_io,
4162+ uint32_t cmd_flags,
4163+ uint16_t token,
4164+ uint16_t if_id,
4165+ const struct dpdmux_accepted_frames *cfg)
4166+{
4167+ struct mc_command cmd = { 0 };
4168+
4169+ /* prepare command */
4170+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_SET_ACCEPTED_FRAMES,
4171+ cmd_flags,
4172+ token);
4173+ DPDMUX_CMD_IF_SET_ACCEPTED_FRAMES(cmd, if_id, cfg);
4174+
4175+ /* send command to mc*/
4176+ return mc_send_command(mc_io, &cmd);
4177+}
4178+
4179+int dpdmux_if_get_attributes(struct fsl_mc_io *mc_io,
4180+ uint32_t cmd_flags,
4181+ uint16_t token,
4182+ uint16_t if_id,
4183+ struct dpdmux_if_attr *attr)
4184+{
4185+ struct mc_command cmd = { 0 };
4186+ int err;
4187+
4188+ /* prepare command */
4189+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_GET_ATTR,
4190+ cmd_flags,
4191+ token);
4192+ DPDMUX_CMD_IF_GET_ATTR(cmd, if_id);
4193+
4194+ /* send command to mc*/
4195+ err = mc_send_command(mc_io, &cmd);
4196+ if (err)
4197+ return err;
4198+
4199+ /* retrieve response parameters */
4200+ DPDMUX_RSP_IF_GET_ATTR(cmd, attr);
4201+
4202+ return 0;
4203+}
4204+
4205+int dpdmux_if_remove_l2_rule(struct fsl_mc_io *mc_io,
4206+ uint32_t cmd_flags,
4207+ uint16_t token,
4208+ uint16_t if_id,
4209+ const struct dpdmux_l2_rule *rule)
4210+{
4211+ struct mc_command cmd = { 0 };
4212+
4213+ /* prepare command */
4214+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_REMOVE_L2_RULE,
4215+ cmd_flags,
4216+ token);
4217+ DPDMUX_CMD_IF_REMOVE_L2_RULE(cmd, if_id, rule);
4218+
4219+ /* send command to mc*/
4220+ return mc_send_command(mc_io, &cmd);
4221+}
4222+
4223+int dpdmux_if_add_l2_rule(struct fsl_mc_io *mc_io,
4224+ uint32_t cmd_flags,
4225+ uint16_t token,
4226+ uint16_t if_id,
4227+ const struct dpdmux_l2_rule *rule)
4228+{
4229+ struct mc_command cmd = { 0 };
4230+
4231+ /* prepare command */
4232+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_ADD_L2_RULE,
4233+ cmd_flags,
4234+ token);
4235+ DPDMUX_CMD_IF_ADD_L2_RULE(cmd, if_id, rule);
4236+
4237+ /* send command to mc*/
4238+ return mc_send_command(mc_io, &cmd);
4239+}
4240+
4241+int dpdmux_if_get_counter(struct fsl_mc_io *mc_io,
4242+ uint32_t cmd_flags,
4243+ uint16_t token,
4244+ uint16_t if_id,
4245+ enum dpdmux_counter_type counter_type,
4246+ uint64_t *counter)
4247+{
4248+ struct mc_command cmd = { 0 };
4249+ int err;
4250+
4251+ /* prepare command */
4252+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_GET_COUNTER,
4253+ cmd_flags,
4254+ token);
4255+ DPDMUX_CMD_IF_GET_COUNTER(cmd, if_id, counter_type);
4256+
4257+ /* send command to mc*/
4258+ err = mc_send_command(mc_io, &cmd);
4259+ if (err)
4260+ return err;
4261+
4262+ /* retrieve response parameters */
4263+ DPDMUX_RSP_IF_GET_COUNTER(cmd, *counter);
4264+
4265+ return 0;
4266+}
4267+
4268+int dpdmux_if_set_link_cfg(struct fsl_mc_io *mc_io,
4269+ uint32_t cmd_flags,
4270+ uint16_t token,
4271+ uint16_t if_id,
4272+ struct dpdmux_link_cfg *cfg)
4273+{
4274+ struct mc_command cmd = { 0 };
4275+
4276+ /* prepare command */
4277+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_SET_LINK_CFG,
4278+ cmd_flags,
4279+ token);
4280+ DPDMUX_CMD_IF_SET_LINK_CFG(cmd, if_id, cfg);
4281+
4282+ /* send command to mc*/
4283+ return mc_send_command(mc_io, &cmd);
4284+}
4285+
4286+int dpdmux_if_get_link_state(struct fsl_mc_io *mc_io,
4287+ uint32_t cmd_flags,
4288+ uint16_t token,
4289+ uint16_t if_id,
4290+ struct dpdmux_link_state *state)
4291+{
4292+ struct mc_command cmd = { 0 };
4293+ int err;
4294+
4295+ /* prepare command */
4296+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_GET_LINK_STATE,
4297+ cmd_flags,
4298+ token);
4299+ DPDMUX_CMD_IF_GET_LINK_STATE(cmd, if_id);
4300+
4301+ /* send command to mc*/
4302+ err = mc_send_command(mc_io, &cmd);
4303+ if (err)
4304+ return err;
4305+
4306+ /* retrieve response parameters */
4307+ DPDMUX_RSP_IF_GET_LINK_STATE(cmd, state);
4308+
4309+ return 0;
4310+}
4311diff --git a/drivers/net/dpaa2/mc/dpio.c b/drivers/net/dpaa2/mc/dpio.c
4312new file mode 100644
4313index 0000000..f511e29
4314--- /dev/null
4315+++ b/drivers/net/dpaa2/mc/dpio.c
4316@@ -0,0 +1,468 @@
4317+/* Copyright 2013-2015 Freescale Semiconductor Inc.
4318+ *
4319+ * Redistribution and use in source and binary forms, with or without
4320+ * modification, are permitted provided that the following conditions are met:
4321+ * * Redistributions of source code must retain the above copyright
4322+ * notice, this list of conditions and the following disclaimer.
4323+ * * Redistributions in binary form must reproduce the above copyright
4324+ * notice, this list of conditions and the following disclaimer in the
4325+ * documentation and/or other materials provided with the distribution.
4326+ * * Neither the name of the above-listed copyright holders nor the
4327+ * names of any contributors may be used to endorse or promote products
4328+ * derived from this software without specific prior written permission.
4329+ *
4330+ *
4331+ * ALTERNATIVELY, this software may be distributed under the terms of the
4332+ * GNU General Public License ("GPL") as published by the Free Software
4333+ * Foundation, either version 2 of that License or (at your option) any
4334+ * later version.
4335+ *
4336+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
4337+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
4338+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4339+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
4340+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
4341+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
4342+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
4343+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
4344+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
4345+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
4346+ * POSSIBILITY OF SUCH DAMAGE.
4347+ */
4348+#include <fsl_mc_sys.h>
4349+#include <fsl_mc_cmd.h>
4350+#include <fsl_dpio.h>
4351+#include <fsl_dpio_cmd.h>
4352+
4353+int dpio_open(struct fsl_mc_io *mc_io,
4354+ uint32_t cmd_flags,
4355+ int dpio_id,
4356+ uint16_t *token)
4357+{
4358+ struct mc_command cmd = { 0 };
4359+ int err;
4360+
4361+ /* prepare command */
4362+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN,
4363+ cmd_flags,
4364+ 0);
4365+ DPIO_CMD_OPEN(cmd, dpio_id);
4366+
4367+ /* send command to mc*/
4368+ err = mc_send_command(mc_io, &cmd);
4369+ if (err)
4370+ return err;
4371+
4372+ /* retrieve response parameters */
4373+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
4374+
4375+ return 0;
4376+}
4377+
4378+int dpio_close(struct fsl_mc_io *mc_io,
4379+ uint32_t cmd_flags,
4380+ uint16_t token)
4381+{
4382+ struct mc_command cmd = { 0 };
4383+
4384+ /* prepare command */
4385+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE,
4386+ cmd_flags,
4387+ token);
4388+
4389+ /* send command to mc*/
4390+ return mc_send_command(mc_io, &cmd);
4391+}
4392+
4393+int dpio_create(struct fsl_mc_io *mc_io,
4394+ uint32_t cmd_flags,
4395+ const struct dpio_cfg *cfg,
4396+ uint16_t *token)
4397+{
4398+ struct mc_command cmd = { 0 };
4399+ int err;
4400+
4401+ /* prepare command */
4402+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_CREATE,
4403+ cmd_flags,
4404+ 0);
4405+ DPIO_CMD_CREATE(cmd, cfg);
4406+
4407+ /* send command to mc*/
4408+ err = mc_send_command(mc_io, &cmd);
4409+ if (err)
4410+ return err;
4411+
4412+ /* retrieve response parameters */
4413+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
4414+
4415+ return 0;
4416+}
4417+
4418+int dpio_destroy(struct fsl_mc_io *mc_io,
4419+ uint32_t cmd_flags,
4420+ uint16_t token)
4421+{
4422+ struct mc_command cmd = { 0 };
4423+
4424+ /* prepare command */
4425+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_DESTROY,
4426+ cmd_flags,
4427+ token);
4428+
4429+ /* send command to mc*/
4430+ return mc_send_command(mc_io, &cmd);
4431+}
4432+
4433+int dpio_enable(struct fsl_mc_io *mc_io,
4434+ uint32_t cmd_flags,
4435+ uint16_t token)
4436+{
4437+ struct mc_command cmd = { 0 };
4438+
4439+ /* prepare command */
4440+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE,
4441+ cmd_flags,
4442+ token);
4443+
4444+ /* send command to mc*/
4445+ return mc_send_command(mc_io, &cmd);
4446+}
4447+
4448+int dpio_disable(struct fsl_mc_io *mc_io,
4449+ uint32_t cmd_flags,
4450+ uint16_t token)
4451+{
4452+ struct mc_command cmd = { 0 };
4453+
4454+ /* prepare command */
4455+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE,
4456+ cmd_flags,
4457+ token);
4458+
4459+ /* send command to mc*/
4460+ return mc_send_command(mc_io, &cmd);
4461+}
4462+
4463+int dpio_is_enabled(struct fsl_mc_io *mc_io,
4464+ uint32_t cmd_flags,
4465+ uint16_t token,
4466+ int *en)
4467+{
4468+ struct mc_command cmd = { 0 };
4469+ int err;
4470+ /* prepare command */
4471+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_IS_ENABLED, cmd_flags,
4472+ token);
4473+
4474+ /* send command to mc*/
4475+ err = mc_send_command(mc_io, &cmd);
4476+ if (err)
4477+ return err;
4478+
4479+ /* retrieve response parameters */
4480+ DPIO_RSP_IS_ENABLED(cmd, *en);
4481+
4482+ return 0;
4483+}
4484+
4485+int dpio_reset(struct fsl_mc_io *mc_io,
4486+ uint32_t cmd_flags,
4487+ uint16_t token)
4488+{
4489+ struct mc_command cmd = { 0 };
4490+
4491+ /* prepare command */
4492+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_RESET,
4493+ cmd_flags,
4494+ token);
4495+
4496+ /* send command to mc*/
4497+ return mc_send_command(mc_io, &cmd);
4498+}
4499+
4500+int dpio_set_irq(struct fsl_mc_io *mc_io,
4501+ uint32_t cmd_flags,
4502+ uint16_t token,
4503+ uint8_t irq_index,
4504+ struct dpio_irq_cfg *irq_cfg)
4505+{
4506+ struct mc_command cmd = { 0 };
4507+
4508+ /* prepare command */
4509+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_SET_IRQ,
4510+ cmd_flags,
4511+ token);
4512+ DPIO_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
4513+
4514+ /* send command to mc*/
4515+ return mc_send_command(mc_io, &cmd);
4516+}
4517+
4518+int dpio_get_irq(struct fsl_mc_io *mc_io,
4519+ uint32_t cmd_flags,
4520+ uint16_t token,
4521+ uint8_t irq_index,
4522+ int *type,
4523+ struct dpio_irq_cfg *irq_cfg)
4524+{
4525+ struct mc_command cmd = { 0 };
4526+ int err;
4527+
4528+ /* prepare command */
4529+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_IRQ,
4530+ cmd_flags,
4531+ token);
4532+ DPIO_CMD_GET_IRQ(cmd, irq_index);
4533+
4534+ /* send command to mc*/
4535+ err = mc_send_command(mc_io, &cmd);
4536+ if (err)
4537+ return err;
4538+
4539+ /* retrieve response parameters */
4540+ DPIO_RSP_GET_IRQ(cmd, *type, irq_cfg);
4541+
4542+ return 0;
4543+}
4544+
4545+int dpio_set_irq_enable(struct fsl_mc_io *mc_io,
4546+ uint32_t cmd_flags,
4547+ uint16_t token,
4548+ uint8_t irq_index,
4549+ uint8_t en)
4550+{
4551+ struct mc_command cmd = { 0 };
4552+
4553+ /* prepare command */
4554+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_SET_IRQ_ENABLE,
4555+ cmd_flags,
4556+ token);
4557+ DPIO_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
4558+
4559+ /* send command to mc*/
4560+ return mc_send_command(mc_io, &cmd);
4561+}
4562+
4563+int dpio_get_irq_enable(struct fsl_mc_io *mc_io,
4564+ uint32_t cmd_flags,
4565+ uint16_t token,
4566+ uint8_t irq_index,
4567+ uint8_t *en)
4568+{
4569+ struct mc_command cmd = { 0 };
4570+ int err;
4571+
4572+ /* prepare command */
4573+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_IRQ_ENABLE,
4574+ cmd_flags,
4575+ token);
4576+ DPIO_CMD_GET_IRQ_ENABLE(cmd, irq_index);
4577+
4578+ /* send command to mc*/
4579+ err = mc_send_command(mc_io, &cmd);
4580+ if (err)
4581+ return err;
4582+
4583+ /* retrieve response parameters */
4584+ DPIO_RSP_GET_IRQ_ENABLE(cmd, *en);
4585+
4586+ return 0;
4587+}
4588+
4589+int dpio_set_irq_mask(struct fsl_mc_io *mc_io,
4590+ uint32_t cmd_flags,
4591+ uint16_t token,
4592+ uint8_t irq_index,
4593+ uint32_t mask)
4594+{
4595+ struct mc_command cmd = { 0 };
4596+
4597+ /* prepare command */
4598+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_SET_IRQ_MASK,
4599+ cmd_flags,
4600+ token);
4601+ DPIO_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
4602+
4603+ /* send command to mc*/
4604+ return mc_send_command(mc_io, &cmd);
4605+}
4606+
4607+int dpio_get_irq_mask(struct fsl_mc_io *mc_io,
4608+ uint32_t cmd_flags,
4609+ uint16_t token,
4610+ uint8_t irq_index,
4611+ uint32_t *mask)
4612+{
4613+ struct mc_command cmd = { 0 };
4614+ int err;
4615+
4616+ /* prepare command */
4617+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_IRQ_MASK,
4618+ cmd_flags,
4619+ token);
4620+ DPIO_CMD_GET_IRQ_MASK(cmd, irq_index);
4621+
4622+ /* send command to mc*/
4623+ err = mc_send_command(mc_io, &cmd);
4624+ if (err)
4625+ return err;
4626+
4627+ /* retrieve response parameters */
4628+ DPIO_RSP_GET_IRQ_MASK(cmd, *mask);
4629+
4630+ return 0;
4631+}
4632+
4633+int dpio_get_irq_status(struct fsl_mc_io *mc_io,
4634+ uint32_t cmd_flags,
4635+ uint16_t token,
4636+ uint8_t irq_index,
4637+ uint32_t *status)
4638+{
4639+ struct mc_command cmd = { 0 };
4640+ int err;
4641+
4642+ /* prepare command */
4643+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_IRQ_STATUS,
4644+ cmd_flags,
4645+ token);
4646+ DPIO_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
4647+
4648+ /* send command to mc*/
4649+ err = mc_send_command(mc_io, &cmd);
4650+ if (err)
4651+ return err;
4652+
4653+ /* retrieve response parameters */
4654+ DPIO_RSP_GET_IRQ_STATUS(cmd, *status);
4655+
4656+ return 0;
4657+}
4658+
4659+int dpio_clear_irq_status(struct fsl_mc_io *mc_io,
4660+ uint32_t cmd_flags,
4661+ uint16_t token,
4662+ uint8_t irq_index,
4663+ uint32_t status)
4664+{
4665+ struct mc_command cmd = { 0 };
4666+
4667+ /* prepare command */
4668+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLEAR_IRQ_STATUS,
4669+ cmd_flags,
4670+ token);
4671+ DPIO_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
4672+
4673+ /* send command to mc*/
4674+ return mc_send_command(mc_io, &cmd);
4675+}
4676+
4677+int dpio_get_attributes(struct fsl_mc_io *mc_io,
4678+ uint32_t cmd_flags,
4679+ uint16_t token,
4680+ struct dpio_attr *attr)
4681+{
4682+ struct mc_command cmd = { 0 };
4683+ int err;
4684+
4685+ /* prepare command */
4686+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_ATTR,
4687+ cmd_flags,
4688+ token);
4689+
4690+ /* send command to mc*/
4691+ err = mc_send_command(mc_io, &cmd);
4692+ if (err)
4693+ return err;
4694+
4695+ /* retrieve response parameters */
4696+ DPIO_RSP_GET_ATTR(cmd, attr);
4697+
4698+ return 0;
4699+}
4700+
4701+int dpio_set_stashing_destination(struct fsl_mc_io *mc_io,
4702+ uint32_t cmd_flags,
4703+ uint16_t token,
4704+ uint8_t sdest)
4705+{
4706+ struct mc_command cmd = { 0 };
4707+
4708+ /* prepare command */
4709+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_SET_STASHING_DEST,
4710+ cmd_flags,
4711+ token);
4712+ DPIO_CMD_SET_STASHING_DEST(cmd, sdest);
4713+
4714+ /* send command to mc*/
4715+ return mc_send_command(mc_io, &cmd);
4716+}
4717+
4718+int dpio_get_stashing_destination(struct fsl_mc_io *mc_io,
4719+ uint32_t cmd_flags,
4720+ uint16_t token,
4721+ uint8_t *sdest)
4722+{
4723+ struct mc_command cmd = { 0 };
4724+ int err;
4725+
4726+ /* prepare command */
4727+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_STASHING_DEST,
4728+ cmd_flags,
4729+ token);
4730+
4731+ /* send command to mc*/
4732+ err = mc_send_command(mc_io, &cmd);
4733+ if (err)
4734+ return err;
4735+
4736+ /* retrieve response parameters */
4737+ DPIO_RSP_GET_STASHING_DEST(cmd, *sdest);
4738+
4739+ return 0;
4740+}
4741+
4742+int dpio_add_static_dequeue_channel(struct fsl_mc_io *mc_io,
4743+ uint32_t cmd_flags,
4744+ uint16_t token,
4745+ int dpcon_id,
4746+ uint8_t *channel_index)
4747+{
4748+ struct mc_command cmd = { 0 };
4749+ int err;
4750+
4751+ /* prepare command */
4752+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_ADD_STATIC_DEQUEUE_CHANNEL,
4753+ cmd_flags,
4754+ token);
4755+ DPIO_CMD_ADD_STATIC_DEQUEUE_CHANNEL(cmd, dpcon_id);
4756+
4757+ /* send command to mc*/
4758+ err = mc_send_command(mc_io, &cmd);
4759+ if (err)
4760+ return err;
4761+
4762+ /* retrieve response parameters */
4763+ DPIO_RSP_ADD_STATIC_DEQUEUE_CHANNEL(cmd, *channel_index);
4764+
4765+ return 0;
4766+}
4767+
4768+int dpio_remove_static_dequeue_channel(struct fsl_mc_io *mc_io,
4769+ uint32_t cmd_flags,
4770+ uint16_t token,
4771+ int dpcon_id)
4772+{
4773+ struct mc_command cmd = { 0 };
4774+
4775+ /* prepare command */
4776+ cmd.header = mc_encode_cmd_header(
4777+ DPIO_CMDID_REMOVE_STATIC_DEQUEUE_CHANNEL,
4778+ cmd_flags,
4779+ token);
4780+ DPIO_CMD_REMOVE_STATIC_DEQUEUE_CHANNEL(cmd, dpcon_id);
4781+
4782+ /* send command to mc*/
4783+ return mc_send_command(mc_io, &cmd);
4784+}
4785diff --git a/drivers/net/dpaa2/mc/dpmac.c b/drivers/net/dpaa2/mc/dpmac.c
4786new file mode 100644
4787index 0000000..f31d949
4788--- /dev/null
4789+++ b/drivers/net/dpaa2/mc/dpmac.c
4790@@ -0,0 +1,422 @@
4791+/* Copyright 2013-2015 Freescale Semiconductor Inc.
4792+ *
4793+ * Redistribution and use in source and binary forms, with or without
4794+ * modification, are permitted provided that the following conditions are met:
4795+ * * Redistributions of source code must retain the above copyright
4796+ * notice, this list of conditions and the following disclaimer.
4797+ * * Redistributions in binary form must reproduce the above copyright
4798+ * notice, this list of conditions and the following disclaimer in the
4799+ * documentation and/or other materials provided with the distribution.
4800+ * * Neither the name of the above-listed copyright holders nor the
4801+ * names of any contributors may be used to endorse or promote products
4802+ * derived from this software without specific prior written permission.
4803+ *
4804+ *
4805+ * ALTERNATIVELY, this software may be distributed under the terms of the
4806+ * GNU General Public License ("GPL") as published by the Free Software
4807+ * Foundation, either version 2 of that License or (at your option) any
4808+ * later version.
4809+ *
4810+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
4811+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
4812+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4813+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
4814+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
4815+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
4816+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
4817+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
4818+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
4819+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
4820+ * POSSIBILITY OF SUCH DAMAGE.
4821+ */
4822+#include <fsl_mc_sys.h>
4823+#include <fsl_mc_cmd.h>
4824+#include <fsl_dpmac.h>
4825+#include <fsl_dpmac_cmd.h>
4826+
4827+int dpmac_open(struct fsl_mc_io *mc_io,
4828+ uint32_t cmd_flags,
4829+ int dpmac_id,
4830+ uint16_t *token)
4831+{
4832+ struct mc_command cmd = { 0 };
4833+ int err;
4834+
4835+ /* prepare command */
4836+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN,
4837+ cmd_flags,
4838+ 0);
4839+ DPMAC_CMD_OPEN(cmd, dpmac_id);
4840+
4841+ /* send command to mc*/
4842+ err = mc_send_command(mc_io, &cmd);
4843+ if (err)
4844+ return err;
4845+
4846+ /* retrieve response parameters */
4847+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
4848+
4849+ return err;
4850+}
4851+
4852+int dpmac_close(struct fsl_mc_io *mc_io,
4853+ uint32_t cmd_flags,
4854+ uint16_t token)
4855+{
4856+ struct mc_command cmd = { 0 };
4857+
4858+ /* prepare command */
4859+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags,
4860+ token);
4861+
4862+ /* send command to mc*/
4863+ return mc_send_command(mc_io, &cmd);
4864+}
4865+
4866+int dpmac_create(struct fsl_mc_io *mc_io,
4867+ uint32_t cmd_flags,
4868+ const struct dpmac_cfg *cfg,
4869+ uint16_t *token)
4870+{
4871+ struct mc_command cmd = { 0 };
4872+ int err;
4873+
4874+ /* prepare command */
4875+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE,
4876+ cmd_flags,
4877+ 0);
4878+ DPMAC_CMD_CREATE(cmd, cfg);
4879+
4880+ /* send command to mc*/
4881+ err = mc_send_command(mc_io, &cmd);
4882+ if (err)
4883+ return err;
4884+
4885+ /* retrieve response parameters */
4886+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
4887+
4888+ return 0;
4889+}
4890+
4891+int dpmac_destroy(struct fsl_mc_io *mc_io,
4892+ uint32_t cmd_flags,
4893+ uint16_t token)
4894+{
4895+ struct mc_command cmd = { 0 };
4896+
4897+ /* prepare command */
4898+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY,
4899+ cmd_flags,
4900+ token);
4901+
4902+ /* send command to mc*/
4903+ return mc_send_command(mc_io, &cmd);
4904+}
4905+
4906+int dpmac_set_irq(struct fsl_mc_io *mc_io,
4907+ uint32_t cmd_flags,
4908+ uint16_t token,
4909+ uint8_t irq_index,
4910+ struct dpmac_irq_cfg *irq_cfg)
4911+{
4912+ struct mc_command cmd = { 0 };
4913+
4914+ /* prepare command */
4915+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_IRQ,
4916+ cmd_flags,
4917+ token);
4918+ DPMAC_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
4919+
4920+ /* send command to mc*/
4921+ return mc_send_command(mc_io, &cmd);
4922+}
4923+
4924+int dpmac_get_irq(struct fsl_mc_io *mc_io,
4925+ uint32_t cmd_flags,
4926+ uint16_t token,
4927+ uint8_t irq_index,
4928+ int *type,
4929+ struct dpmac_irq_cfg *irq_cfg)
4930+{
4931+ struct mc_command cmd = { 0 };
4932+ int err;
4933+
4934+ /* prepare command */
4935+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ,
4936+ cmd_flags,
4937+ token);
4938+ DPMAC_CMD_GET_IRQ(cmd, irq_index);
4939+
4940+ /* send command to mc*/
4941+ err = mc_send_command(mc_io, &cmd);
4942+ if (err)
4943+ return err;
4944+
4945+ /* retrieve response parameters */
4946+ DPMAC_RSP_GET_IRQ(cmd, *type, irq_cfg);
4947+
4948+ return 0;
4949+}
4950+
4951+int dpmac_set_irq_enable(struct fsl_mc_io *mc_io,
4952+ uint32_t cmd_flags,
4953+ uint16_t token,
4954+ uint8_t irq_index,
4955+ uint8_t en)
4956+{
4957+ struct mc_command cmd = { 0 };
4958+
4959+ /* prepare command */
4960+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_IRQ_ENABLE,
4961+ cmd_flags,
4962+ token);
4963+ DPMAC_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
4964+
4965+ /* send command to mc*/
4966+ return mc_send_command(mc_io, &cmd);
4967+}
4968+
4969+int dpmac_get_irq_enable(struct fsl_mc_io *mc_io,
4970+ uint32_t cmd_flags,
4971+ uint16_t token,
4972+ uint8_t irq_index,
4973+ uint8_t *en)
4974+{
4975+ struct mc_command cmd = { 0 };
4976+ int err;
4977+
4978+ /* prepare command */
4979+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ_ENABLE,
4980+ cmd_flags,
4981+ token);
4982+ DPMAC_CMD_GET_IRQ_ENABLE(cmd, irq_index);
4983+
4984+ /* send command to mc*/
4985+ err = mc_send_command(mc_io, &cmd);
4986+ if (err)
4987+ return err;
4988+
4989+ /* retrieve response parameters */
4990+ DPMAC_RSP_GET_IRQ_ENABLE(cmd, *en);
4991+
4992+ return 0;
4993+}
4994+
4995+int dpmac_set_irq_mask(struct fsl_mc_io *mc_io,
4996+ uint32_t cmd_flags,
4997+ uint16_t token,
4998+ uint8_t irq_index,
4999+ uint32_t mask)
5000+{
5001+ struct mc_command cmd = { 0 };
5002+
5003+ /* prepare command */
5004+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_IRQ_MASK,
5005+ cmd_flags,
5006+ token);
5007+ DPMAC_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
5008+
5009+ /* send command to mc*/
5010+ return mc_send_command(mc_io, &cmd);
5011+}
5012+
5013+int dpmac_get_irq_mask(struct fsl_mc_io *mc_io,
5014+ uint32_t cmd_flags,
5015+ uint16_t token,
5016+ uint8_t irq_index,
5017+ uint32_t *mask)
5018+{
5019+ struct mc_command cmd = { 0 };
5020+ int err;
5021+
5022+ /* prepare command */
5023+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ_MASK,
5024+ cmd_flags,
5025+ token);
5026+ DPMAC_CMD_GET_IRQ_MASK(cmd, irq_index);
5027+
5028+ /* send command to mc*/
5029+ err = mc_send_command(mc_io, &cmd);
5030+ if (err)
5031+ return err;
5032+
5033+ /* retrieve response parameters */
5034+ DPMAC_RSP_GET_IRQ_MASK(cmd, *mask);
5035+
5036+ return 0;
5037+}
5038+
5039+int dpmac_get_irq_status(struct fsl_mc_io *mc_io,
5040+ uint32_t cmd_flags,
5041+ uint16_t token,
5042+ uint8_t irq_index,
5043+ uint32_t *status)
5044+{
5045+ struct mc_command cmd = { 0 };
5046+ int err;
5047+
5048+ /* prepare command */
5049+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ_STATUS,
5050+ cmd_flags,
5051+ token);
5052+ DPMAC_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
5053+
5054+ /* send command to mc*/
5055+ err = mc_send_command(mc_io, &cmd);
5056+ if (err)
5057+ return err;
5058+
5059+ /* retrieve response parameters */
5060+ DPMAC_RSP_GET_IRQ_STATUS(cmd, *status);
5061+
5062+ return 0;
5063+}
5064+
5065+int dpmac_clear_irq_status(struct fsl_mc_io *mc_io,
5066+ uint32_t cmd_flags,
5067+ uint16_t token,
5068+ uint8_t irq_index,
5069+ uint32_t status)
5070+{
5071+ struct mc_command cmd = { 0 };
5072+
5073+ /* prepare command */
5074+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLEAR_IRQ_STATUS,
5075+ cmd_flags,
5076+ token);
5077+ DPMAC_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
5078+
5079+ /* send command to mc*/
5080+ return mc_send_command(mc_io, &cmd);
5081+}
5082+
5083+int dpmac_get_attributes(struct fsl_mc_io *mc_io,
5084+ uint32_t cmd_flags,
5085+ uint16_t token,
5086+ struct dpmac_attr *attr)
5087+{
5088+ struct mc_command cmd = { 0 };
5089+ int err;
5090+
5091+ /* prepare command */
5092+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR,
5093+ cmd_flags,
5094+ token);
5095+
5096+ /* send command to mc*/
5097+ err = mc_send_command(mc_io, &cmd);
5098+ if (err)
5099+ return err;
5100+
5101+ /* retrieve response parameters */
5102+ DPMAC_RSP_GET_ATTRIBUTES(cmd, attr);
5103+
5104+ return 0;
5105+}
5106+
5107+int dpmac_mdio_read(struct fsl_mc_io *mc_io,
5108+ uint32_t cmd_flags,
5109+ uint16_t token,
5110+ struct dpmac_mdio_cfg *cfg)
5111+{
5112+ struct mc_command cmd = { 0 };
5113+ int err;
5114+
5115+ /* prepare command */
5116+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_READ,
5117+ cmd_flags,
5118+ token);
5119+ DPMAC_CMD_MDIO_READ(cmd, cfg);
5120+
5121+ /* send command to mc*/
5122+ err = mc_send_command(mc_io, &cmd);
5123+ if (err)
5124+ return err;
5125+
5126+ /* retrieve response parameters */
5127+ DPMAC_RSP_MDIO_READ(cmd, cfg->data);
5128+
5129+ return 0;
5130+}
5131+
5132+int dpmac_mdio_write(struct fsl_mc_io *mc_io,
5133+ uint32_t cmd_flags,
5134+ uint16_t token,
5135+ struct dpmac_mdio_cfg *cfg)
5136+{
5137+ struct mc_command cmd = { 0 };
5138+
5139+ /* prepare command */
5140+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_WRITE,
5141+ cmd_flags,
5142+ token);
5143+ DPMAC_CMD_MDIO_WRITE(cmd, cfg);
5144+
5145+ /* send command to mc*/
5146+ return mc_send_command(mc_io, &cmd);
5147+}
5148+
5149+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
5150+ uint32_t cmd_flags,
5151+ uint16_t token,
5152+ struct dpmac_link_cfg *cfg)
5153+{
5154+ struct mc_command cmd = { 0 };
5155+ int err = 0;
5156+
5157+ /* prepare command */
5158+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG,
5159+ cmd_flags,
5160+ token);
5161+
5162+ /* send command to mc*/
5163+ err = mc_send_command(mc_io, &cmd);
5164+ if (err)
5165+ return err;
5166+
5167+ DPMAC_RSP_GET_LINK_CFG(cmd, cfg);
5168+
5169+ return 0;
5170+}
5171+
5172+int dpmac_set_link_state(struct fsl_mc_io *mc_io,
5173+ uint32_t cmd_flags,
5174+ uint16_t token,
5175+ struct dpmac_link_state *link_state)
5176+{
5177+ struct mc_command cmd = { 0 };
5178+
5179+ /* prepare command */
5180+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE,
5181+ cmd_flags,
5182+ token);
5183+ DPMAC_CMD_SET_LINK_STATE(cmd, link_state);
5184+
5185+ /* send command to mc*/
5186+ return mc_send_command(mc_io, &cmd);
5187+}
5188+
5189+int dpmac_get_counter(struct fsl_mc_io *mc_io,
5190+ uint32_t cmd_flags,
5191+ uint16_t token,
5192+ enum dpmac_counter type,
5193+ uint64_t *counter)
5194+{
5195+ struct mc_command cmd = { 0 };
5196+ int err = 0;
5197+
5198+ /* prepare command */
5199+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER,
5200+ cmd_flags,
5201+ token);
5202+ DPMAC_CMD_GET_COUNTER(cmd, type);
5203+
5204+ /* send command to mc*/
5205+ err = mc_send_command(mc_io, &cmd);
5206+ if (err)
5207+ return err;
5208+
5209+ DPMAC_RSP_GET_COUNTER(cmd, *counter);
5210+
5211+ return 0;
5212+}
5213diff --git a/drivers/net/dpaa2/mc/dpmcp.c b/drivers/net/dpaa2/mc/dpmcp.c
5214new file mode 100644
5215index 0000000..dfd84b8
5216--- /dev/null
5217+++ b/drivers/net/dpaa2/mc/dpmcp.c
5218@@ -0,0 +1,312 @@
5219+/* Copyright 2013-2015 Freescale Semiconductor Inc.
5220+ *
5221+ * Redistribution and use in source and binary forms, with or without
5222+ * modification, are permitted provided that the following conditions are met:
5223+ * * Redistributions of source code must retain the above copyright
5224+ * notice, this list of conditions and the following disclaimer.
5225+ * * Redistributions in binary form must reproduce the above copyright
5226+ * notice, this list of conditions and the following disclaimer in the
5227+ * documentation and/or other materials provided with the distribution.
5228+ * * Neither the name of the above-listed copyright holders nor the
5229+ * names of any contributors may be used to endorse or promote products
5230+ * derived from this software without specific prior written permission.
5231+ *
5232+ *
5233+ * ALTERNATIVELY, this software may be distributed under the terms of the
5234+ * GNU General Public License ("GPL") as published by the Free Software
5235+ * Foundation, either version 2 of that License or (at your option) any
5236+ * later version.
5237+ *
5238+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
5239+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
5240+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
5241+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
5242+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
5243+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
5244+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
5245+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
5246+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
5247+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
5248+ * POSSIBILITY OF SUCH DAMAGE.
5249+ */
5250+#include <fsl_mc_sys.h>
5251+#include <fsl_mc_cmd.h>
5252+#include <fsl_dpmcp.h>
5253+#include <fsl_dpmcp_cmd.h>
5254+
5255+int dpmcp_open(struct fsl_mc_io *mc_io,
5256+ uint32_t cmd_flags,
5257+ int dpmcp_id,
5258+ uint16_t *token)
5259+{
5260+ struct mc_command cmd = { 0 };
5261+ int err;
5262+
5263+ /* prepare command */
5264+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_OPEN,
5265+ cmd_flags,
5266+ 0);
5267+ DPMCP_CMD_OPEN(cmd, dpmcp_id);
5268+
5269+ /* send command to mc*/
5270+ err = mc_send_command(mc_io, &cmd);
5271+ if (err)
5272+ return err;
5273+
5274+ /* retrieve response parameters */
5275+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
5276+
5277+ return err;
5278+}
5279+
5280+int dpmcp_close(struct fsl_mc_io *mc_io,
5281+ uint32_t cmd_flags,
5282+ uint16_t token)
5283+{
5284+ struct mc_command cmd = { 0 };
5285+
5286+ /* prepare command */
5287+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_CLOSE, cmd_flags,
5288+ token);
5289+
5290+ /* send command to mc*/
5291+ return mc_send_command(mc_io, &cmd);
5292+}
5293+
5294+int dpmcp_create(struct fsl_mc_io *mc_io,
5295+ uint32_t cmd_flags,
5296+ const struct dpmcp_cfg *cfg,
5297+ uint16_t *token)
5298+{
5299+ struct mc_command cmd = { 0 };
5300+ int err;
5301+
5302+ /* prepare command */
5303+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_CREATE,
5304+ cmd_flags,
5305+ 0);
5306+ DPMCP_CMD_CREATE(cmd, cfg);
5307+
5308+ /* send command to mc*/
5309+ err = mc_send_command(mc_io, &cmd);
5310+ if (err)
5311+ return err;
5312+
5313+ /* retrieve response parameters */
5314+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
5315+
5316+ return 0;
5317+}
5318+
5319+int dpmcp_destroy(struct fsl_mc_io *mc_io,
5320+ uint32_t cmd_flags,
5321+ uint16_t token)
5322+{
5323+ struct mc_command cmd = { 0 };
5324+
5325+ /* prepare command */
5326+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_DESTROY,
5327+ cmd_flags,
5328+ token);
5329+
5330+ /* send command to mc*/
5331+ return mc_send_command(mc_io, &cmd);
5332+}
5333+
5334+int dpmcp_reset(struct fsl_mc_io *mc_io,
5335+ uint32_t cmd_flags,
5336+ uint16_t token)
5337+{
5338+ struct mc_command cmd = { 0 };
5339+
5340+ /* prepare command */
5341+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_RESET,
5342+ cmd_flags,
5343+ token);
5344+
5345+ /* send command to mc*/
5346+ return mc_send_command(mc_io, &cmd);
5347+}
5348+
5349+int dpmcp_set_irq(struct fsl_mc_io *mc_io,
5350+ uint32_t cmd_flags,
5351+ uint16_t token,
5352+ uint8_t irq_index,
5353+ struct dpmcp_irq_cfg *irq_cfg)
5354+{
5355+ struct mc_command cmd = { 0 };
5356+
5357+ /* prepare command */
5358+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ,
5359+ cmd_flags,
5360+ token);
5361+ DPMCP_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
5362+
5363+ /* send command to mc*/
5364+ return mc_send_command(mc_io, &cmd);
5365+}
5366+
5367+int dpmcp_get_irq(struct fsl_mc_io *mc_io,
5368+ uint32_t cmd_flags,
5369+ uint16_t token,
5370+ uint8_t irq_index,
5371+ int *type,
5372+ struct dpmcp_irq_cfg *irq_cfg)
5373+{
5374+ struct mc_command cmd = { 0 };
5375+ int err;
5376+
5377+ /* prepare command */
5378+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ,
5379+ cmd_flags,
5380+ token);
5381+ DPMCP_CMD_GET_IRQ(cmd, irq_index);
5382+
5383+ /* send command to mc*/
5384+ err = mc_send_command(mc_io, &cmd);
5385+ if (err)
5386+ return err;
5387+
5388+ /* retrieve response parameters */
5389+ DPMCP_RSP_GET_IRQ(cmd, *type, irq_cfg);
5390+
5391+ return 0;
5392+}
5393+
5394+int dpmcp_set_irq_enable(struct fsl_mc_io *mc_io,
5395+ uint32_t cmd_flags,
5396+ uint16_t token,
5397+ uint8_t irq_index,
5398+ uint8_t en)
5399+{
5400+ struct mc_command cmd = { 0 };
5401+
5402+ /* prepare command */
5403+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ_ENABLE,
5404+ cmd_flags,
5405+ token);
5406+ DPMCP_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
5407+
5408+ /* send command to mc*/
5409+ return mc_send_command(mc_io, &cmd);
5410+}
5411+
5412+int dpmcp_get_irq_enable(struct fsl_mc_io *mc_io,
5413+ uint32_t cmd_flags,
5414+ uint16_t token,
5415+ uint8_t irq_index,
5416+ uint8_t *en)
5417+{
5418+ struct mc_command cmd = { 0 };
5419+ int err;
5420+
5421+ /* prepare command */
5422+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_ENABLE,
5423+ cmd_flags,
5424+ token);
5425+ DPMCP_CMD_GET_IRQ_ENABLE(cmd, irq_index);
5426+
5427+ /* send command to mc*/
5428+ err = mc_send_command(mc_io, &cmd);
5429+ if (err)
5430+ return err;
5431+
5432+ /* retrieve response parameters */
5433+ DPMCP_RSP_GET_IRQ_ENABLE(cmd, *en);
5434+
5435+ return 0;
5436+}
5437+
5438+int dpmcp_set_irq_mask(struct fsl_mc_io *mc_io,
5439+ uint32_t cmd_flags,
5440+ uint16_t token,
5441+ uint8_t irq_index,
5442+ uint32_t mask)
5443+{
5444+ struct mc_command cmd = { 0 };
5445+
5446+ /* prepare command */
5447+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ_MASK,
5448+ cmd_flags,
5449+ token);
5450+ DPMCP_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
5451+
5452+ /* send command to mc*/
5453+ return mc_send_command(mc_io, &cmd);
5454+}
5455+
5456+int dpmcp_get_irq_mask(struct fsl_mc_io *mc_io,
5457+ uint32_t cmd_flags,
5458+ uint16_t token,
5459+ uint8_t irq_index,
5460+ uint32_t *mask)
5461+{
5462+ struct mc_command cmd = { 0 };
5463+ int err;
5464+
5465+ /* prepare command */
5466+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_MASK,
5467+ cmd_flags,
5468+ token);
5469+ DPMCP_CMD_GET_IRQ_MASK(cmd, irq_index);
5470+
5471+ /* send command to mc*/
5472+ err = mc_send_command(mc_io, &cmd);
5473+ if (err)
5474+ return err;
5475+
5476+ /* retrieve response parameters */
5477+ DPMCP_RSP_GET_IRQ_MASK(cmd, *mask);
5478+
5479+ return 0;
5480+}
5481+
5482+int dpmcp_get_irq_status(struct fsl_mc_io *mc_io,
5483+ uint32_t cmd_flags,
5484+ uint16_t token,
5485+ uint8_t irq_index,
5486+ uint32_t *status)
5487+{
5488+ struct mc_command cmd = { 0 };
5489+ int err;
5490+
5491+ /* prepare command */
5492+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_STATUS,
5493+ cmd_flags,
5494+ token);
5495+ DPMCP_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
5496+
5497+ /* send command to mc*/
5498+ err = mc_send_command(mc_io, &cmd);
5499+ if (err)
5500+ return err;
5501+
5502+ /* retrieve response parameters */
5503+ DPMCP_RSP_GET_IRQ_STATUS(cmd, *status);
5504+
5505+ return 0;
5506+}
5507+
5508+int dpmcp_get_attributes(struct fsl_mc_io *mc_io,
5509+ uint32_t cmd_flags,
5510+ uint16_t token,
5511+ struct dpmcp_attr *attr)
5512+{
5513+ struct mc_command cmd = { 0 };
5514+ int err;
5515+
5516+ /* prepare command */
5517+ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_ATTR,
5518+ cmd_flags,
5519+ token);
5520+
5521+ /* send command to mc*/
5522+ err = mc_send_command(mc_io, &cmd);
5523+ if (err)
5524+ return err;
5525+
5526+ /* retrieve response parameters */
5527+ DPMCP_RSP_GET_ATTRIBUTES(cmd, attr);
5528+
5529+ return 0;
5530+}
5531diff --git a/drivers/net/dpaa2/mc/dpmng.c b/drivers/net/dpaa2/mc/dpmng.c
5532new file mode 100644
5533index 0000000..cac5ba5
5534--- /dev/null
5535+++ b/drivers/net/dpaa2/mc/dpmng.c
5536@@ -0,0 +1,58 @@
5537+/* Copyright 2013-2015 Freescale Semiconductor Inc.
5538+ *
5539+ * Redistribution and use in source and binary forms, with or without
5540+ * modification, are permitted provided that the following conditions are met:
5541+ * * Redistributions of source code must retain the above copyright
5542+ * notice, this list of conditions and the following disclaimer.
5543+ * * Redistributions in binary form must reproduce the above copyright
5544+ * notice, this list of conditions and the following disclaimer in the
5545+ * documentation and/or other materials provided with the distribution.
5546+ * * Neither the name of the above-listed copyright holders nor the
5547+ * names of any contributors may be used to endorse or promote products
5548+ * derived from this software without specific prior written permission.
5549+ *
5550+ *
5551+ * ALTERNATIVELY, this software may be distributed under the terms of the
5552+ * GNU General Public License ("GPL") as published by the Free Software
5553+ * Foundation, either version 2 of that License or (at your option) any
5554+ * later version.
5555+ *
5556+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
5557+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
5558+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
5559+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
5560+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
5561+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
5562+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
5563+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
5564+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
5565+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
5566+ * POSSIBILITY OF SUCH DAMAGE.
5567+ */
5568+#include <fsl_mc_sys.h>
5569+#include <fsl_mc_cmd.h>
5570+#include <fsl_dpmng.h>
5571+#include <fsl_dpmng_cmd.h>
5572+
5573+int mc_get_version(struct fsl_mc_io *mc_io,
5574+ uint32_t cmd_flags,
5575+ struct mc_version *mc_ver_info)
5576+{
5577+ struct mc_command cmd = { 0 };
5578+ int err;
5579+
5580+ /* prepare command */
5581+ cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION,
5582+ cmd_flags,
5583+ 0);
5584+
5585+ /* send command to mc*/
5586+ err = mc_send_command(mc_io, &cmd);
5587+ if (err)
5588+ return err;
5589+
5590+ /* retrieve response parameters */
5591+ DPMNG_RSP_GET_VERSION(cmd, mc_ver_info);
5592+
5593+ return 0;
5594+}
5595diff --git a/drivers/net/dpaa2/mc/dpni.c b/drivers/net/dpaa2/mc/dpni.c
5596new file mode 100644
5597index 0000000..cdd2f37
5598--- /dev/null
5599+++ b/drivers/net/dpaa2/mc/dpni.c
5600@@ -0,0 +1,1907 @@
5601+/* Copyright 2013-2015 Freescale Semiconductor Inc.
5602+ *
5603+ * Redistribution and use in source and binary forms, with or without
5604+ * modification, are permitted provided that the following conditions are met:
5605+ * * Redistributions of source code must retain the above copyright
5606+ * notice, this list of conditions and the following disclaimer.
5607+ * * Redistributions in binary form must reproduce the above copyright
5608+ * notice, this list of conditions and the following disclaimer in the
5609+ * documentation and/or other materials provided with the distribution.
5610+ * * Neither the name of the above-listed copyright holders nor the
5611+ * names of any contributors may be used to endorse or promote products
5612+ * derived from this software without specific prior written permission.
5613+ *
5614+ *
5615+ * ALTERNATIVELY, this software may be distributed under the terms of the
5616+ * GNU General Public License ("GPL") as published by the Free Software
5617+ * Foundation, either version 2 of that License or (at your option) any
5618+ * later version.
5619+ *
5620+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
5621+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
5622+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
5623+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
5624+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
5625+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
5626+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
5627+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
5628+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
5629+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
5630+ * POSSIBILITY OF SUCH DAMAGE.
5631+ */
5632+#include <fsl_mc_sys.h>
5633+#include <fsl_mc_cmd.h>
5634+#include <fsl_dpni.h>
5635+#include <fsl_dpni_cmd.h>
5636+
5637+int dpni_prepare_key_cfg(const struct dpkg_profile_cfg *cfg,
5638+ uint8_t *key_cfg_buf)
5639+{
5640+ int i, j;
5641+ int offset = 0;
5642+ int param = 1;
5643+ uint64_t *params = (uint64_t *)key_cfg_buf;
5644+
5645+ if (!key_cfg_buf || !cfg)
5646+ return -EINVAL;
5647+
5648+ params[0] |= mc_enc(0, 8, cfg->num_extracts);
5649+ params[0] = cpu_to_le64(params[0]);
5650+
5651+ if (cfg->num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS)
5652+ return -EINVAL;
5653+
5654+ for (i = 0; i < cfg->num_extracts; i++) {
5655+ switch (cfg->extracts[i].type) {
5656+ case DPKG_EXTRACT_FROM_HDR:
5657+ params[param] |= mc_enc(0, 8,
5658+ cfg->extracts[i].extract.from_hdr.prot);
5659+ params[param] |= mc_enc(8, 4,
5660+ cfg->extracts[i].extract.from_hdr.type);
5661+ params[param] |= mc_enc(16, 8,
5662+ cfg->extracts[i].extract.from_hdr.size);
5663+ params[param] |= mc_enc(24, 8,
5664+ cfg->extracts[i].extract.
5665+ from_hdr.offset);
5666+ params[param] |= mc_enc(32, 32,
5667+ cfg->extracts[i].extract.
5668+ from_hdr.field);
5669+ params[param] = cpu_to_le64(params[param]);
5670+ param++;
5671+ params[param] |= mc_enc(0, 8,
5672+ cfg->extracts[i].extract.
5673+ from_hdr.hdr_index);
5674+ break;
5675+ case DPKG_EXTRACT_FROM_DATA:
5676+ params[param] |= mc_enc(16, 8,
5677+ cfg->extracts[i].extract.
5678+ from_data.size);
5679+ params[param] |= mc_enc(24, 8,
5680+ cfg->extracts[i].extract.
5681+ from_data.offset);
5682+ params[param] = cpu_to_le64(params[param]);
5683+ param++;
5684+ break;
5685+ case DPKG_EXTRACT_FROM_PARSE:
5686+ params[param] |= mc_enc(16, 8,
5687+ cfg->extracts[i].extract.
5688+ from_parse.size);
5689+ params[param] |= mc_enc(24, 8,
5690+ cfg->extracts[i].extract.
5691+ from_parse.offset);
5692+ params[param] = cpu_to_le64(params[param]);
5693+ param++;
5694+ break;
5695+ default:
5696+ return -EINVAL;
5697+ }
5698+ params[param] |= mc_enc(
5699+ 24, 8, cfg->extracts[i].num_of_byte_masks);
5700+ params[param] |= mc_enc(32, 4, cfg->extracts[i].type);
5701+ params[param] = cpu_to_le64(params[param]);
5702+ param++;
5703+ for (offset = 0, j = 0;
5704+ j < DPKG_NUM_OF_MASKS;
5705+ offset += 16, j++) {
5706+ params[param] |= mc_enc(
5707+ (offset), 8, cfg->extracts[i].masks[j].mask);
5708+ params[param] |= mc_enc(
5709+ (offset + 8), 8,
5710+ cfg->extracts[i].masks[j].offset);
5711+ }
5712+ params[param] = cpu_to_le64(params[param]);
5713+ param++;
5714+ }
5715+ return 0;
5716+}
5717+
5718+int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg,
5719+ uint8_t *ext_cfg_buf)
5720+{
5721+ uint64_t *ext_params = (uint64_t *)ext_cfg_buf;
5722+
5723+ DPNI_PREP_EXTENDED_CFG(ext_params, cfg);
5724+
5725+ return 0;
5726+}
5727+
5728+int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg,
5729+ const uint8_t *ext_cfg_buf)
5730+{
5731+ const uint64_t *ext_params = (const uint64_t *)ext_cfg_buf;
5732+
5733+ DPNI_EXT_EXTENDED_CFG(ext_params, cfg);
5734+
5735+ return 0;
5736+}
5737+
5738+int dpni_open(struct fsl_mc_io *mc_io,
5739+ uint32_t cmd_flags,
5740+ int dpni_id,
5741+ uint16_t *token)
5742+{
5743+ struct mc_command cmd = { 0 };
5744+ int err;
5745+
5746+ /* prepare command */
5747+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_OPEN,
5748+ cmd_flags,
5749+ 0);
5750+ DPNI_CMD_OPEN(cmd, dpni_id);
5751+
5752+ /* send command to mc*/
5753+ err = mc_send_command(mc_io, &cmd);
5754+ if (err)
5755+ return err;
5756+
5757+ /* retrieve response parameters */
5758+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
5759+
5760+ return 0;
5761+}
5762+
5763+int dpni_close(struct fsl_mc_io *mc_io,
5764+ uint32_t cmd_flags,
5765+ uint16_t token)
5766+{
5767+ struct mc_command cmd = { 0 };
5768+
5769+ /* prepare command */
5770+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLOSE,
5771+ cmd_flags,
5772+ token);
5773+
5774+ /* send command to mc*/
5775+ return mc_send_command(mc_io, &cmd);
5776+}
5777+
5778+int dpni_create(struct fsl_mc_io *mc_io,
5779+ uint32_t cmd_flags,
5780+ const struct dpni_cfg *cfg,
5781+ uint16_t *token)
5782+{
5783+ struct mc_command cmd = { 0 };
5784+ int err;
5785+
5786+ /* prepare command */
5787+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CREATE,
5788+ cmd_flags,
5789+ 0);
5790+ DPNI_CMD_CREATE(cmd, cfg);
5791+
5792+ /* send command to mc*/
5793+ err = mc_send_command(mc_io, &cmd);
5794+ if (err)
5795+ return err;
5796+
5797+ /* retrieve response parameters */
5798+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
5799+
5800+ return 0;
5801+}
5802+
5803+int dpni_destroy(struct fsl_mc_io *mc_io,
5804+ uint32_t cmd_flags,
5805+ uint16_t token)
5806+{
5807+ struct mc_command cmd = { 0 };
5808+
5809+ /* prepare command */
5810+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_DESTROY,
5811+ cmd_flags,
5812+ token);
5813+
5814+ /* send command to mc*/
5815+ return mc_send_command(mc_io, &cmd);
5816+}
5817+
5818+int dpni_set_pools(struct fsl_mc_io *mc_io,
5819+ uint32_t cmd_flags,
5820+ uint16_t token,
5821+ const struct dpni_pools_cfg *cfg)
5822+{
5823+ struct mc_command cmd = { 0 };
5824+
5825+ /* prepare command */
5826+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_POOLS,
5827+ cmd_flags,
5828+ token);
5829+ DPNI_CMD_SET_POOLS(cmd, cfg);
5830+
5831+ /* send command to mc*/
5832+ return mc_send_command(mc_io, &cmd);
5833+}
5834+
5835+int dpni_enable(struct fsl_mc_io *mc_io,
5836+ uint32_t cmd_flags,
5837+ uint16_t token)
5838+{
5839+ struct mc_command cmd = { 0 };
5840+
5841+ /* prepare command */
5842+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ENABLE,
5843+ cmd_flags,
5844+ token);
5845+
5846+ /* send command to mc*/
5847+ return mc_send_command(mc_io, &cmd);
5848+}
5849+
5850+int dpni_disable(struct fsl_mc_io *mc_io,
5851+ uint32_t cmd_flags,
5852+ uint16_t token)
5853+{
5854+ struct mc_command cmd = { 0 };
5855+
5856+ /* prepare command */
5857+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_DISABLE,
5858+ cmd_flags,
5859+ token);
5860+
5861+ /* send command to mc*/
5862+ return mc_send_command(mc_io, &cmd);
5863+}
5864+
5865+int dpni_is_enabled(struct fsl_mc_io *mc_io,
5866+ uint32_t cmd_flags,
5867+ uint16_t token,
5868+ int *en)
5869+{
5870+ struct mc_command cmd = { 0 };
5871+ int err;
5872+ /* prepare command */
5873+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_IS_ENABLED, cmd_flags,
5874+ token);
5875+
5876+ /* send command to mc*/
5877+ err = mc_send_command(mc_io, &cmd);
5878+ if (err)
5879+ return err;
5880+
5881+ /* retrieve response parameters */
5882+ DPNI_RSP_IS_ENABLED(cmd, *en);
5883+
5884+ return 0;
5885+}
5886+
5887+int dpni_reset(struct fsl_mc_io *mc_io,
5888+ uint32_t cmd_flags,
5889+ uint16_t token)
5890+{
5891+ struct mc_command cmd = { 0 };
5892+
5893+ /* prepare command */
5894+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET,
5895+ cmd_flags,
5896+ token);
5897+
5898+ /* send command to mc*/
5899+ return mc_send_command(mc_io, &cmd);
5900+}
5901+
5902+int dpni_set_irq(struct fsl_mc_io *mc_io,
5903+ uint32_t cmd_flags,
5904+ uint16_t token,
5905+ uint8_t irq_index,
5906+ struct dpni_irq_cfg *irq_cfg)
5907+{
5908+ struct mc_command cmd = { 0 };
5909+
5910+ /* prepare command */
5911+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IRQ,
5912+ cmd_flags,
5913+ token);
5914+ DPNI_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
5915+
5916+ /* send command to mc*/
5917+ return mc_send_command(mc_io, &cmd);
5918+}
5919+
5920+int dpni_get_irq(struct fsl_mc_io *mc_io,
5921+ uint32_t cmd_flags,
5922+ uint16_t token,
5923+ uint8_t irq_index,
5924+ int *type,
5925+ struct dpni_irq_cfg *irq_cfg)
5926+{
5927+ struct mc_command cmd = { 0 };
5928+ int err;
5929+
5930+ /* prepare command */
5931+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ,
5932+ cmd_flags,
5933+ token);
5934+ DPNI_CMD_GET_IRQ(cmd, irq_index);
5935+
5936+ /* send command to mc*/
5937+ err = mc_send_command(mc_io, &cmd);
5938+ if (err)
5939+ return err;
5940+
5941+ /* retrieve response parameters */
5942+ DPNI_RSP_GET_IRQ(cmd, *type, irq_cfg);
5943+
5944+ return 0;
5945+}
5946+
5947+int dpni_set_irq_enable(struct fsl_mc_io *mc_io,
5948+ uint32_t cmd_flags,
5949+ uint16_t token,
5950+ uint8_t irq_index,
5951+ uint8_t en)
5952+{
5953+ struct mc_command cmd = { 0 };
5954+
5955+ /* prepare command */
5956+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IRQ_ENABLE,
5957+ cmd_flags,
5958+ token);
5959+ DPNI_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
5960+
5961+ /* send command to mc*/
5962+ return mc_send_command(mc_io, &cmd);
5963+}
5964+
5965+int dpni_get_irq_enable(struct fsl_mc_io *mc_io,
5966+ uint32_t cmd_flags,
5967+ uint16_t token,
5968+ uint8_t irq_index,
5969+ uint8_t *en)
5970+{
5971+ struct mc_command cmd = { 0 };
5972+ int err;
5973+
5974+ /* prepare command */
5975+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_ENABLE,
5976+ cmd_flags,
5977+ token);
5978+ DPNI_CMD_GET_IRQ_ENABLE(cmd, irq_index);
5979+
5980+ /* send command to mc*/
5981+ err = mc_send_command(mc_io, &cmd);
5982+ if (err)
5983+ return err;
5984+
5985+ /* retrieve response parameters */
5986+ DPNI_RSP_GET_IRQ_ENABLE(cmd, *en);
5987+
5988+ return 0;
5989+}
5990+
5991+int dpni_set_irq_mask(struct fsl_mc_io *mc_io,
5992+ uint32_t cmd_flags,
5993+ uint16_t token,
5994+ uint8_t irq_index,
5995+ uint32_t mask)
5996+{
5997+ struct mc_command cmd = { 0 };
5998+
5999+ /* prepare command */
6000+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IRQ_MASK,
6001+ cmd_flags,
6002+ token);
6003+ DPNI_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
6004+
6005+ /* send command to mc*/
6006+ return mc_send_command(mc_io, &cmd);
6007+}
6008+
6009+int dpni_get_irq_mask(struct fsl_mc_io *mc_io,
6010+ uint32_t cmd_flags,
6011+ uint16_t token,
6012+ uint8_t irq_index,
6013+ uint32_t *mask)
6014+{
6015+ struct mc_command cmd = { 0 };
6016+ int err;
6017+
6018+ /* prepare command */
6019+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_MASK,
6020+ cmd_flags,
6021+ token);
6022+ DPNI_CMD_GET_IRQ_MASK(cmd, irq_index);
6023+
6024+ /* send command to mc*/
6025+ err = mc_send_command(mc_io, &cmd);
6026+ if (err)
6027+ return err;
6028+
6029+ /* retrieve response parameters */
6030+ DPNI_RSP_GET_IRQ_MASK(cmd, *mask);
6031+
6032+ return 0;
6033+}
6034+
6035+int dpni_get_irq_status(struct fsl_mc_io *mc_io,
6036+ uint32_t cmd_flags,
6037+ uint16_t token,
6038+ uint8_t irq_index,
6039+ uint32_t *status)
6040+{
6041+ struct mc_command cmd = { 0 };
6042+ int err;
6043+
6044+ /* prepare command */
6045+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_STATUS,
6046+ cmd_flags,
6047+ token);
6048+ DPNI_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
6049+
6050+ /* send command to mc*/
6051+ err = mc_send_command(mc_io, &cmd);
6052+ if (err)
6053+ return err;
6054+
6055+ /* retrieve response parameters */
6056+ DPNI_RSP_GET_IRQ_STATUS(cmd, *status);
6057+
6058+ return 0;
6059+}
6060+
6061+int dpni_clear_irq_status(struct fsl_mc_io *mc_io,
6062+ uint32_t cmd_flags,
6063+ uint16_t token,
6064+ uint8_t irq_index,
6065+ uint32_t status)
6066+{
6067+ struct mc_command cmd = { 0 };
6068+
6069+ /* prepare command */
6070+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLEAR_IRQ_STATUS,
6071+ cmd_flags,
6072+ token);
6073+ DPNI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
6074+
6075+ /* send command to mc*/
6076+ return mc_send_command(mc_io, &cmd);
6077+}
6078+
6079+int dpni_get_attributes(struct fsl_mc_io *mc_io,
6080+ uint32_t cmd_flags,
6081+ uint16_t token,
6082+ struct dpni_attr *attr)
6083+{
6084+ struct mc_command cmd = { 0 };
6085+ int err;
6086+
6087+ /* prepare command */
6088+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR,
6089+ cmd_flags,
6090+ token);
6091+ DPNI_CMD_GET_ATTR(cmd, attr);
6092+
6093+ /* send command to mc*/
6094+ err = mc_send_command(mc_io, &cmd);
6095+ if (err)
6096+ return err;
6097+
6098+ /* retrieve response parameters */
6099+ DPNI_RSP_GET_ATTR(cmd, attr);
6100+
6101+ return 0;
6102+}
6103+
6104+int dpni_set_errors_behavior(struct fsl_mc_io *mc_io,
6105+ uint32_t cmd_flags,
6106+ uint16_t token,
6107+ struct dpni_error_cfg *cfg)
6108+{
6109+ struct mc_command cmd = { 0 };
6110+
6111+ /* prepare command */
6112+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_ERRORS_BEHAVIOR,
6113+ cmd_flags,
6114+ token);
6115+ DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg);
6116+
6117+ /* send command to mc*/
6118+ return mc_send_command(mc_io, &cmd);
6119+}
6120+
6121+int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io,
6122+ uint32_t cmd_flags,
6123+ uint16_t token,
6124+ struct dpni_buffer_layout *layout)
6125+{
6126+ struct mc_command cmd = { 0 };
6127+ int err;
6128+
6129+ /* prepare command */
6130+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_BUFFER_LAYOUT,
6131+ cmd_flags,
6132+ token);
6133+
6134+ /* send command to mc*/
6135+ err = mc_send_command(mc_io, &cmd);
6136+ if (err)
6137+ return err;
6138+
6139+ /* retrieve response parameters */
6140+ DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout);
6141+
6142+ return 0;
6143+}
6144+
6145+int dpni_set_rx_buffer_layout(struct fsl_mc_io *mc_io,
6146+ uint32_t cmd_flags,
6147+ uint16_t token,
6148+ const struct dpni_buffer_layout *layout)
6149+{
6150+ struct mc_command cmd = { 0 };
6151+
6152+ /* prepare command */
6153+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_BUFFER_LAYOUT,
6154+ cmd_flags,
6155+ token);
6156+ DPNI_CMD_SET_RX_BUFFER_LAYOUT(cmd, layout);
6157+
6158+ /* send command to mc*/
6159+ return mc_send_command(mc_io, &cmd);
6160+}
6161+
6162+int dpni_get_tx_buffer_layout(struct fsl_mc_io *mc_io,
6163+ uint32_t cmd_flags,
6164+ uint16_t token,
6165+ struct dpni_buffer_layout *layout)
6166+{
6167+ struct mc_command cmd = { 0 };
6168+ int err;
6169+
6170+ /* prepare command */
6171+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_BUFFER_LAYOUT,
6172+ cmd_flags,
6173+ token);
6174+
6175+ /* send command to mc*/
6176+ err = mc_send_command(mc_io, &cmd);
6177+ if (err)
6178+ return err;
6179+
6180+ /* retrieve response parameters */
6181+ DPNI_RSP_GET_TX_BUFFER_LAYOUT(cmd, layout);
6182+
6183+ return 0;
6184+}
6185+
6186+int dpni_set_tx_buffer_layout(struct fsl_mc_io *mc_io,
6187+ uint32_t cmd_flags,
6188+ uint16_t token,
6189+ const struct dpni_buffer_layout *layout)
6190+{
6191+ struct mc_command cmd = { 0 };
6192+
6193+ /* prepare command */
6194+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_BUFFER_LAYOUT,
6195+ cmd_flags,
6196+ token);
6197+ DPNI_CMD_SET_TX_BUFFER_LAYOUT(cmd, layout);
6198+
6199+ /* send command to mc*/
6200+ return mc_send_command(mc_io, &cmd);
6201+}
6202+
6203+int dpni_get_tx_conf_buffer_layout(struct fsl_mc_io *mc_io,
6204+ uint32_t cmd_flags,
6205+ uint16_t token,
6206+ struct dpni_buffer_layout *layout)
6207+{
6208+ struct mc_command cmd = { 0 };
6209+ int err;
6210+
6211+ /* prepare command */
6212+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT,
6213+ cmd_flags,
6214+ token);
6215+
6216+ /* send command to mc*/
6217+ err = mc_send_command(mc_io, &cmd);
6218+ if (err)
6219+ return err;
6220+
6221+ /* retrieve response parameters */
6222+ DPNI_RSP_GET_TX_CONF_BUFFER_LAYOUT(cmd, layout);
6223+
6224+ return 0;
6225+}
6226+
6227+int dpni_set_tx_conf_buffer_layout(struct fsl_mc_io *mc_io,
6228+ uint32_t cmd_flags,
6229+ uint16_t token,
6230+ const struct dpni_buffer_layout *layout)
6231+{
6232+ struct mc_command cmd = { 0 };
6233+
6234+ /* prepare command */
6235+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT,
6236+ cmd_flags,
6237+ token);
6238+ DPNI_CMD_SET_TX_CONF_BUFFER_LAYOUT(cmd, layout);
6239+
6240+ /* send command to mc*/
6241+ return mc_send_command(mc_io, &cmd);
6242+}
6243+
6244+int dpni_get_l3_chksum_validation(struct fsl_mc_io *mc_io,
6245+ uint32_t cmd_flags,
6246+ uint16_t token,
6247+ int *en)
6248+{
6249+ struct mc_command cmd = { 0 };
6250+ int err;
6251+
6252+ /* prepare command */
6253+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_L3_CHKSUM_VALIDATION,
6254+ cmd_flags,
6255+ token);
6256+
6257+ /* send command to mc*/
6258+ err = mc_send_command(mc_io, &cmd);
6259+ if (err)
6260+ return err;
6261+
6262+ /* retrieve response parameters */
6263+ DPNI_RSP_GET_L3_CHKSUM_VALIDATION(cmd, *en);
6264+
6265+ return 0;
6266+}
6267+
6268+int dpni_set_l3_chksum_validation(struct fsl_mc_io *mc_io,
6269+ uint32_t cmd_flags,
6270+ uint16_t token,
6271+ int en)
6272+{
6273+ struct mc_command cmd = { 0 };
6274+
6275+ /* prepare command */
6276+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_L3_CHKSUM_VALIDATION,
6277+ cmd_flags,
6278+ token);
6279+ DPNI_CMD_SET_L3_CHKSUM_VALIDATION(cmd, en);
6280+
6281+ /* send command to mc*/
6282+ return mc_send_command(mc_io, &cmd);
6283+}
6284+
6285+int dpni_get_l4_chksum_validation(struct fsl_mc_io *mc_io,
6286+ uint32_t cmd_flags,
6287+ uint16_t token,
6288+ int *en)
6289+{
6290+ struct mc_command cmd = { 0 };
6291+ int err;
6292+
6293+ /* prepare command */
6294+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_L4_CHKSUM_VALIDATION,
6295+ cmd_flags,
6296+ token);
6297+
6298+ /* send command to mc*/
6299+ err = mc_send_command(mc_io, &cmd);
6300+ if (err)
6301+ return err;
6302+
6303+ /* retrieve response parameters */
6304+ DPNI_RSP_GET_L4_CHKSUM_VALIDATION(cmd, *en);
6305+
6306+ return 0;
6307+}
6308+
6309+int dpni_set_l4_chksum_validation(struct fsl_mc_io *mc_io,
6310+ uint32_t cmd_flags,
6311+ uint16_t token,
6312+ int en)
6313+{
6314+ struct mc_command cmd = { 0 };
6315+
6316+ /* prepare command */
6317+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_L4_CHKSUM_VALIDATION,
6318+ cmd_flags,
6319+ token);
6320+ DPNI_CMD_SET_L4_CHKSUM_VALIDATION(cmd, en);
6321+
6322+ /* send command to mc*/
6323+ return mc_send_command(mc_io, &cmd);
6324+}
6325+
6326+int dpni_get_qdid(struct fsl_mc_io *mc_io,
6327+ uint32_t cmd_flags,
6328+ uint16_t token,
6329+ uint16_t *qdid)
6330+{
6331+ struct mc_command cmd = { 0 };
6332+ int err;
6333+
6334+ /* prepare command */
6335+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QDID,
6336+ cmd_flags,
6337+ token);
6338+
6339+ /* send command to mc*/
6340+ err = mc_send_command(mc_io, &cmd);
6341+ if (err)
6342+ return err;
6343+
6344+ /* retrieve response parameters */
6345+ DPNI_RSP_GET_QDID(cmd, *qdid);
6346+
6347+ return 0;
6348+}
6349+
6350+int dpni_get_sp_info(struct fsl_mc_io *mc_io,
6351+ uint32_t cmd_flags,
6352+ uint16_t token,
6353+ struct dpni_sp_info *sp_info)
6354+{
6355+ struct mc_command cmd = { 0 };
6356+ int err;
6357+
6358+ /* prepare command */
6359+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_SP_INFO,
6360+ cmd_flags,
6361+ token);
6362+
6363+ /* send command to mc*/
6364+ err = mc_send_command(mc_io, &cmd);
6365+ if (err)
6366+ return err;
6367+
6368+ /* retrieve response parameters */
6369+ DPNI_RSP_GET_SP_INFO(cmd, sp_info);
6370+
6371+ return 0;
6372+}
6373+
6374+int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io,
6375+ uint32_t cmd_flags,
6376+ uint16_t token,
6377+ uint16_t *data_offset)
6378+{
6379+ struct mc_command cmd = { 0 };
6380+ int err;
6381+
6382+ /* prepare command */
6383+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_DATA_OFFSET,
6384+ cmd_flags,
6385+ token);
6386+
6387+ /* send command to mc*/
6388+ err = mc_send_command(mc_io, &cmd);
6389+ if (err)
6390+ return err;
6391+
6392+ /* retrieve response parameters */
6393+ DPNI_RSP_GET_TX_DATA_OFFSET(cmd, *data_offset);
6394+
6395+ return 0;
6396+}
6397+
6398+int dpni_get_counter(struct fsl_mc_io *mc_io,
6399+ uint32_t cmd_flags,
6400+ uint16_t token,
6401+ enum dpni_counter counter,
6402+ uint64_t *value)
6403+{
6404+ struct mc_command cmd = { 0 };
6405+ int err;
6406+
6407+ /* prepare command */
6408+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_COUNTER,
6409+ cmd_flags,
6410+ token);
6411+ DPNI_CMD_GET_COUNTER(cmd, counter);
6412+
6413+ /* send command to mc*/
6414+ err = mc_send_command(mc_io, &cmd);
6415+ if (err)
6416+ return err;
6417+
6418+ /* retrieve response parameters */
6419+ DPNI_RSP_GET_COUNTER(cmd, *value);
6420+
6421+ return 0;
6422+}
6423+
6424+int dpni_set_counter(struct fsl_mc_io *mc_io,
6425+ uint32_t cmd_flags,
6426+ uint16_t token,
6427+ enum dpni_counter counter,
6428+ uint64_t value)
6429+{
6430+ struct mc_command cmd = { 0 };
6431+
6432+ /* prepare command */
6433+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_COUNTER,
6434+ cmd_flags,
6435+ token);
6436+ DPNI_CMD_SET_COUNTER(cmd, counter, value);
6437+
6438+ /* send command to mc*/
6439+ return mc_send_command(mc_io, &cmd);
6440+}
6441+
6442+int dpni_set_link_cfg(struct fsl_mc_io *mc_io,
6443+ uint32_t cmd_flags,
6444+ uint16_t token,
6445+ const struct dpni_link_cfg *cfg)
6446+{
6447+ struct mc_command cmd = { 0 };
6448+
6449+ /* prepare command */
6450+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_LINK_CFG,
6451+ cmd_flags,
6452+ token);
6453+ DPNI_CMD_SET_LINK_CFG(cmd, cfg);
6454+
6455+ /* send command to mc*/
6456+ return mc_send_command(mc_io, &cmd);
6457+}
6458+
6459+int dpni_get_link_state(struct fsl_mc_io *mc_io,
6460+ uint32_t cmd_flags,
6461+ uint16_t token,
6462+ struct dpni_link_state *state)
6463+{
6464+ struct mc_command cmd = { 0 };
6465+ int err;
6466+
6467+ /* prepare command */
6468+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_LINK_STATE,
6469+ cmd_flags,
6470+ token);
6471+
6472+ /* send command to mc*/
6473+ err = mc_send_command(mc_io, &cmd);
6474+ if (err)
6475+ return err;
6476+
6477+ /* retrieve response parameters */
6478+ DPNI_RSP_GET_LINK_STATE(cmd, state);
6479+
6480+ return 0;
6481+}
6482+
6483+int dpni_set_tx_shaping(struct fsl_mc_io *mc_io,
6484+ uint32_t cmd_flags,
6485+ uint16_t token,
6486+ const struct dpni_tx_shaping_cfg *tx_shaper)
6487+{
6488+ struct mc_command cmd = { 0 };
6489+
6490+ /* prepare command */
6491+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_SHAPING,
6492+ cmd_flags,
6493+ token);
6494+ DPNI_CMD_SET_TX_SHAPING(cmd, tx_shaper);
6495+
6496+ /* send command to mc*/
6497+ return mc_send_command(mc_io, &cmd);
6498+}
6499+
6500+int dpni_set_max_frame_length(struct fsl_mc_io *mc_io,
6501+ uint32_t cmd_flags,
6502+ uint16_t token,
6503+ uint16_t max_frame_length)
6504+{
6505+ struct mc_command cmd = { 0 };
6506+
6507+ /* prepare command */
6508+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_MAX_FRAME_LENGTH,
6509+ cmd_flags,
6510+ token);
6511+ DPNI_CMD_SET_MAX_FRAME_LENGTH(cmd, max_frame_length);
6512+
6513+ /* send command to mc*/
6514+ return mc_send_command(mc_io, &cmd);
6515+}
6516+
6517+int dpni_get_max_frame_length(struct fsl_mc_io *mc_io,
6518+ uint32_t cmd_flags,
6519+ uint16_t token,
6520+ uint16_t *max_frame_length)
6521+{
6522+ struct mc_command cmd = { 0 };
6523+ int err;
6524+
6525+ /* prepare command */
6526+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_MAX_FRAME_LENGTH,
6527+ cmd_flags,
6528+ token);
6529+
6530+ /* send command to mc*/
6531+ err = mc_send_command(mc_io, &cmd);
6532+ if (err)
6533+ return err;
6534+
6535+ /* retrieve response parameters */
6536+ DPNI_RSP_GET_MAX_FRAME_LENGTH(cmd, *max_frame_length);
6537+
6538+ return 0;
6539+}
6540+
6541+int dpni_set_mtu(struct fsl_mc_io *mc_io,
6542+ uint32_t cmd_flags,
6543+ uint16_t token,
6544+ uint16_t mtu)
6545+{
6546+ struct mc_command cmd = { 0 };
6547+
6548+ /* prepare command */
6549+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_MTU,
6550+ cmd_flags,
6551+ token);
6552+ DPNI_CMD_SET_MTU(cmd, mtu);
6553+
6554+ /* send command to mc*/
6555+ return mc_send_command(mc_io, &cmd);
6556+}
6557+
6558+int dpni_get_mtu(struct fsl_mc_io *mc_io,
6559+ uint32_t cmd_flags,
6560+ uint16_t token,
6561+ uint16_t *mtu)
6562+{
6563+ struct mc_command cmd = { 0 };
6564+ int err;
6565+
6566+ /* prepare command */
6567+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_MTU,
6568+ cmd_flags,
6569+ token);
6570+
6571+ /* send command to mc*/
6572+ err = mc_send_command(mc_io, &cmd);
6573+ if (err)
6574+ return err;
6575+
6576+ /* retrieve response parameters */
6577+ DPNI_RSP_GET_MTU(cmd, *mtu);
6578+
6579+ return 0;
6580+}
6581+
6582+int dpni_set_multicast_promisc(struct fsl_mc_io *mc_io,
6583+ uint32_t cmd_flags,
6584+ uint16_t token,
6585+ int en)
6586+{
6587+ struct mc_command cmd = { 0 };
6588+
6589+ /* prepare command */
6590+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_MCAST_PROMISC,
6591+ cmd_flags,
6592+ token);
6593+ DPNI_CMD_SET_MULTICAST_PROMISC(cmd, en);
6594+
6595+ /* send command to mc*/
6596+ return mc_send_command(mc_io, &cmd);
6597+}
6598+
6599+int dpni_get_multicast_promisc(struct fsl_mc_io *mc_io,
6600+ uint32_t cmd_flags,
6601+ uint16_t token,
6602+ int *en)
6603+{
6604+ struct mc_command cmd = { 0 };
6605+ int err;
6606+
6607+ /* prepare command */
6608+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_MCAST_PROMISC,
6609+ cmd_flags,
6610+ token);
6611+
6612+ /* send command to mc*/
6613+ err = mc_send_command(mc_io, &cmd);
6614+ if (err)
6615+ return err;
6616+
6617+ /* retrieve response parameters */
6618+ DPNI_RSP_GET_MULTICAST_PROMISC(cmd, *en);
6619+
6620+ return 0;
6621+}
6622+
6623+int dpni_set_unicast_promisc(struct fsl_mc_io *mc_io,
6624+ uint32_t cmd_flags,
6625+ uint16_t token,
6626+ int en)
6627+{
6628+ struct mc_command cmd = { 0 };
6629+
6630+ /* prepare command */
6631+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_UNICAST_PROMISC,
6632+ cmd_flags,
6633+ token);
6634+ DPNI_CMD_SET_UNICAST_PROMISC(cmd, en);
6635+
6636+ /* send command to mc*/
6637+ return mc_send_command(mc_io, &cmd);
6638+}
6639+
6640+int dpni_get_unicast_promisc(struct fsl_mc_io *mc_io,
6641+ uint32_t cmd_flags,
6642+ uint16_t token,
6643+ int *en)
6644+{
6645+ struct mc_command cmd = { 0 };
6646+ int err;
6647+
6648+ /* prepare command */
6649+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_UNICAST_PROMISC,
6650+ cmd_flags,
6651+ token);
6652+
6653+ /* send command to mc*/
6654+ err = mc_send_command(mc_io, &cmd);
6655+ if (err)
6656+ return err;
6657+
6658+ /* retrieve response parameters */
6659+ DPNI_RSP_GET_UNICAST_PROMISC(cmd, *en);
6660+
6661+ return 0;
6662+}
6663+
6664+int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io,
6665+ uint32_t cmd_flags,
6666+ uint16_t token,
6667+ const uint8_t mac_addr[6])
6668+{
6669+ struct mc_command cmd = { 0 };
6670+
6671+ /* prepare command */
6672+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_PRIM_MAC,
6673+ cmd_flags,
6674+ token);
6675+ DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr);
6676+
6677+ /* send command to mc*/
6678+ return mc_send_command(mc_io, &cmd);
6679+}
6680+
6681+int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io,
6682+ uint32_t cmd_flags,
6683+ uint16_t token,
6684+ uint8_t mac_addr[6])
6685+{
6686+ struct mc_command cmd = { 0 };
6687+ int err;
6688+
6689+ /* prepare command */
6690+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_PRIM_MAC,
6691+ cmd_flags,
6692+ token);
6693+
6694+ /* send command to mc*/
6695+ err = mc_send_command(mc_io, &cmd);
6696+ if (err)
6697+ return err;
6698+
6699+ /* retrieve response parameters */
6700+ DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr);
6701+
6702+ return 0;
6703+}
6704+
6705+int dpni_add_mac_addr(struct fsl_mc_io *mc_io,
6706+ uint32_t cmd_flags,
6707+ uint16_t token,
6708+ const uint8_t mac_addr[6])
6709+{
6710+ struct mc_command cmd = { 0 };
6711+
6712+ /* prepare command */
6713+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_MAC_ADDR,
6714+ cmd_flags,
6715+ token);
6716+ DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr);
6717+
6718+ /* send command to mc*/
6719+ return mc_send_command(mc_io, &cmd);
6720+}
6721+
6722+int dpni_remove_mac_addr(struct fsl_mc_io *mc_io,
6723+ uint32_t cmd_flags,
6724+ uint16_t token,
6725+ const uint8_t mac_addr[6])
6726+{
6727+ struct mc_command cmd = { 0 };
6728+
6729+ /* prepare command */
6730+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_MAC_ADDR,
6731+ cmd_flags,
6732+ token);
6733+ DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr);
6734+
6735+ /* send command to mc*/
6736+ return mc_send_command(mc_io, &cmd);
6737+}
6738+
6739+int dpni_clear_mac_filters(struct fsl_mc_io *mc_io,
6740+ uint32_t cmd_flags,
6741+ uint16_t token,
6742+ int unicast,
6743+ int multicast)
6744+{
6745+ struct mc_command cmd = { 0 };
6746+
6747+ /* prepare command */
6748+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLR_MAC_FILTERS,
6749+ cmd_flags,
6750+ token);
6751+ DPNI_CMD_CLEAR_MAC_FILTERS(cmd, unicast, multicast);
6752+
6753+ /* send command to mc*/
6754+ return mc_send_command(mc_io, &cmd);
6755+}
6756+
6757+int dpni_set_vlan_filters(struct fsl_mc_io *mc_io,
6758+ uint32_t cmd_flags,
6759+ uint16_t token,
6760+ int en)
6761+{
6762+ struct mc_command cmd = { 0 };
6763+
6764+ /* prepare command */
6765+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_VLAN_FILTERS,
6766+ cmd_flags,
6767+ token);
6768+ DPNI_CMD_SET_VLAN_FILTERS(cmd, en);
6769+
6770+ /* send command to mc*/
6771+ return mc_send_command(mc_io, &cmd);
6772+}
6773+
6774+int dpni_add_vlan_id(struct fsl_mc_io *mc_io,
6775+ uint32_t cmd_flags,
6776+ uint16_t token,
6777+ uint16_t vlan_id)
6778+{
6779+ struct mc_command cmd = { 0 };
6780+
6781+ /* prepare command */
6782+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_VLAN_ID,
6783+ cmd_flags,
6784+ token);
6785+ DPNI_CMD_ADD_VLAN_ID(cmd, vlan_id);
6786+
6787+ /* send command to mc*/
6788+ return mc_send_command(mc_io, &cmd);
6789+}
6790+
6791+int dpni_remove_vlan_id(struct fsl_mc_io *mc_io,
6792+ uint32_t cmd_flags,
6793+ uint16_t token,
6794+ uint16_t vlan_id)
6795+{
6796+ struct mc_command cmd = { 0 };
6797+
6798+ /* prepare command */
6799+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_VLAN_ID,
6800+ cmd_flags,
6801+ token);
6802+ DPNI_CMD_REMOVE_VLAN_ID(cmd, vlan_id);
6803+
6804+ /* send command to mc*/
6805+ return mc_send_command(mc_io, &cmd);
6806+}
6807+
6808+int dpni_clear_vlan_filters(struct fsl_mc_io *mc_io,
6809+ uint32_t cmd_flags,
6810+ uint16_t token)
6811+{
6812+ struct mc_command cmd = { 0 };
6813+
6814+ /* prepare command */
6815+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLR_VLAN_FILTERS,
6816+ cmd_flags,
6817+ token);
6818+
6819+ /* send command to mc*/
6820+ return mc_send_command(mc_io, &cmd);
6821+}
6822+
6823+int dpni_set_tx_selection(struct fsl_mc_io *mc_io,
6824+ uint32_t cmd_flags,
6825+ uint16_t token,
6826+ const struct dpni_tx_selection_cfg *cfg)
6827+{
6828+ struct mc_command cmd = { 0 };
6829+
6830+ /* prepare command */
6831+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_SELECTION,
6832+ cmd_flags,
6833+ token);
6834+ DPNI_CMD_SET_TX_SELECTION(cmd, cfg);
6835+
6836+ /* send command to mc*/
6837+ return mc_send_command(mc_io, &cmd);
6838+}
6839+
6840+int dpni_set_rx_tc_dist(struct fsl_mc_io *mc_io,
6841+ uint32_t cmd_flags,
6842+ uint16_t token,
6843+ uint8_t tc_id,
6844+ const struct dpni_rx_tc_dist_cfg *cfg)
6845+{
6846+ struct mc_command cmd = { 0 };
6847+
6848+ /* prepare command */
6849+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_TC_DIST,
6850+ cmd_flags,
6851+ token);
6852+ DPNI_CMD_SET_RX_TC_DIST(cmd, tc_id, cfg);
6853+
6854+ /* send command to mc*/
6855+ return mc_send_command(mc_io, &cmd);
6856+}
6857+
6858+int dpni_set_tx_flow(struct fsl_mc_io *mc_io,
6859+ uint32_t cmd_flags,
6860+ uint16_t token,
6861+ uint16_t *flow_id,
6862+ const struct dpni_tx_flow_cfg *cfg)
6863+{
6864+ struct mc_command cmd = { 0 };
6865+ int err;
6866+
6867+ /* prepare command */
6868+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_FLOW,
6869+ cmd_flags,
6870+ token);
6871+ DPNI_CMD_SET_TX_FLOW(cmd, *flow_id, cfg);
6872+
6873+ /* send command to mc*/
6874+ err = mc_send_command(mc_io, &cmd);
6875+ if (err)
6876+ return err;
6877+
6878+ /* retrieve response parameters */
6879+ DPNI_RSP_SET_TX_FLOW(cmd, *flow_id);
6880+
6881+ return 0;
6882+}
6883+
6884+int dpni_get_tx_flow(struct fsl_mc_io *mc_io,
6885+ uint32_t cmd_flags,
6886+ uint16_t token,
6887+ uint16_t flow_id,
6888+ struct dpni_tx_flow_attr *attr)
6889+{
6890+ struct mc_command cmd = { 0 };
6891+ int err;
6892+
6893+ /* prepare command */
6894+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_FLOW,
6895+ cmd_flags,
6896+ token);
6897+ DPNI_CMD_GET_TX_FLOW(cmd, flow_id);
6898+
6899+ /* send command to mc*/
6900+ err = mc_send_command(mc_io, &cmd);
6901+ if (err)
6902+ return err;
6903+
6904+ /* retrieve response parameters */
6905+ DPNI_RSP_GET_TX_FLOW(cmd, attr);
6906+
6907+ return 0;
6908+}
6909+
6910+int dpni_set_rx_flow(struct fsl_mc_io *mc_io,
6911+ uint32_t cmd_flags,
6912+ uint16_t token,
6913+ uint8_t tc_id,
6914+ uint16_t flow_id,
6915+ const struct dpni_queue_cfg *cfg)
6916+{
6917+ struct mc_command cmd = { 0 };
6918+
6919+ /* prepare command */
6920+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_FLOW,
6921+ cmd_flags,
6922+ token);
6923+ DPNI_CMD_SET_RX_FLOW(cmd, tc_id, flow_id, cfg);
6924+
6925+ /* send command to mc*/
6926+ return mc_send_command(mc_io, &cmd);
6927+}
6928+
6929+int dpni_get_rx_flow(struct fsl_mc_io *mc_io,
6930+ uint32_t cmd_flags,
6931+ uint16_t token,
6932+ uint8_t tc_id,
6933+ uint16_t flow_id,
6934+ struct dpni_queue_attr *attr)
6935+{
6936+ struct mc_command cmd = { 0 };
6937+ int err;
6938+ /* prepare command */
6939+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_FLOW,
6940+ cmd_flags,
6941+ token);
6942+ DPNI_CMD_GET_RX_FLOW(cmd, tc_id, flow_id);
6943+
6944+ /* send command to mc*/
6945+ err = mc_send_command(mc_io, &cmd);
6946+ if (err)
6947+ return err;
6948+
6949+ /* retrieve response parameters */
6950+ DPNI_RSP_GET_RX_FLOW(cmd, attr);
6951+
6952+ return 0;
6953+}
6954+
6955+int dpni_set_rx_err_queue(struct fsl_mc_io *mc_io,
6956+ uint32_t cmd_flags,
6957+ uint16_t token,
6958+ const struct dpni_queue_cfg *cfg)
6959+{
6960+ struct mc_command cmd = { 0 };
6961+
6962+ /* prepare command */
6963+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_ERR_QUEUE,
6964+ cmd_flags,
6965+ token);
6966+ DPNI_CMD_SET_RX_ERR_QUEUE(cmd, cfg);
6967+
6968+ /* send command to mc*/
6969+ return mc_send_command(mc_io, &cmd);
6970+}
6971+
6972+int dpni_get_rx_err_queue(struct fsl_mc_io *mc_io,
6973+ uint32_t cmd_flags,
6974+ uint16_t token,
6975+ struct dpni_queue_attr *attr)
6976+{
6977+ struct mc_command cmd = { 0 };
6978+ int err;
6979+
6980+ /* prepare command */
6981+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_ERR_QUEUE,
6982+ cmd_flags,
6983+ token);
6984+
6985+ /* send command to mc*/
6986+ err = mc_send_command(mc_io, &cmd);
6987+ if (err)
6988+ return err;
6989+
6990+ /* retrieve response parameters */
6991+ DPNI_RSP_GET_RX_ERR_QUEUE(cmd, attr);
6992+
6993+ return 0;
6994+}
6995+
6996+int dpni_set_tx_conf_revoke(struct fsl_mc_io *mc_io,
6997+ uint32_t cmd_flags,
6998+ uint16_t token,
6999+ int revoke)
7000+{
7001+ struct mc_command cmd = { 0 };
7002+
7003+ /* prepare command */
7004+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF_REVOKE,
7005+ cmd_flags,
7006+ token);
7007+ DPNI_CMD_SET_TX_CONF_REVOKE(cmd, revoke);
7008+
7009+ /* send command to mc*/
7010+ return mc_send_command(mc_io, &cmd);
7011+}
7012+
7013+int dpni_set_qos_table(struct fsl_mc_io *mc_io,
7014+ uint32_t cmd_flags,
7015+ uint16_t token,
7016+ const struct dpni_qos_tbl_cfg *cfg)
7017+{
7018+ struct mc_command cmd = { 0 };
7019+
7020+ /* prepare command */
7021+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_QOS_TBL,
7022+ cmd_flags,
7023+ token);
7024+ DPNI_CMD_SET_QOS_TABLE(cmd, cfg);
7025+
7026+ /* send command to mc*/
7027+ return mc_send_command(mc_io, &cmd);
7028+}
7029+
7030+int dpni_add_qos_entry(struct fsl_mc_io *mc_io,
7031+ uint32_t cmd_flags,
7032+ uint16_t token,
7033+ const struct dpni_rule_cfg *cfg,
7034+ uint8_t tc_id)
7035+{
7036+ struct mc_command cmd = { 0 };
7037+
7038+ /* prepare command */
7039+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_QOS_ENT,
7040+ cmd_flags,
7041+ token);
7042+ DPNI_CMD_ADD_QOS_ENTRY(cmd, cfg, tc_id);
7043+
7044+ /* send command to mc*/
7045+ return mc_send_command(mc_io, &cmd);
7046+}
7047+
7048+int dpni_remove_qos_entry(struct fsl_mc_io *mc_io,
7049+ uint32_t cmd_flags,
7050+ uint16_t token,
7051+ const struct dpni_rule_cfg *cfg)
7052+{
7053+ struct mc_command cmd = { 0 };
7054+
7055+ /* prepare command */
7056+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_QOS_ENT,
7057+ cmd_flags,
7058+ token);
7059+ DPNI_CMD_REMOVE_QOS_ENTRY(cmd, cfg);
7060+
7061+ /* send command to mc*/
7062+ return mc_send_command(mc_io, &cmd);
7063+}
7064+
7065+int dpni_clear_qos_table(struct fsl_mc_io *mc_io,
7066+ uint32_t cmd_flags,
7067+ uint16_t token)
7068+{
7069+ struct mc_command cmd = { 0 };
7070+
7071+ /* prepare command */
7072+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLR_QOS_TBL,
7073+ cmd_flags,
7074+ token);
7075+
7076+ /* send command to mc*/
7077+ return mc_send_command(mc_io, &cmd);
7078+}
7079+
7080+int dpni_add_fs_entry(struct fsl_mc_io *mc_io,
7081+ uint32_t cmd_flags,
7082+ uint16_t token,
7083+ uint8_t tc_id,
7084+ const struct dpni_rule_cfg *cfg,
7085+ uint16_t flow_id)
7086+{
7087+ struct mc_command cmd = { 0 };
7088+
7089+ /* prepare command */
7090+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_FS_ENT,
7091+ cmd_flags,
7092+ token);
7093+ DPNI_CMD_ADD_FS_ENTRY(cmd, tc_id, cfg, flow_id);
7094+
7095+ /* send command to mc*/
7096+ return mc_send_command(mc_io, &cmd);
7097+}
7098+
7099+int dpni_remove_fs_entry(struct fsl_mc_io *mc_io,
7100+ uint32_t cmd_flags,
7101+ uint16_t token,
7102+ uint8_t tc_id,
7103+ const struct dpni_rule_cfg *cfg)
7104+{
7105+ struct mc_command cmd = { 0 };
7106+
7107+ /* prepare command */
7108+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_FS_ENT,
7109+ cmd_flags,
7110+ token);
7111+ DPNI_CMD_REMOVE_FS_ENTRY(cmd, tc_id, cfg);
7112+
7113+ /* send command to mc*/
7114+ return mc_send_command(mc_io, &cmd);
7115+}
7116+
7117+int dpni_clear_fs_entries(struct fsl_mc_io *mc_io,
7118+ uint32_t cmd_flags,
7119+ uint16_t token,
7120+ uint8_t tc_id)
7121+{
7122+ struct mc_command cmd = { 0 };
7123+
7124+ /* prepare command */
7125+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLR_FS_ENT,
7126+ cmd_flags,
7127+ token);
7128+ DPNI_CMD_CLEAR_FS_ENTRIES(cmd, tc_id);
7129+
7130+ /* send command to mc*/
7131+ return mc_send_command(mc_io, &cmd);
7132+}
7133+
7134+int dpni_set_vlan_insertion(struct fsl_mc_io *mc_io,
7135+ uint32_t cmd_flags,
7136+ uint16_t token,
7137+ int en)
7138+{
7139+ struct mc_command cmd = { 0 };
7140+
7141+ /* prepare command */
7142+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_VLAN_INSERTION,
7143+ cmd_flags, token);
7144+ DPNI_CMD_SET_VLAN_INSERTION(cmd, en);
7145+
7146+ /* send command to mc*/
7147+ return mc_send_command(mc_io, &cmd);
7148+}
7149+
7150+int dpni_set_vlan_removal(struct fsl_mc_io *mc_io,
7151+ uint32_t cmd_flags,
7152+ uint16_t token,
7153+ int en)
7154+{
7155+ struct mc_command cmd = { 0 };
7156+
7157+ /* prepare command */
7158+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_VLAN_REMOVAL,
7159+ cmd_flags, token);
7160+ DPNI_CMD_SET_VLAN_REMOVAL(cmd, en);
7161+
7162+ /* send command to mc*/
7163+ return mc_send_command(mc_io, &cmd);
7164+}
7165+
7166+int dpni_set_ipr(struct fsl_mc_io *mc_io,
7167+ uint32_t cmd_flags,
7168+ uint16_t token,
7169+ int en)
7170+{
7171+ struct mc_command cmd = { 0 };
7172+
7173+ /* prepare command */
7174+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IPR,
7175+ cmd_flags,
7176+ token);
7177+ DPNI_CMD_SET_IPR(cmd, en);
7178+
7179+ /* send command to mc*/
7180+ return mc_send_command(mc_io, &cmd);
7181+}
7182+
7183+int dpni_set_ipf(struct fsl_mc_io *mc_io,
7184+ uint32_t cmd_flags,
7185+ uint16_t token,
7186+ int en)
7187+{
7188+ struct mc_command cmd = { 0 };
7189+
7190+ /* prepare command */
7191+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IPF,
7192+ cmd_flags,
7193+ token);
7194+ DPNI_CMD_SET_IPF(cmd, en);
7195+
7196+ /* send command to mc*/
7197+ return mc_send_command(mc_io, &cmd);
7198+}
7199+
7200+int dpni_set_rx_tc_policing(struct fsl_mc_io *mc_io,
7201+ uint32_t cmd_flags,
7202+ uint16_t token,
7203+ uint8_t tc_id,
7204+ const struct dpni_rx_tc_policing_cfg *cfg)
7205+{
7206+ struct mc_command cmd = { 0 };
7207+
7208+ /* prepare command */
7209+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_TC_POLICING,
7210+ cmd_flags,
7211+ token);
7212+ DPNI_CMD_SET_RX_TC_POLICING(cmd, tc_id, cfg);
7213+
7214+ /* send command to mc*/
7215+ return mc_send_command(mc_io, &cmd);
7216+}
7217+
7218+int dpni_get_rx_tc_policing(struct fsl_mc_io *mc_io,
7219+ uint32_t cmd_flags,
7220+ uint16_t token,
7221+ uint8_t tc_id,
7222+ struct dpni_rx_tc_policing_cfg *cfg)
7223+{
7224+ struct mc_command cmd = { 0 };
7225+ int err;
7226+
7227+ /* prepare command */
7228+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_TC_POLICING,
7229+ cmd_flags,
7230+ token);
7231+ DPNI_CMD_GET_RX_TC_POLICING(cmd, tc_id);
7232+
7233+ /* send command to mc*/
7234+ err = mc_send_command(mc_io, &cmd);
7235+ if (err)
7236+ return err;
7237+
7238+ DPNI_RSP_GET_RX_TC_POLICING(cmd, cfg);
7239+
7240+ return 0;
7241+}
7242+
7243+void dpni_prepare_early_drop(const struct dpni_early_drop_cfg *cfg,
7244+ uint8_t *early_drop_buf)
7245+{
7246+ uint64_t *ext_params = (uint64_t *)early_drop_buf;
7247+
7248+ DPNI_PREP_EARLY_DROP(ext_params, cfg);
7249+}
7250+
7251+void dpni_extract_early_drop(struct dpni_early_drop_cfg *cfg,
7252+ const uint8_t *early_drop_buf)
7253+{
7254+ const uint64_t *ext_params = (const uint64_t *)early_drop_buf;
7255+
7256+ DPNI_EXT_EARLY_DROP(ext_params, cfg);
7257+}
7258+
7259+int dpni_set_rx_tc_early_drop(struct fsl_mc_io *mc_io,
7260+ uint32_t cmd_flags,
7261+ uint16_t token,
7262+ uint8_t tc_id,
7263+ uint64_t early_drop_iova)
7264+{
7265+ struct mc_command cmd = { 0 };
7266+
7267+ /* prepare command */
7268+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_TC_EARLY_DROP,
7269+ cmd_flags,
7270+ token);
7271+ DPNI_CMD_SET_RX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova);
7272+
7273+ /* send command to mc*/
7274+ return mc_send_command(mc_io, &cmd);
7275+}
7276+
7277+int dpni_get_rx_tc_early_drop(struct fsl_mc_io *mc_io,
7278+ uint32_t cmd_flags,
7279+ uint16_t token,
7280+ uint8_t tc_id,
7281+ uint64_t early_drop_iova)
7282+{
7283+ struct mc_command cmd = { 0 };
7284+
7285+ /* prepare command */
7286+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_TC_EARLY_DROP,
7287+ cmd_flags,
7288+ token);
7289+ DPNI_CMD_GET_RX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova);
7290+
7291+ /* send command to mc*/
7292+ return mc_send_command(mc_io, &cmd);
7293+}
7294+
7295+int dpni_set_tx_tc_early_drop(struct fsl_mc_io *mc_io,
7296+ uint32_t cmd_flags,
7297+ uint16_t token,
7298+ uint8_t tc_id,
7299+ uint64_t early_drop_iova)
7300+{
7301+ struct mc_command cmd = { 0 };
7302+
7303+ /* prepare command */
7304+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_TC_EARLY_DROP,
7305+ cmd_flags,
7306+ token);
7307+ DPNI_CMD_SET_TX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova);
7308+
7309+ /* send command to mc*/
7310+ return mc_send_command(mc_io, &cmd);
7311+}
7312+
7313+int dpni_get_tx_tc_early_drop(struct fsl_mc_io *mc_io,
7314+ uint32_t cmd_flags,
7315+ uint16_t token,
7316+ uint8_t tc_id,
7317+ uint64_t early_drop_iova)
7318+{
7319+ struct mc_command cmd = { 0 };
7320+
7321+ /* prepare command */
7322+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_TC_EARLY_DROP,
7323+ cmd_flags,
7324+ token);
7325+ DPNI_CMD_GET_TX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova);
7326+
7327+ /* send command to mc*/
7328+ return mc_send_command(mc_io, &cmd);
7329+}
7330+
7331+int dpni_set_rx_tc_congestion_notification(struct fsl_mc_io *mc_io,
7332+ uint32_t cmd_flags,
7333+ uint16_t token,
7334+ uint8_t tc_id,
7335+ const struct dpni_congestion_notification_cfg *cfg)
7336+{
7337+ struct mc_command cmd = { 0 };
7338+
7339+ /* prepare command */
7340+ cmd.header = mc_encode_cmd_header(
7341+ DPNI_CMDID_SET_RX_TC_CONGESTION_NOTIFICATION,
7342+ cmd_flags,
7343+ token);
7344+ DPNI_CMD_SET_RX_TC_CONGESTION_NOTIFICATION(cmd, tc_id, cfg);
7345+
7346+ /* send command to mc*/
7347+ return mc_send_command(mc_io, &cmd);
7348+}
7349+
7350+int dpni_get_rx_tc_congestion_notification(struct fsl_mc_io *mc_io,
7351+ uint32_t cmd_flags,
7352+ uint16_t token,
7353+ uint8_t tc_id,
7354+ struct dpni_congestion_notification_cfg *cfg)
7355+{
7356+ struct mc_command cmd = { 0 };
7357+ int err;
7358+
7359+ /* prepare command */
7360+ cmd.header = mc_encode_cmd_header(
7361+ DPNI_CMDID_GET_RX_TC_CONGESTION_NOTIFICATION,
7362+ cmd_flags,
7363+ token);
7364+ DPNI_CMD_GET_RX_TC_CONGESTION_NOTIFICATION(cmd, tc_id);
7365+
7366+ /* send command to mc*/
7367+ err = mc_send_command(mc_io, &cmd);
7368+ if (err)
7369+ return err;
7370+
7371+ DPNI_RSP_GET_RX_TC_CONGESTION_NOTIFICATION(cmd, cfg);
7372+
7373+ return 0;
7374+}
7375+
7376+int dpni_set_tx_tc_congestion_notification(struct fsl_mc_io *mc_io,
7377+ uint32_t cmd_flags,
7378+ uint16_t token,
7379+ uint8_t tc_id,
7380+ const struct dpni_congestion_notification_cfg *cfg)
7381+{
7382+ struct mc_command cmd = { 0 };
7383+
7384+ /* prepare command */
7385+ cmd.header = mc_encode_cmd_header(
7386+ DPNI_CMDID_SET_TX_TC_CONGESTION_NOTIFICATION,
7387+ cmd_flags,
7388+ token);
7389+ DPNI_CMD_SET_TX_TC_CONGESTION_NOTIFICATION(cmd, tc_id, cfg);
7390+
7391+ /* send command to mc*/
7392+ return mc_send_command(mc_io, &cmd);
7393+}
7394+
7395+int dpni_get_tx_tc_congestion_notification(struct fsl_mc_io *mc_io,
7396+ uint32_t cmd_flags,
7397+ uint16_t token,
7398+ uint8_t tc_id,
7399+ struct dpni_congestion_notification_cfg *cfg)
7400+{
7401+ struct mc_command cmd = { 0 };
7402+ int err;
7403+
7404+ /* prepare command */
7405+ cmd.header = mc_encode_cmd_header(
7406+ DPNI_CMDID_GET_TX_TC_CONGESTION_NOTIFICATION,
7407+ cmd_flags,
7408+ token);
7409+ DPNI_CMD_GET_TX_TC_CONGESTION_NOTIFICATION(cmd, tc_id);
7410+
7411+ /* send command to mc*/
7412+ err = mc_send_command(mc_io, &cmd);
7413+ if (err)
7414+ return err;
7415+
7416+ DPNI_RSP_GET_TX_TC_CONGESTION_NOTIFICATION(cmd, cfg);
7417+
7418+ return 0;
7419+}
7420+
7421+int dpni_set_tx_conf(struct fsl_mc_io *mc_io,
7422+ uint32_t cmd_flags,
7423+ uint16_t token,
7424+ uint16_t flow_id,
7425+ const struct dpni_tx_conf_cfg *cfg)
7426+{
7427+ struct mc_command cmd = { 0 };
7428+
7429+ /* prepare command */
7430+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF,
7431+ cmd_flags,
7432+ token);
7433+ DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg);
7434+
7435+ /* send command to mc*/
7436+ return mc_send_command(mc_io, &cmd);
7437+}
7438+
7439+int dpni_get_tx_conf(struct fsl_mc_io *mc_io,
7440+ uint32_t cmd_flags,
7441+ uint16_t token,
7442+ uint16_t flow_id,
7443+ struct dpni_tx_conf_attr *attr)
7444+{
7445+ struct mc_command cmd = { 0 };
7446+ int err;
7447+
7448+ /* prepare command */
7449+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_CONF,
7450+ cmd_flags,
7451+ token);
7452+ DPNI_CMD_GET_TX_CONF(cmd, flow_id);
7453+
7454+ /* send command to mc*/
7455+ err = mc_send_command(mc_io, &cmd);
7456+ if (err)
7457+ return err;
7458+
7459+ DPNI_RSP_GET_TX_CONF(cmd, attr);
7460+
7461+ return 0;
7462+}
7463+
7464+int dpni_set_tx_conf_congestion_notification(struct fsl_mc_io *mc_io,
7465+ uint32_t cmd_flags,
7466+ uint16_t token,
7467+ uint16_t flow_id,
7468+ const struct dpni_congestion_notification_cfg *cfg)
7469+{
7470+ struct mc_command cmd = { 0 };
7471+
7472+ /* prepare command */
7473+ cmd.header = mc_encode_cmd_header(
7474+ DPNI_CMDID_SET_TX_CONF_CONGESTION_NOTIFICATION,
7475+ cmd_flags,
7476+ token);
7477+ DPNI_CMD_SET_TX_CONF_CONGESTION_NOTIFICATION(cmd, flow_id, cfg);
7478+
7479+ /* send command to mc*/
7480+ return mc_send_command(mc_io, &cmd);
7481+}
7482+
7483+int dpni_get_tx_conf_congestion_notification(struct fsl_mc_io *mc_io,
7484+ uint32_t cmd_flags,
7485+ uint16_t token,
7486+ uint16_t flow_id,
7487+ struct dpni_congestion_notification_cfg *cfg)
7488+{
7489+ struct mc_command cmd = { 0 };
7490+ int err;
7491+
7492+ /* prepare command */
7493+ cmd.header = mc_encode_cmd_header(
7494+ DPNI_CMDID_GET_TX_CONF_CONGESTION_NOTIFICATION,
7495+ cmd_flags,
7496+ token);
7497+ DPNI_CMD_GET_TX_CONF_CONGESTION_NOTIFICATION(cmd, flow_id);
7498+
7499+ /* send command to mc*/
7500+ err = mc_send_command(mc_io, &cmd);
7501+ if (err)
7502+ return err;
7503+
7504+ DPNI_RSP_GET_TX_CONF_CONGESTION_NOTIFICATION(cmd, cfg);
7505+
7506+ return 0;
7507+}
7508diff --git a/drivers/net/dpaa2/mc/dprc.c b/drivers/net/dpaa2/mc/dprc.c
7509new file mode 100644
7510index 0000000..75c6a68
7511--- /dev/null
7512+++ b/drivers/net/dpaa2/mc/dprc.c
7513@@ -0,0 +1,786 @@
7514+/* Copyright 2013-2015 Freescale Semiconductor Inc.
7515+ *
7516+ * Redistribution and use in source and binary forms, with or without
7517+ * modification, are permitted provided that the following conditions are met:
7518+ * * Redistributions of source code must retain the above copyright
7519+ * notice, this list of conditions and the following disclaimer.
7520+ * * Redistributions in binary form must reproduce the above copyright
7521+ * notice, this list of conditions and the following disclaimer in the
7522+ * documentation and/or other materials provided with the distribution.
7523+ * * Neither the name of the above-listed copyright holders nor the
7524+ * names of any contributors may be used to endorse or promote products
7525+ * derived from this software without specific prior written permission.
7526+ *
7527+ *
7528+ * ALTERNATIVELY, this software may be distributed under the terms of the
7529+ * GNU General Public License ("GPL") as published by the Free Software
7530+ * Foundation, either version 2 of that License or (at your option) any
7531+ * later version.
7532+ *
7533+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
7534+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
7535+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
7536+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
7537+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
7538+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
7539+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
7540+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
7541+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
7542+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
7543+ * POSSIBILITY OF SUCH DAMAGE.
7544+ */
7545+#include <fsl_mc_sys.h>
7546+#include <fsl_mc_cmd.h>
7547+#include <fsl_dprc.h>
7548+#include <fsl_dprc_cmd.h>
7549+
7550+int dprc_get_container_id(struct fsl_mc_io *mc_io,
7551+ uint32_t cmd_flags,
7552+ int *container_id)
7553+{
7554+ struct mc_command cmd = { 0 };
7555+ int err;
7556+
7557+ /* prepare command */
7558+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONT_ID,
7559+ cmd_flags,
7560+ 0);
7561+
7562+ /* send command to mc*/
7563+ err = mc_send_command(mc_io, &cmd);
7564+ if (err)
7565+ return err;
7566+
7567+ /* retrieve response parameters */
7568+ DPRC_RSP_GET_CONTAINER_ID(cmd, *container_id);
7569+
7570+ return 0;
7571+}
7572+
7573+int dprc_open(struct fsl_mc_io *mc_io,
7574+ uint32_t cmd_flags,
7575+ int container_id,
7576+ uint16_t *token)
7577+{
7578+ struct mc_command cmd = { 0 };
7579+ int err;
7580+
7581+ /* prepare command */
7582+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_OPEN, cmd_flags,
7583+ 0);
7584+ DPRC_CMD_OPEN(cmd, container_id);
7585+
7586+ /* send command to mc*/
7587+ err = mc_send_command(mc_io, &cmd);
7588+ if (err)
7589+ return err;
7590+
7591+ /* retrieve response parameters */
7592+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
7593+
7594+ return 0;
7595+}
7596+
7597+int dprc_close(struct fsl_mc_io *mc_io,
7598+ uint32_t cmd_flags,
7599+ uint16_t token)
7600+{
7601+ struct mc_command cmd = { 0 };
7602+
7603+ /* prepare command */
7604+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLOSE, cmd_flags,
7605+ token);
7606+
7607+ /* send command to mc*/
7608+ return mc_send_command(mc_io, &cmd);
7609+}
7610+
7611+int dprc_create_container(struct fsl_mc_io *mc_io,
7612+ uint32_t cmd_flags,
7613+ uint16_t token,
7614+ struct dprc_cfg *cfg,
7615+ int *child_container_id,
7616+ uint64_t *child_portal_paddr)
7617+{
7618+ struct mc_command cmd = { 0 };
7619+ int err;
7620+
7621+ /* prepare command */
7622+ DPRC_CMD_CREATE_CONTAINER(cmd, cfg);
7623+
7624+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT,
7625+ cmd_flags,
7626+ token);
7627+
7628+ /* send command to mc*/
7629+ err = mc_send_command(mc_io, &cmd);
7630+ if (err)
7631+ return err;
7632+
7633+ /* retrieve response parameters */
7634+ DPRC_RSP_CREATE_CONTAINER(cmd, *child_container_id,
7635+ *child_portal_paddr);
7636+
7637+ return 0;
7638+}
7639+
7640+int dprc_destroy_container(struct fsl_mc_io *mc_io,
7641+ uint32_t cmd_flags,
7642+ uint16_t token,
7643+ int child_container_id)
7644+{
7645+ struct mc_command cmd = { 0 };
7646+
7647+ /* prepare command */
7648+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT,
7649+ cmd_flags,
7650+ token);
7651+ DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id);
7652+
7653+ /* send command to mc*/
7654+ return mc_send_command(mc_io, &cmd);
7655+}
7656+
7657+int dprc_reset_container(struct fsl_mc_io *mc_io,
7658+ uint32_t cmd_flags,
7659+ uint16_t token,
7660+ int child_container_id)
7661+{
7662+ struct mc_command cmd = { 0 };
7663+
7664+ /* prepare command */
7665+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_RESET_CONT,
7666+ cmd_flags,
7667+ token);
7668+ DPRC_CMD_RESET_CONTAINER(cmd, child_container_id);
7669+
7670+ /* send command to mc*/
7671+ return mc_send_command(mc_io, &cmd);
7672+}
7673+
7674+int dprc_get_irq(struct fsl_mc_io *mc_io,
7675+ uint32_t cmd_flags,
7676+ uint16_t token,
7677+ uint8_t irq_index,
7678+ int *type,
7679+ struct dprc_irq_cfg *irq_cfg)
7680+{
7681+ struct mc_command cmd = { 0 };
7682+ int err;
7683+
7684+ /* prepare command */
7685+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ,
7686+ cmd_flags,
7687+ token);
7688+ DPRC_CMD_GET_IRQ(cmd, irq_index);
7689+
7690+ /* send command to mc*/
7691+ err = mc_send_command(mc_io, &cmd);
7692+ if (err)
7693+ return err;
7694+
7695+ /* retrieve response parameters */
7696+ DPRC_RSP_GET_IRQ(cmd, *type, irq_cfg);
7697+
7698+ return 0;
7699+}
7700+
7701+int dprc_set_irq(struct fsl_mc_io *mc_io,
7702+ uint32_t cmd_flags,
7703+ uint16_t token,
7704+ uint8_t irq_index,
7705+ struct dprc_irq_cfg *irq_cfg)
7706+{
7707+ struct mc_command cmd = { 0 };
7708+
7709+ /* prepare command */
7710+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ,
7711+ cmd_flags,
7712+ token);
7713+ DPRC_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
7714+
7715+ /* send command to mc*/
7716+ return mc_send_command(mc_io, &cmd);
7717+}
7718+
7719+int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
7720+ uint32_t cmd_flags,
7721+ uint16_t token,
7722+ uint8_t irq_index,
7723+ uint8_t *en)
7724+{
7725+ struct mc_command cmd = { 0 };
7726+ int err;
7727+
7728+ /* prepare command */
7729+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ_ENABLE,
7730+ cmd_flags,
7731+ token);
7732+ DPRC_CMD_GET_IRQ_ENABLE(cmd, irq_index);
7733+
7734+ /* send command to mc*/
7735+ err = mc_send_command(mc_io, &cmd);
7736+ if (err)
7737+ return err;
7738+
7739+ /* retrieve response parameters */
7740+ DPRC_RSP_GET_IRQ_ENABLE(cmd, *en);
7741+
7742+ return 0;
7743+}
7744+
7745+int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
7746+ uint32_t cmd_flags,
7747+ uint16_t token,
7748+ uint8_t irq_index,
7749+ uint8_t en)
7750+{
7751+ struct mc_command cmd = { 0 };
7752+
7753+ /* prepare command */
7754+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ_ENABLE,
7755+ cmd_flags,
7756+ token);
7757+ DPRC_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
7758+
7759+ /* send command to mc*/
7760+ return mc_send_command(mc_io, &cmd);
7761+}
7762+
7763+int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
7764+ uint32_t cmd_flags,
7765+ uint16_t token,
7766+ uint8_t irq_index,
7767+ uint32_t *mask)
7768+{
7769+ struct mc_command cmd = { 0 };
7770+ int err;
7771+
7772+ /* prepare command */
7773+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ_MASK,
7774+ cmd_flags,
7775+ token);
7776+ DPRC_CMD_GET_IRQ_MASK(cmd, irq_index);
7777+
7778+ /* send command to mc*/
7779+ err = mc_send_command(mc_io, &cmd);
7780+ if (err)
7781+ return err;
7782+
7783+ /* retrieve response parameters */
7784+ DPRC_RSP_GET_IRQ_MASK(cmd, *mask);
7785+
7786+ return 0;
7787+}
7788+
7789+int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
7790+ uint32_t cmd_flags,
7791+ uint16_t token,
7792+ uint8_t irq_index,
7793+ uint32_t mask)
7794+{
7795+ struct mc_command cmd = { 0 };
7796+
7797+ /* prepare command */
7798+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ_MASK,
7799+ cmd_flags,
7800+ token);
7801+ DPRC_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
7802+
7803+ /* send command to mc*/
7804+ return mc_send_command(mc_io, &cmd);
7805+}
7806+
7807+int dprc_get_irq_status(struct fsl_mc_io *mc_io,
7808+ uint32_t cmd_flags,
7809+ uint16_t token,
7810+ uint8_t irq_index,
7811+ uint32_t *status)
7812+{
7813+ struct mc_command cmd = { 0 };
7814+ int err;
7815+
7816+ /* prepare command */
7817+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ_STATUS,
7818+ cmd_flags,
7819+ token);
7820+ DPRC_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
7821+
7822+ /* send command to mc*/
7823+ err = mc_send_command(mc_io, &cmd);
7824+ if (err)
7825+ return err;
7826+
7827+ /* retrieve response parameters */
7828+ DPRC_RSP_GET_IRQ_STATUS(cmd, *status);
7829+
7830+ return 0;
7831+}
7832+
7833+int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
7834+ uint32_t cmd_flags,
7835+ uint16_t token,
7836+ uint8_t irq_index,
7837+ uint32_t status)
7838+{
7839+ struct mc_command cmd = { 0 };
7840+
7841+ /* prepare command */
7842+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLEAR_IRQ_STATUS,
7843+ cmd_flags,
7844+ token);
7845+ DPRC_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
7846+
7847+ /* send command to mc*/
7848+ return mc_send_command(mc_io, &cmd);
7849+}
7850+
7851+int dprc_get_attributes(struct fsl_mc_io *mc_io,
7852+ uint32_t cmd_flags,
7853+ uint16_t token,
7854+ struct dprc_attributes *attr)
7855+{
7856+ struct mc_command cmd = { 0 };
7857+ int err;
7858+
7859+ /* prepare command */
7860+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_ATTR,
7861+ cmd_flags,
7862+ token);
7863+
7864+ /* send command to mc*/
7865+ err = mc_send_command(mc_io, &cmd);
7866+ if (err)
7867+ return err;
7868+
7869+ /* retrieve response parameters */
7870+ DPRC_RSP_GET_ATTRIBUTES(cmd, attr);
7871+
7872+ return 0;
7873+}
7874+
7875+int dprc_set_res_quota(struct fsl_mc_io *mc_io,
7876+ uint32_t cmd_flags,
7877+ uint16_t token,
7878+ int child_container_id,
7879+ char *type,
7880+ uint16_t quota)
7881+{
7882+ struct mc_command cmd = { 0 };
7883+
7884+ /* prepare command */
7885+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_RES_QUOTA,
7886+ cmd_flags,
7887+ token);
7888+ DPRC_CMD_SET_RES_QUOTA(cmd, child_container_id, type, quota);
7889+
7890+ /* send command to mc*/
7891+ return mc_send_command(mc_io, &cmd);
7892+}
7893+
7894+int dprc_get_res_quota(struct fsl_mc_io *mc_io,
7895+ uint32_t cmd_flags,
7896+ uint16_t token,
7897+ int child_container_id,
7898+ char *type,
7899+ uint16_t *quota)
7900+{
7901+ struct mc_command cmd = { 0 };
7902+ int err;
7903+
7904+ /* prepare command */
7905+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_QUOTA,
7906+ cmd_flags,
7907+ token);
7908+ DPRC_CMD_GET_RES_QUOTA(cmd, child_container_id, type);
7909+
7910+ /* send command to mc*/
7911+ err = mc_send_command(mc_io, &cmd);
7912+ if (err)
7913+ return err;
7914+
7915+ /* retrieve response parameters */
7916+ DPRC_RSP_GET_RES_QUOTA(cmd, *quota);
7917+
7918+ return 0;
7919+}
7920+
7921+int dprc_assign(struct fsl_mc_io *mc_io,
7922+ uint32_t cmd_flags,
7923+ uint16_t token,
7924+ int container_id,
7925+ struct dprc_res_req *res_req)
7926+{
7927+ struct mc_command cmd = { 0 };
7928+
7929+ /* prepare command */
7930+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_ASSIGN,
7931+ cmd_flags,
7932+ token);
7933+ DPRC_CMD_ASSIGN(cmd, container_id, res_req);
7934+
7935+ /* send command to mc*/
7936+ return mc_send_command(mc_io, &cmd);
7937+}
7938+
7939+int dprc_unassign(struct fsl_mc_io *mc_io,
7940+ uint32_t cmd_flags,
7941+ uint16_t token,
7942+ int child_container_id,
7943+ struct dprc_res_req *res_req)
7944+{
7945+ struct mc_command cmd = { 0 };
7946+
7947+ /* prepare command */
7948+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_UNASSIGN,
7949+ cmd_flags,
7950+ token);
7951+ DPRC_CMD_UNASSIGN(cmd, child_container_id, res_req);
7952+
7953+ /* send command to mc*/
7954+ return mc_send_command(mc_io, &cmd);
7955+}
7956+
7957+int dprc_get_pool_count(struct fsl_mc_io *mc_io,
7958+ uint32_t cmd_flags,
7959+ uint16_t token,
7960+ int *pool_count)
7961+{
7962+ struct mc_command cmd = { 0 };
7963+ int err;
7964+
7965+ /* prepare command */
7966+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_POOL_COUNT,
7967+ cmd_flags,
7968+ token);
7969+
7970+ /* send command to mc*/
7971+ err = mc_send_command(mc_io, &cmd);
7972+ if (err)
7973+ return err;
7974+
7975+ /* retrieve response parameters */
7976+ DPRC_RSP_GET_POOL_COUNT(cmd, *pool_count);
7977+
7978+ return 0;
7979+}
7980+
7981+int dprc_get_pool(struct fsl_mc_io *mc_io,
7982+ uint32_t cmd_flags,
7983+ uint16_t token,
7984+ int pool_index,
7985+ char *type)
7986+{
7987+ struct mc_command cmd = { 0 };
7988+ int err;
7989+
7990+ /* prepare command */
7991+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_POOL,
7992+ cmd_flags,
7993+ token);
7994+ DPRC_CMD_GET_POOL(cmd, pool_index);
7995+
7996+ /* send command to mc*/
7997+ err = mc_send_command(mc_io, &cmd);
7998+ if (err)
7999+ return err;
8000+
8001+ /* retrieve response parameters */
8002+ DPRC_RSP_GET_POOL(cmd, type);
8003+
8004+ return 0;
8005+}
8006+
8007+int dprc_get_obj_count(struct fsl_mc_io *mc_io,
8008+ uint32_t cmd_flags,
8009+ uint16_t token,
8010+ int *obj_count)
8011+{
8012+ struct mc_command cmd = { 0 };
8013+ int err;
8014+
8015+ /* prepare command */
8016+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_COUNT,
8017+ cmd_flags,
8018+ token);
8019+
8020+ /* send command to mc*/
8021+ err = mc_send_command(mc_io, &cmd);
8022+ if (err)
8023+ return err;
8024+
8025+ /* retrieve response parameters */
8026+ DPRC_RSP_GET_OBJ_COUNT(cmd, *obj_count);
8027+
8028+ return 0;
8029+}
8030+
8031+int dprc_get_obj(struct fsl_mc_io *mc_io,
8032+ uint32_t cmd_flags,
8033+ uint16_t token,
8034+ int obj_index,
8035+ struct dprc_obj_desc *obj_desc)
8036+{
8037+ struct mc_command cmd = { 0 };
8038+ int err;
8039+
8040+ /* prepare command */
8041+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ,
8042+ cmd_flags,
8043+ token);
8044+ DPRC_CMD_GET_OBJ(cmd, obj_index);
8045+
8046+ /* send command to mc*/
8047+ err = mc_send_command(mc_io, &cmd);
8048+ if (err)
8049+ return err;
8050+
8051+ /* retrieve response parameters */
8052+ DPRC_RSP_GET_OBJ(cmd, obj_desc);
8053+
8054+ return 0;
8055+}
8056+
8057+int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
8058+ uint32_t cmd_flags,
8059+ uint16_t token,
8060+ char *obj_type,
8061+ int obj_id,
8062+ struct dprc_obj_desc *obj_desc)
8063+{
8064+ struct mc_command cmd = { 0 };
8065+ int err;
8066+
8067+ /* prepare command */
8068+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_DESC,
8069+ cmd_flags,
8070+ token);
8071+ DPRC_CMD_GET_OBJ_DESC(cmd, obj_type, obj_id);
8072+
8073+ /* send command to mc*/
8074+ err = mc_send_command(mc_io, &cmd);
8075+ if (err)
8076+ return err;
8077+
8078+ /* retrieve response parameters */
8079+ DPRC_RSP_GET_OBJ_DESC(cmd, obj_desc);
8080+
8081+ return 0;
8082+}
8083+
8084+int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
8085+ uint32_t cmd_flags,
8086+ uint16_t token,
8087+ char *obj_type,
8088+ int obj_id,
8089+ uint8_t irq_index,
8090+ struct dprc_irq_cfg *irq_cfg)
8091+{
8092+ struct mc_command cmd = { 0 };
8093+
8094+ /* prepare command */
8095+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_OBJ_IRQ,
8096+ cmd_flags,
8097+ token);
8098+ DPRC_CMD_SET_OBJ_IRQ(cmd,
8099+ obj_type,
8100+ obj_id,
8101+ irq_index,
8102+ irq_cfg);
8103+
8104+ /* send command to mc*/
8105+ return mc_send_command(mc_io, &cmd);
8106+}
8107+
8108+int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
8109+ uint32_t cmd_flags,
8110+ uint16_t token,
8111+ char *obj_type,
8112+ int obj_id,
8113+ uint8_t irq_index,
8114+ int *type,
8115+ struct dprc_irq_cfg *irq_cfg)
8116+{
8117+ struct mc_command cmd = { 0 };
8118+ int err;
8119+
8120+ /* prepare command */
8121+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_IRQ,
8122+ cmd_flags,
8123+ token);
8124+ DPRC_CMD_GET_OBJ_IRQ(cmd, obj_type, obj_id, irq_index);
8125+
8126+ /* send command to mc*/
8127+ err = mc_send_command(mc_io, &cmd);
8128+ if (err)
8129+ return err;
8130+
8131+ /* retrieve response parameters */
8132+ DPRC_RSP_GET_OBJ_IRQ(cmd, *type, irq_cfg);
8133+
8134+ return 0;
8135+}
8136+
8137+int dprc_get_res_count(struct fsl_mc_io *mc_io,
8138+ uint32_t cmd_flags,
8139+ uint16_t token,
8140+ char *type,
8141+ int *res_count)
8142+{
8143+ struct mc_command cmd = { 0 };
8144+ int err;
8145+
8146+ *res_count = 0;
8147+
8148+ /* prepare command */
8149+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_COUNT,
8150+ cmd_flags,
8151+ token);
8152+ DPRC_CMD_GET_RES_COUNT(cmd, type);
8153+
8154+ /* send command to mc*/
8155+ err = mc_send_command(mc_io, &cmd);
8156+ if (err)
8157+ return err;
8158+
8159+ /* retrieve response parameters */
8160+ DPRC_RSP_GET_RES_COUNT(cmd, *res_count);
8161+
8162+ return 0;
8163+}
8164+
8165+int dprc_get_res_ids(struct fsl_mc_io *mc_io,
8166+ uint32_t cmd_flags,
8167+ uint16_t token,
8168+ char *type,
8169+ struct dprc_res_ids_range_desc *range_desc)
8170+{
8171+ struct mc_command cmd = { 0 };
8172+ int err;
8173+
8174+ /* prepare command */
8175+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_IDS,
8176+ cmd_flags,
8177+ token);
8178+ DPRC_CMD_GET_RES_IDS(cmd, range_desc, type);
8179+
8180+ /* send command to mc*/
8181+ err = mc_send_command(mc_io, &cmd);
8182+ if (err)
8183+ return err;
8184+
8185+ /* retrieve response parameters */
8186+ DPRC_RSP_GET_RES_IDS(cmd, range_desc);
8187+
8188+ return 0;
8189+}
8190+
8191+int dprc_get_obj_region(struct fsl_mc_io *mc_io,
8192+ uint32_t cmd_flags,
8193+ uint16_t token,
8194+ char *obj_type,
8195+ int obj_id,
8196+ uint8_t region_index,
8197+ struct dprc_region_desc *region_desc)
8198+{
8199+ struct mc_command cmd = { 0 };
8200+ int err;
8201+
8202+ /* prepare command */
8203+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_REG,
8204+ cmd_flags,
8205+ token);
8206+ DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index);
8207+
8208+ /* send command to mc*/
8209+ err = mc_send_command(mc_io, &cmd);
8210+ if (err)
8211+ return err;
8212+
8213+ /* retrieve response parameters */
8214+ DPRC_RSP_GET_OBJ_REGION(cmd, region_desc);
8215+
8216+ return 0;
8217+}
8218+
8219+int dprc_set_obj_label(struct fsl_mc_io *mc_io,
8220+ uint32_t cmd_flags,
8221+ uint16_t token,
8222+ char *obj_type,
8223+ int obj_id,
8224+ char *label)
8225+{
8226+ struct mc_command cmd = { 0 };
8227+
8228+ /* prepare command */
8229+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_OBJ_LABEL,
8230+ cmd_flags,
8231+ token);
8232+ DPRC_CMD_SET_OBJ_LABEL(cmd, obj_type, obj_id, label);
8233+
8234+ /* send command to mc*/
8235+ return mc_send_command(mc_io, &cmd);
8236+}
8237+
8238+int dprc_connect(struct fsl_mc_io *mc_io,
8239+ uint32_t cmd_flags,
8240+ uint16_t token,
8241+ const struct dprc_endpoint *endpoint1,
8242+ const struct dprc_endpoint *endpoint2,
8243+ const struct dprc_connection_cfg *cfg)
8244+{
8245+ struct mc_command cmd = { 0 };
8246+
8247+ /* prepare command */
8248+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_CONNECT,
8249+ cmd_flags,
8250+ token);
8251+ DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg);
8252+
8253+ /* send command to mc*/
8254+ return mc_send_command(mc_io, &cmd);
8255+}
8256+
8257+int dprc_disconnect(struct fsl_mc_io *mc_io,
8258+ uint32_t cmd_flags,
8259+ uint16_t token,
8260+ const struct dprc_endpoint *endpoint)
8261+{
8262+ struct mc_command cmd = { 0 };
8263+
8264+ /* prepare command */
8265+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_DISCONNECT,
8266+ cmd_flags,
8267+ token);
8268+ DPRC_CMD_DISCONNECT(cmd, endpoint);
8269+
8270+ /* send command to mc*/
8271+ return mc_send_command(mc_io, &cmd);
8272+}
8273+
8274+int dprc_get_connection(struct fsl_mc_io *mc_io,
8275+ uint32_t cmd_flags,
8276+ uint16_t token,
8277+ const struct dprc_endpoint *endpoint1,
8278+ struct dprc_endpoint *endpoint2,
8279+ int *state)
8280+{
8281+ struct mc_command cmd = { 0 };
8282+ int err;
8283+
8284+ /* prepare command */
8285+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONNECTION,
8286+ cmd_flags,
8287+ token);
8288+ DPRC_CMD_GET_CONNECTION(cmd, endpoint1);
8289+
8290+ /* send command to mc*/
8291+ err = mc_send_command(mc_io, &cmd);
8292+ if (err)
8293+ return err;
8294+
8295+ /* retrieve response parameters */
8296+ DPRC_RSP_GET_CONNECTION(cmd, endpoint2, *state);
8297+
8298+ return 0;
8299+}
8300diff --git a/drivers/net/dpaa2/mc/dprtc.c b/drivers/net/dpaa2/mc/dprtc.c
8301new file mode 100644
8302index 0000000..73667af
8303--- /dev/null
8304+++ b/drivers/net/dpaa2/mc/dprtc.c
8305@@ -0,0 +1,509 @@
8306+/* Copyright 2013-2015 Freescale Semiconductor Inc.
8307+ *
8308+ * Redistribution and use in source and binary forms, with or without
8309+ * modification, are permitted provided that the following conditions are met:
8310+ * * Redistributions of source code must retain the above copyright
8311+ * notice, this list of conditions and the following disclaimer.
8312+ * * Redistributions in binary form must reproduce the above copyright
8313+ * notice, this list of conditions and the following disclaimer in the
8314+ * documentation and/or other materials provided with the distribution.
8315+ * * Neither the name of the above-listed copyright holders nor the
8316+ * names of any contributors may be used to endorse or promote products
8317+ * derived from this software without specific prior written permission.
8318+ *
8319+ *
8320+ * ALTERNATIVELY, this software may be distributed under the terms of the
8321+ * GNU General Public License ("GPL") as published by the Free Software
8322+ * Foundation, either version 2 of that License or (at your option) any
8323+ * later version.
8324+ *
8325+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
8326+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
8327+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
8328+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
8329+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
8330+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
8331+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
8332+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
8333+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
8334+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
8335+ * POSSIBILITY OF SUCH DAMAGE.
8336+ */
8337+#include <fsl_mc_sys.h>
8338+#include <fsl_mc_cmd.h>
8339+#include <fsl_dprtc.h>
8340+#include <fsl_dprtc_cmd.h>
8341+
8342+int dprtc_open(struct fsl_mc_io *mc_io,
8343+ uint32_t cmd_flags,
8344+ int dprtc_id,
8345+ uint16_t *token)
8346+{
8347+ struct mc_command cmd = { 0 };
8348+ int err;
8349+
8350+ /* prepare command */
8351+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_OPEN,
8352+ cmd_flags,
8353+ 0);
8354+ DPRTC_CMD_OPEN(cmd, dprtc_id);
8355+
8356+ /* send command to mc*/
8357+ err = mc_send_command(mc_io, &cmd);
8358+ if (err)
8359+ return err;
8360+
8361+ /* retrieve response parameters */
8362+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
8363+
8364+ return err;
8365+}
8366+
8367+int dprtc_close(struct fsl_mc_io *mc_io,
8368+ uint32_t cmd_flags,
8369+ uint16_t token)
8370+{
8371+ struct mc_command cmd = { 0 };
8372+
8373+ /* prepare command */
8374+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CLOSE, cmd_flags,
8375+ token);
8376+
8377+ /* send command to mc*/
8378+ return mc_send_command(mc_io, &cmd);
8379+}
8380+
8381+int dprtc_create(struct fsl_mc_io *mc_io,
8382+ uint32_t cmd_flags,
8383+ const struct dprtc_cfg *cfg,
8384+ uint16_t *token)
8385+{
8386+ struct mc_command cmd = { 0 };
8387+ int err;
8388+
8389+ (void)(cfg); /* unused */
8390+
8391+ /* prepare command */
8392+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CREATE,
8393+ cmd_flags,
8394+ 0);
8395+
8396+ /* send command to mc*/
8397+ err = mc_send_command(mc_io, &cmd);
8398+ if (err)
8399+ return err;
8400+
8401+ /* retrieve response parameters */
8402+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
8403+
8404+ return 0;
8405+}
8406+
8407+int dprtc_destroy(struct fsl_mc_io *mc_io,
8408+ uint32_t cmd_flags,
8409+ uint16_t token)
8410+{
8411+ struct mc_command cmd = { 0 };
8412+
8413+ /* prepare command */
8414+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_DESTROY,
8415+ cmd_flags,
8416+ token);
8417+
8418+ /* send command to mc*/
8419+ return mc_send_command(mc_io, &cmd);
8420+}
8421+
8422+int dprtc_enable(struct fsl_mc_io *mc_io,
8423+ uint32_t cmd_flags,
8424+ uint16_t token)
8425+{
8426+ struct mc_command cmd = { 0 };
8427+
8428+ /* prepare command */
8429+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_ENABLE, cmd_flags,
8430+ token);
8431+
8432+ /* send command to mc*/
8433+ return mc_send_command(mc_io, &cmd);
8434+}
8435+
8436+int dprtc_disable(struct fsl_mc_io *mc_io,
8437+ uint32_t cmd_flags,
8438+ uint16_t token)
8439+{
8440+ struct mc_command cmd = { 0 };
8441+
8442+ /* prepare command */
8443+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_DISABLE,
8444+ cmd_flags,
8445+ token);
8446+
8447+ /* send command to mc*/
8448+ return mc_send_command(mc_io, &cmd);
8449+}
8450+
8451+int dprtc_is_enabled(struct fsl_mc_io *mc_io,
8452+ uint32_t cmd_flags,
8453+ uint16_t token,
8454+ int *en)
8455+{
8456+ struct mc_command cmd = { 0 };
8457+ int err;
8458+ /* prepare command */
8459+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_IS_ENABLED, cmd_flags,
8460+ token);
8461+
8462+ /* send command to mc*/
8463+ err = mc_send_command(mc_io, &cmd);
8464+ if (err)
8465+ return err;
8466+
8467+ /* retrieve response parameters */
8468+ DPRTC_RSP_IS_ENABLED(cmd, *en);
8469+
8470+ return 0;
8471+}
8472+
8473+int dprtc_reset(struct fsl_mc_io *mc_io,
8474+ uint32_t cmd_flags,
8475+ uint16_t token)
8476+{
8477+ struct mc_command cmd = { 0 };
8478+
8479+ /* prepare command */
8480+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_RESET,
8481+ cmd_flags,
8482+ token);
8483+
8484+ /* send command to mc*/
8485+ return mc_send_command(mc_io, &cmd);
8486+}
8487+
8488+int dprtc_set_irq(struct fsl_mc_io *mc_io,
8489+ uint32_t cmd_flags,
8490+ uint16_t token,
8491+ uint8_t irq_index,
8492+ struct dprtc_irq_cfg *irq_cfg)
8493+{
8494+ struct mc_command cmd = { 0 };
8495+
8496+ /* prepare command */
8497+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ,
8498+ cmd_flags,
8499+ token);
8500+
8501+ DPRTC_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
8502+
8503+ /* send command to mc*/
8504+ return mc_send_command(mc_io, &cmd);
8505+}
8506+
8507+int dprtc_get_irq(struct fsl_mc_io *mc_io,
8508+ uint32_t cmd_flags,
8509+ uint16_t token,
8510+ uint8_t irq_index,
8511+ int *type,
8512+ struct dprtc_irq_cfg *irq_cfg)
8513+{
8514+ struct mc_command cmd = { 0 };
8515+ int err;
8516+
8517+ /* prepare command */
8518+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ,
8519+ cmd_flags,
8520+ token);
8521+
8522+ DPRTC_CMD_GET_IRQ(cmd, irq_index);
8523+
8524+ /* send command to mc*/
8525+ err = mc_send_command(mc_io, &cmd);
8526+ if (err)
8527+ return err;
8528+
8529+ /* retrieve response parameters */
8530+ DPRTC_RSP_GET_IRQ(cmd, *type, irq_cfg);
8531+
8532+ return 0;
8533+}
8534+
8535+int dprtc_set_irq_enable(struct fsl_mc_io *mc_io,
8536+ uint32_t cmd_flags,
8537+ uint16_t token,
8538+ uint8_t irq_index,
8539+ uint8_t en)
8540+{
8541+ struct mc_command cmd = { 0 };
8542+
8543+ /* prepare command */
8544+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ_ENABLE,
8545+ cmd_flags,
8546+ token);
8547+
8548+ DPRTC_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
8549+
8550+ /* send command to mc*/
8551+ return mc_send_command(mc_io, &cmd);
8552+}
8553+
8554+int dprtc_get_irq_enable(struct fsl_mc_io *mc_io,
8555+ uint32_t cmd_flags,
8556+ uint16_t token,
8557+ uint8_t irq_index,
8558+ uint8_t *en)
8559+{
8560+ struct mc_command cmd = { 0 };
8561+ int err;
8562+
8563+ /* prepare command */
8564+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_ENABLE,
8565+ cmd_flags,
8566+ token);
8567+
8568+ DPRTC_CMD_GET_IRQ_ENABLE(cmd, irq_index);
8569+
8570+ /* send command to mc*/
8571+ err = mc_send_command(mc_io, &cmd);
8572+ if (err)
8573+ return err;
8574+
8575+ /* retrieve response parameters */
8576+ DPRTC_RSP_GET_IRQ_ENABLE(cmd, *en);
8577+
8578+ return 0;
8579+}
8580+
8581+int dprtc_set_irq_mask(struct fsl_mc_io *mc_io,
8582+ uint32_t cmd_flags,
8583+ uint16_t token,
8584+ uint8_t irq_index,
8585+ uint32_t mask)
8586+{
8587+ struct mc_command cmd = { 0 };
8588+
8589+ /* prepare command */
8590+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ_MASK,
8591+ cmd_flags,
8592+ token);
8593+
8594+ DPRTC_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
8595+
8596+ /* send command to mc*/
8597+ return mc_send_command(mc_io, &cmd);
8598+}
8599+
8600+int dprtc_get_irq_mask(struct fsl_mc_io *mc_io,
8601+ uint32_t cmd_flags,
8602+ uint16_t token,
8603+ uint8_t irq_index,
8604+ uint32_t *mask)
8605+{
8606+ struct mc_command cmd = { 0 };
8607+ int err;
8608+
8609+ /* prepare command */
8610+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_MASK,
8611+ cmd_flags,
8612+ token);
8613+
8614+ DPRTC_CMD_GET_IRQ_MASK(cmd, irq_index);
8615+
8616+ /* send command to mc*/
8617+ err = mc_send_command(mc_io, &cmd);
8618+ if (err)
8619+ return err;
8620+
8621+ /* retrieve response parameters */
8622+ DPRTC_RSP_GET_IRQ_MASK(cmd, *mask);
8623+
8624+ return 0;
8625+}
8626+
8627+int dprtc_get_irq_status(struct fsl_mc_io *mc_io,
8628+ uint32_t cmd_flags,
8629+ uint16_t token,
8630+ uint8_t irq_index,
8631+ uint32_t *status)
8632+{
8633+ struct mc_command cmd = { 0 };
8634+ int err;
8635+
8636+ /* prepare command */
8637+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_STATUS,
8638+ cmd_flags,
8639+ token);
8640+
8641+ DPRTC_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
8642+
8643+ /* send command to mc*/
8644+ err = mc_send_command(mc_io, &cmd);
8645+ if (err)
8646+ return err;
8647+
8648+ /* retrieve response parameters */
8649+ DPRTC_RSP_GET_IRQ_STATUS(cmd, *status);
8650+
8651+ return 0;
8652+}
8653+
8654+int dprtc_clear_irq_status(struct fsl_mc_io *mc_io,
8655+ uint32_t cmd_flags,
8656+ uint16_t token,
8657+ uint8_t irq_index,
8658+ uint32_t status)
8659+{
8660+ struct mc_command cmd = { 0 };
8661+
8662+ /* prepare command */
8663+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CLEAR_IRQ_STATUS,
8664+ cmd_flags,
8665+ token);
8666+
8667+ DPRTC_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
8668+
8669+ /* send command to mc*/
8670+ return mc_send_command(mc_io, &cmd);
8671+}
8672+
8673+int dprtc_get_attributes(struct fsl_mc_io *mc_io,
8674+ uint32_t cmd_flags,
8675+ uint16_t token,
8676+ struct dprtc_attr *attr)
8677+{
8678+ struct mc_command cmd = { 0 };
8679+ int err;
8680+
8681+ /* prepare command */
8682+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_ATTR,
8683+ cmd_flags,
8684+ token);
8685+
8686+ /* send command to mc*/
8687+ err = mc_send_command(mc_io, &cmd);
8688+ if (err)
8689+ return err;
8690+
8691+ /* retrieve response parameters */
8692+ DPRTC_RSP_GET_ATTRIBUTES(cmd, attr);
8693+
8694+ return 0;
8695+}
8696+
8697+int dprtc_set_clock_offset(struct fsl_mc_io *mc_io,
8698+ uint32_t cmd_flags,
8699+ uint16_t token,
8700+ int64_t offset)
8701+{
8702+ struct mc_command cmd = { 0 };
8703+
8704+ /* prepare command */
8705+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_CLOCK_OFFSET,
8706+ cmd_flags,
8707+ token);
8708+
8709+ DPRTC_CMD_SET_CLOCK_OFFSET(cmd, offset);
8710+
8711+ /* send command to mc*/
8712+ return mc_send_command(mc_io, &cmd);
8713+}
8714+
8715+int dprtc_set_freq_compensation(struct fsl_mc_io *mc_io,
8716+ uint32_t cmd_flags,
8717+ uint16_t token,
8718+ uint32_t freq_compensation)
8719+{
8720+ struct mc_command cmd = { 0 };
8721+
8722+ /* prepare command */
8723+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_FREQ_COMPENSATION,
8724+ cmd_flags,
8725+ token);
8726+
8727+ DPRTC_CMD_SET_FREQ_COMPENSATION(cmd, freq_compensation);
8728+
8729+ /* send command to mc*/
8730+ return mc_send_command(mc_io, &cmd);
8731+}
8732+
8733+int dprtc_get_freq_compensation(struct fsl_mc_io *mc_io,
8734+ uint32_t cmd_flags,
8735+ uint16_t token,
8736+ uint32_t *freq_compensation)
8737+{
8738+ struct mc_command cmd = { 0 };
8739+ int err;
8740+
8741+ /* prepare command */
8742+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_FREQ_COMPENSATION,
8743+ cmd_flags,
8744+ token);
8745+
8746+ /* send command to mc*/
8747+ err = mc_send_command(mc_io, &cmd);
8748+ if (err)
8749+ return err;
8750+
8751+ /* retrieve response parameters */
8752+ DPRTC_RSP_GET_FREQ_COMPENSATION(cmd, *freq_compensation);
8753+
8754+ return 0;
8755+}
8756+
8757+int dprtc_get_time(struct fsl_mc_io *mc_io,
8758+ uint32_t cmd_flags,
8759+ uint16_t token,
8760+ uint64_t *time)
8761+{
8762+ struct mc_command cmd = { 0 };
8763+ int err;
8764+
8765+ /* prepare command */
8766+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_TIME,
8767+ cmd_flags,
8768+ token);
8769+
8770+ /* send command to mc*/
8771+ err = mc_send_command(mc_io, &cmd);
8772+ if (err)
8773+ return err;
8774+
8775+ /* retrieve response parameters */
8776+ DPRTC_RSP_GET_TIME(cmd, *time);
8777+
8778+ return 0;
8779+}
8780+
8781+int dprtc_set_time(struct fsl_mc_io *mc_io,
8782+ uint32_t cmd_flags,
8783+ uint16_t token,
8784+ uint64_t time)
8785+{
8786+ struct mc_command cmd = { 0 };
8787+
8788+ /* prepare command */
8789+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_TIME,
8790+ cmd_flags,
8791+ token);
8792+
8793+ DPRTC_CMD_SET_TIME(cmd, time);
8794+
8795+ /* send command to mc*/
8796+ return mc_send_command(mc_io, &cmd);
8797+}
8798+
8799+int dprtc_set_alarm(struct fsl_mc_io *mc_io,
8800+ uint32_t cmd_flags,
8801+ uint16_t token, uint64_t time)
8802+{
8803+ struct mc_command cmd = { 0 };
8804+
8805+ /* prepare command */
8806+ cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_ALARM,
8807+ cmd_flags,
8808+ token);
8809+
8810+ DPRTC_CMD_SET_ALARM(cmd, time);
8811+
8812+ /* send command to mc*/
8813+ return mc_send_command(mc_io, &cmd);
8814+}
8815diff --git a/drivers/net/dpaa2/mc/dpseci.c b/drivers/net/dpaa2/mc/dpseci.c
8816new file mode 100644
8817index 0000000..a4b932a
8818--- /dev/null
8819+++ b/drivers/net/dpaa2/mc/dpseci.c
8820@@ -0,0 +1,502 @@
8821+/* Copyright 2013-2015 Freescale Semiconductor Inc.
8822+ *
8823+ * Redistribution and use in source and binary forms, with or without
8824+ * modification, are permitted provided that the following conditions are met:
8825+ * * Redistributions of source code must retain the above copyright
8826+ * notice, this list of conditions and the following disclaimer.
8827+ * * Redistributions in binary form must reproduce the above copyright
8828+ * notice, this list of conditions and the following disclaimer in the
8829+ * documentation and/or other materials provided with the distribution.
8830+ * * Neither the name of the above-listed copyright holders nor the
8831+ * names of any contributors may be used to endorse or promote products
8832+ * derived from this software without specific prior written permission.
8833+ *
8834+ *
8835+ * ALTERNATIVELY, this software may be distributed under the terms of the
8836+ * GNU General Public License ("GPL") as published by the Free Software
8837+ * Foundation, either version 2 of that License or (at your option) any
8838+ * later version.
8839+ *
8840+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
8841+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
8842+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
8843+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
8844+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
8845+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
8846+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
8847+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
8848+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
8849+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
8850+ * POSSIBILITY OF SUCH DAMAGE.
8851+ */
8852+#include <fsl_mc_sys.h>
8853+#include <fsl_mc_cmd.h>
8854+#include <fsl_dpseci.h>
8855+#include <fsl_dpseci_cmd.h>
8856+
8857+int dpseci_open(struct fsl_mc_io *mc_io,
8858+ uint32_t cmd_flags,
8859+ int dpseci_id,
8860+ uint16_t *token)
8861+{
8862+ struct mc_command cmd = { 0 };
8863+ int err;
8864+
8865+ /* prepare command */
8866+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_OPEN,
8867+ cmd_flags,
8868+ 0);
8869+ DPSECI_CMD_OPEN(cmd, dpseci_id);
8870+
8871+ /* send command to mc*/
8872+ err = mc_send_command(mc_io, &cmd);
8873+ if (err)
8874+ return err;
8875+
8876+ /* retrieve response parameters */
8877+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
8878+
8879+ return 0;
8880+}
8881+
8882+int dpseci_close(struct fsl_mc_io *mc_io,
8883+ uint32_t cmd_flags,
8884+ uint16_t token)
8885+{
8886+ struct mc_command cmd = { 0 };
8887+
8888+ /* prepare command */
8889+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CLOSE,
8890+ cmd_flags,
8891+ token);
8892+
8893+ /* send command to mc*/
8894+ return mc_send_command(mc_io, &cmd);
8895+}
8896+
8897+int dpseci_create(struct fsl_mc_io *mc_io,
8898+ uint32_t cmd_flags,
8899+ const struct dpseci_cfg *cfg,
8900+ uint16_t *token)
8901+{
8902+ struct mc_command cmd = { 0 };
8903+ int err;
8904+
8905+ /* prepare command */
8906+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CREATE,
8907+ cmd_flags,
8908+ 0);
8909+ DPSECI_CMD_CREATE(cmd, cfg);
8910+
8911+ /* send command to mc*/
8912+ err = mc_send_command(mc_io, &cmd);
8913+ if (err)
8914+ return err;
8915+
8916+ /* retrieve response parameters */
8917+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
8918+
8919+ return 0;
8920+}
8921+
8922+int dpseci_destroy(struct fsl_mc_io *mc_io,
8923+ uint32_t cmd_flags,
8924+ uint16_t token)
8925+{
8926+ struct mc_command cmd = { 0 };
8927+
8928+ /* prepare command */
8929+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_DESTROY,
8930+ cmd_flags,
8931+ token);
8932+
8933+ /* send command to mc*/
8934+ return mc_send_command(mc_io, &cmd);
8935+}
8936+
8937+int dpseci_enable(struct fsl_mc_io *mc_io,
8938+ uint32_t cmd_flags,
8939+ uint16_t token)
8940+{
8941+ struct mc_command cmd = { 0 };
8942+
8943+ /* prepare command */
8944+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_ENABLE,
8945+ cmd_flags,
8946+ token);
8947+
8948+ /* send command to mc*/
8949+ return mc_send_command(mc_io, &cmd);
8950+}
8951+
8952+int dpseci_disable(struct fsl_mc_io *mc_io,
8953+ uint32_t cmd_flags,
8954+ uint16_t token)
8955+{
8956+ struct mc_command cmd = { 0 };
8957+
8958+ /* prepare command */
8959+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_DISABLE,
8960+ cmd_flags,
8961+ token);
8962+
8963+ /* send command to mc*/
8964+ return mc_send_command(mc_io, &cmd);
8965+}
8966+
8967+int dpseci_is_enabled(struct fsl_mc_io *mc_io,
8968+ uint32_t cmd_flags,
8969+ uint16_t token,
8970+ int *en)
8971+{
8972+ struct mc_command cmd = { 0 };
8973+ int err;
8974+ /* prepare command */
8975+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_IS_ENABLED,
8976+ cmd_flags,
8977+ token);
8978+
8979+ /* send command to mc*/
8980+ err = mc_send_command(mc_io, &cmd);
8981+ if (err)
8982+ return err;
8983+
8984+ /* retrieve response parameters */
8985+ DPSECI_RSP_IS_ENABLED(cmd, *en);
8986+
8987+ return 0;
8988+}
8989+
8990+int dpseci_reset(struct fsl_mc_io *mc_io,
8991+ uint32_t cmd_flags,
8992+ uint16_t token)
8993+{
8994+ struct mc_command cmd = { 0 };
8995+
8996+ /* prepare command */
8997+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_RESET,
8998+ cmd_flags,
8999+ token);
9000+
9001+ /* send command to mc*/
9002+ return mc_send_command(mc_io, &cmd);
9003+}
9004+
9005+int dpseci_get_irq(struct fsl_mc_io *mc_io,
9006+ uint32_t cmd_flags,
9007+ uint16_t token,
9008+ uint8_t irq_index,
9009+ int *type,
9010+ struct dpseci_irq_cfg *irq_cfg)
9011+{
9012+ struct mc_command cmd = { 0 };
9013+ int err;
9014+
9015+ /* prepare command */
9016+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ,
9017+ cmd_flags,
9018+ token);
9019+ DPSECI_CMD_GET_IRQ(cmd, irq_index);
9020+
9021+ /* send command to mc*/
9022+ err = mc_send_command(mc_io, &cmd);
9023+ if (err)
9024+ return err;
9025+
9026+ /* retrieve response parameters */
9027+ DPSECI_RSP_GET_IRQ(cmd, *type, irq_cfg);
9028+
9029+ return 0;
9030+}
9031+
9032+int dpseci_set_irq(struct fsl_mc_io *mc_io,
9033+ uint32_t cmd_flags,
9034+ uint16_t token,
9035+ uint8_t irq_index,
9036+ struct dpseci_irq_cfg *irq_cfg)
9037+{
9038+ struct mc_command cmd = { 0 };
9039+
9040+ /* prepare command */
9041+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ,
9042+ cmd_flags,
9043+ token);
9044+ DPSECI_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
9045+
9046+ /* send command to mc*/
9047+ return mc_send_command(mc_io, &cmd);
9048+}
9049+
9050+int dpseci_get_irq_enable(struct fsl_mc_io *mc_io,
9051+ uint32_t cmd_flags,
9052+ uint16_t token,
9053+ uint8_t irq_index,
9054+ uint8_t *en)
9055+{
9056+ struct mc_command cmd = { 0 };
9057+ int err;
9058+
9059+ /* prepare command */
9060+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_ENABLE,
9061+ cmd_flags,
9062+ token);
9063+ DPSECI_CMD_GET_IRQ_ENABLE(cmd, irq_index);
9064+
9065+ /* send command to mc*/
9066+ err = mc_send_command(mc_io, &cmd);
9067+ if (err)
9068+ return err;
9069+
9070+ /* retrieve response parameters */
9071+ DPSECI_RSP_GET_IRQ_ENABLE(cmd, *en);
9072+
9073+ return 0;
9074+}
9075+
9076+int dpseci_set_irq_enable(struct fsl_mc_io *mc_io,
9077+ uint32_t cmd_flags,
9078+ uint16_t token,
9079+ uint8_t irq_index,
9080+ uint8_t en)
9081+{
9082+ struct mc_command cmd = { 0 };
9083+
9084+ /* prepare command */
9085+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_ENABLE,
9086+ cmd_flags,
9087+ token);
9088+ DPSECI_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
9089+
9090+ /* send command to mc*/
9091+ return mc_send_command(mc_io, &cmd);
9092+}
9093+
9094+int dpseci_get_irq_mask(struct fsl_mc_io *mc_io,
9095+ uint32_t cmd_flags,
9096+ uint16_t token,
9097+ uint8_t irq_index,
9098+ uint32_t *mask)
9099+{
9100+ struct mc_command cmd = { 0 };
9101+ int err;
9102+
9103+ /* prepare command */
9104+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_MASK,
9105+ cmd_flags,
9106+ token);
9107+ DPSECI_CMD_GET_IRQ_MASK(cmd, irq_index);
9108+
9109+ /* send command to mc*/
9110+ err = mc_send_command(mc_io, &cmd);
9111+ if (err)
9112+ return err;
9113+
9114+ /* retrieve response parameters */
9115+ DPSECI_RSP_GET_IRQ_MASK(cmd, *mask);
9116+
9117+ return 0;
9118+}
9119+
9120+int dpseci_set_irq_mask(struct fsl_mc_io *mc_io,
9121+ uint32_t cmd_flags,
9122+ uint16_t token,
9123+ uint8_t irq_index,
9124+ uint32_t mask)
9125+{
9126+ struct mc_command cmd = { 0 };
9127+
9128+ /* prepare command */
9129+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_MASK,
9130+ cmd_flags,
9131+ token);
9132+ DPSECI_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
9133+
9134+ /* send command to mc*/
9135+ return mc_send_command(mc_io, &cmd);
9136+}
9137+
9138+int dpseci_get_irq_status(struct fsl_mc_io *mc_io,
9139+ uint32_t cmd_flags,
9140+ uint16_t token,
9141+ uint8_t irq_index,
9142+ uint32_t *status)
9143+{
9144+ struct mc_command cmd = { 0 };
9145+ int err;
9146+
9147+ /* prepare command */
9148+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_STATUS,
9149+ cmd_flags,
9150+ token);
9151+ DPSECI_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
9152+
9153+ /* send command to mc*/
9154+ err = mc_send_command(mc_io, &cmd);
9155+ if (err)
9156+ return err;
9157+
9158+ /* retrieve response parameters */
9159+ DPSECI_RSP_GET_IRQ_STATUS(cmd, *status);
9160+
9161+ return 0;
9162+}
9163+
9164+int dpseci_clear_irq_status(struct fsl_mc_io *mc_io,
9165+ uint32_t cmd_flags,
9166+ uint16_t token,
9167+ uint8_t irq_index,
9168+ uint32_t status)
9169+{
9170+ struct mc_command cmd = { 0 };
9171+
9172+ /* prepare command */
9173+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CLEAR_IRQ_STATUS,
9174+ cmd_flags,
9175+ token);
9176+ DPSECI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
9177+
9178+ /* send command to mc*/
9179+ return mc_send_command(mc_io, &cmd);
9180+}
9181+
9182+int dpseci_get_attributes(struct fsl_mc_io *mc_io,
9183+ uint32_t cmd_flags,
9184+ uint16_t token,
9185+ struct dpseci_attr *attr)
9186+{
9187+ struct mc_command cmd = { 0 };
9188+ int err;
9189+
9190+ /* prepare command */
9191+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_ATTR,
9192+ cmd_flags,
9193+ token);
9194+
9195+ /* send command to mc*/
9196+ err = mc_send_command(mc_io, &cmd);
9197+ if (err)
9198+ return err;
9199+
9200+ /* retrieve response parameters */
9201+ DPSECI_RSP_GET_ATTR(cmd, attr);
9202+
9203+ return 0;
9204+}
9205+
9206+int dpseci_set_rx_queue(struct fsl_mc_io *mc_io,
9207+ uint32_t cmd_flags,
9208+ uint16_t token,
9209+ uint8_t queue,
9210+ const struct dpseci_rx_queue_cfg *cfg)
9211+{
9212+ struct mc_command cmd = { 0 };
9213+
9214+ /* prepare command */
9215+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_RX_QUEUE,
9216+ cmd_flags,
9217+ token);
9218+ DPSECI_CMD_SET_RX_QUEUE(cmd, queue, cfg);
9219+
9220+ /* send command to mc*/
9221+ return mc_send_command(mc_io, &cmd);
9222+}
9223+
9224+int dpseci_get_rx_queue(struct fsl_mc_io *mc_io,
9225+ uint32_t cmd_flags,
9226+ uint16_t token,
9227+ uint8_t queue,
9228+ struct dpseci_rx_queue_attr *attr)
9229+{
9230+ struct mc_command cmd = { 0 };
9231+ int err;
9232+
9233+ /* prepare command */
9234+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_RX_QUEUE,
9235+ cmd_flags,
9236+ token);
9237+ DPSECI_CMD_GET_RX_QUEUE(cmd, queue);
9238+
9239+ /* send command to mc*/
9240+ err = mc_send_command(mc_io, &cmd);
9241+ if (err)
9242+ return err;
9243+
9244+ /* retrieve response parameters */
9245+ DPSECI_RSP_GET_RX_QUEUE(cmd, attr);
9246+
9247+ return 0;
9248+}
9249+
9250+int dpseci_get_tx_queue(struct fsl_mc_io *mc_io,
9251+ uint32_t cmd_flags,
9252+ uint16_t token,
9253+ uint8_t queue,
9254+ struct dpseci_tx_queue_attr *attr)
9255+{
9256+ struct mc_command cmd = { 0 };
9257+ int err;
9258+
9259+ /* prepare command */
9260+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_TX_QUEUE,
9261+ cmd_flags,
9262+ token);
9263+ DPSECI_CMD_GET_TX_QUEUE(cmd, queue);
9264+
9265+ /* send command to mc*/
9266+ err = mc_send_command(mc_io, &cmd);
9267+ if (err)
9268+ return err;
9269+
9270+ /* retrieve response parameters */
9271+ DPSECI_RSP_GET_TX_QUEUE(cmd, attr);
9272+
9273+ return 0;
9274+}
9275+
9276+int dpseci_get_sec_attr(struct fsl_mc_io *mc_io,
9277+ uint32_t cmd_flags,
9278+ uint16_t token,
9279+ struct dpseci_sec_attr *attr)
9280+{
9281+ struct mc_command cmd = { 0 };
9282+ int err;
9283+
9284+ /* prepare command */
9285+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_SEC_ATTR,
9286+ cmd_flags,
9287+ token);
9288+
9289+ /* send command to mc*/
9290+ err = mc_send_command(mc_io, &cmd);
9291+ if (err)
9292+ return err;
9293+
9294+ /* retrieve response parameters */
9295+ DPSECI_RSP_GET_SEC_ATTR(cmd, attr);
9296+
9297+ return 0;
9298+}
9299+
9300+int dpseci_get_sec_counters(struct fsl_mc_io *mc_io,
9301+ uint32_t cmd_flags,
9302+ uint16_t token,
9303+ struct dpseci_sec_counters *counters)
9304+{
9305+ struct mc_command cmd = { 0 };
9306+ int err;
9307+
9308+ /* prepare command */
9309+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_SEC_COUNTERS,
9310+ cmd_flags,
9311+ token);
9312+
9313+ /* send command to mc*/
9314+ err = mc_send_command(mc_io, &cmd);
9315+ if (err)
9316+ return err;
9317+
9318+ /* retrieve response parameters */
9319+ DPSECI_RSP_GET_SEC_COUNTERS(cmd, counters);
9320+
9321+ return 0;
9322+}
9323diff --git a/drivers/net/dpaa2/mc/dpsw.c b/drivers/net/dpaa2/mc/dpsw.c
9324new file mode 100644
9325index 0000000..2034b55
9326--- /dev/null
9327+++ b/drivers/net/dpaa2/mc/dpsw.c
9328@@ -0,0 +1,1639 @@
9329+/* Copyright 2013-2015 Freescale Semiconductor Inc.
9330+ *
9331+ * Redistribution and use in source and binary forms, with or without
9332+ * modification, are permitted provided that the following conditions are met:
9333+ * * Redistributions of source code must retain the above copyright
9334+ * notice, this list of conditions and the following disclaimer.
9335+ * * Redistributions in binary form must reproduce the above copyright
9336+ * notice, this list of conditions and the following disclaimer in the
9337+ * documentation and/or other materials provided with the distribution.
9338+ * * Neither the name of the above-listed copyright holders nor the
9339+ * names of any contributors may be used to endorse or promote products
9340+ * derived from this software without specific prior written permission.
9341+ *
9342+ *
9343+ * ALTERNATIVELY, this software may be distributed under the terms of the
9344+ * GNU General Public License ("GPL") as published by the Free Software
9345+ * Foundation, either version 2 of that License or (at your option) any
9346+ * later version.
9347+ *
9348+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
9349+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
9350+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9351+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
9352+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
9353+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
9354+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
9355+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
9356+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
9357+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
9358+ * POSSIBILITY OF SUCH DAMAGE.
9359+ */
9360+#include <fsl_mc_sys.h>
9361+#include <fsl_mc_cmd.h>
9362+#include <fsl_dpsw.h>
9363+#include <fsl_dpsw_cmd.h>
9364+
9365+/* internal functions */
9366+static void build_if_id_bitmap(const uint16_t *if_id,
9367+ const uint16_t num_ifs,
9368+ struct mc_command *cmd,
9369+ int start_param)
9370+{
9371+ int i;
9372+
9373+ for (i = 0; (i < num_ifs) && (i < DPSW_MAX_IF); i++)
9374+ cmd->params[start_param + (if_id[i] / 64)] |= mc_enc(
9375+ (if_id[i] % 64), 1, 1);
9376+}
9377+
9378+static int read_if_id_bitmap(uint16_t *if_id,
9379+ uint16_t *num_ifs,
9380+ struct mc_command *cmd,
9381+ int start_param)
9382+{
9383+ int bitmap[DPSW_MAX_IF] = { 0 };
9384+ int i, j = 0;
9385+ int count = 0;
9386+
9387+ for (i = 0; i < DPSW_MAX_IF; i++) {
9388+ bitmap[i] = (int)mc_dec(cmd->params[start_param + i / 64],
9389+ i % 64, 1);
9390+ count += bitmap[i];
9391+ }
9392+
9393+ *num_ifs = (uint16_t)count;
9394+
9395+ for (i = 0; (i < DPSW_MAX_IF) && (j < count); i++) {
9396+ if (bitmap[i]) {
9397+ if_id[j] = (uint16_t)i;
9398+ j++;
9399+ }
9400+ }
9401+
9402+ return 0;
9403+}
9404+
9405+/* DPSW APIs */
9406+int dpsw_open(struct fsl_mc_io *mc_io,
9407+ uint32_t cmd_flags,
9408+ int dpsw_id,
9409+ uint16_t *token)
9410+{
9411+ struct mc_command cmd = { 0 };
9412+ int err;
9413+
9414+ /* prepare command */
9415+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_OPEN,
9416+ cmd_flags,
9417+ 0);
9418+ DPSW_CMD_OPEN(cmd, dpsw_id);
9419+
9420+ /* send command to mc*/
9421+ err = mc_send_command(mc_io, &cmd);
9422+ if (err)
9423+ return err;
9424+
9425+ /* retrieve response parameters */
9426+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
9427+
9428+ return 0;
9429+}
9430+
9431+int dpsw_close(struct fsl_mc_io *mc_io,
9432+ uint32_t cmd_flags,
9433+ uint16_t token)
9434+{
9435+ struct mc_command cmd = { 0 };
9436+
9437+ /* prepare command */
9438+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CLOSE,
9439+ cmd_flags,
9440+ token);
9441+
9442+ /* send command to mc*/
9443+ return mc_send_command(mc_io, &cmd);
9444+}
9445+
9446+int dpsw_create(struct fsl_mc_io *mc_io,
9447+ uint32_t cmd_flags,
9448+ const struct dpsw_cfg *cfg,
9449+ uint16_t *token)
9450+{
9451+ struct mc_command cmd = { 0 };
9452+ int err;
9453+
9454+ /* prepare command */
9455+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CREATE,
9456+ cmd_flags,
9457+ 0);
9458+ DPSW_CMD_CREATE(cmd, cfg);
9459+
9460+ /* send command to mc*/
9461+ err = mc_send_command(mc_io, &cmd);
9462+ if (err)
9463+ return err;
9464+
9465+ /* retrieve response parameters */
9466+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
9467+
9468+ return 0;
9469+}
9470+
9471+int dpsw_destroy(struct fsl_mc_io *mc_io,
9472+ uint32_t cmd_flags,
9473+ uint16_t token)
9474+{
9475+ struct mc_command cmd = { 0 };
9476+
9477+ /* prepare command */
9478+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_DESTROY,
9479+ cmd_flags,
9480+ token);
9481+
9482+ /* send command to mc*/
9483+ return mc_send_command(mc_io, &cmd);
9484+}
9485+
9486+int dpsw_enable(struct fsl_mc_io *mc_io,
9487+ uint32_t cmd_flags,
9488+ uint16_t token)
9489+{
9490+ struct mc_command cmd = { 0 };
9491+
9492+ /* prepare command */
9493+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ENABLE,
9494+ cmd_flags,
9495+ token);
9496+
9497+ /* send command to mc*/
9498+ return mc_send_command(mc_io, &cmd);
9499+}
9500+
9501+int dpsw_disable(struct fsl_mc_io *mc_io,
9502+ uint32_t cmd_flags,
9503+ uint16_t token)
9504+{
9505+ struct mc_command cmd = { 0 };
9506+
9507+ /* prepare command */
9508+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_DISABLE,
9509+ cmd_flags,
9510+ token);
9511+
9512+ /* send command to mc*/
9513+ return mc_send_command(mc_io, &cmd);
9514+}
9515+
9516+int dpsw_is_enabled(struct fsl_mc_io *mc_io,
9517+ uint32_t cmd_flags,
9518+ uint16_t token,
9519+ int *en)
9520+{
9521+ struct mc_command cmd = { 0 };
9522+ int err;
9523+
9524+ /* prepare command */
9525+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IS_ENABLED, cmd_flags,
9526+ token);
9527+
9528+ /* send command to mc*/
9529+ err = mc_send_command(mc_io, &cmd);
9530+ if (err)
9531+ return err;
9532+
9533+ /* retrieve response parameters */
9534+ DPSW_RSP_IS_ENABLED(cmd, *en);
9535+
9536+ return 0;
9537+}
9538+
9539+int dpsw_reset(struct fsl_mc_io *mc_io,
9540+ uint32_t cmd_flags,
9541+ uint16_t token)
9542+{
9543+ struct mc_command cmd = { 0 };
9544+
9545+ /* prepare command */
9546+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_RESET,
9547+ cmd_flags,
9548+ token);
9549+
9550+ /* send command to mc*/
9551+ return mc_send_command(mc_io, &cmd);
9552+}
9553+
9554+int dpsw_set_irq(struct fsl_mc_io *mc_io,
9555+ uint32_t cmd_flags,
9556+ uint16_t token,
9557+ uint8_t irq_index,
9558+ struct dpsw_irq_cfg *irq_cfg)
9559+{
9560+ struct mc_command cmd = { 0 };
9561+
9562+ /* prepare command */
9563+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_IRQ,
9564+ cmd_flags,
9565+ token);
9566+ DPSW_CMD_SET_IRQ(cmd, irq_index, irq_cfg);
9567+
9568+ /* send command to mc*/
9569+ return mc_send_command(mc_io, &cmd);
9570+}
9571+
9572+int dpsw_get_irq(struct fsl_mc_io *mc_io,
9573+ uint32_t cmd_flags,
9574+ uint16_t token,
9575+ uint8_t irq_index,
9576+ int *type,
9577+ struct dpsw_irq_cfg *irq_cfg)
9578+{
9579+ struct mc_command cmd = { 0 };
9580+ int err;
9581+
9582+ /* prepare command */
9583+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_IRQ,
9584+ cmd_flags,
9585+ token);
9586+ DPSW_CMD_GET_IRQ(cmd, irq_index);
9587+
9588+ /* send command to mc*/
9589+ err = mc_send_command(mc_io, &cmd);
9590+ if (err)
9591+ return err;
9592+
9593+ /* retrieve response parameters */
9594+ DPSW_RSP_GET_IRQ(cmd, *type, irq_cfg);
9595+
9596+ return 0;
9597+}
9598+
9599+int dpsw_set_irq_enable(struct fsl_mc_io *mc_io,
9600+ uint32_t cmd_flags,
9601+ uint16_t token,
9602+ uint8_t irq_index,
9603+ uint8_t en)
9604+{
9605+ struct mc_command cmd = { 0 };
9606+
9607+ /* prepare command */
9608+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_IRQ_ENABLE,
9609+ cmd_flags,
9610+ token);
9611+ DPSW_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);
9612+
9613+ /* send command to mc*/
9614+ return mc_send_command(mc_io, &cmd);
9615+}
9616+
9617+int dpsw_get_irq_enable(struct fsl_mc_io *mc_io,
9618+ uint32_t cmd_flags,
9619+ uint16_t token,
9620+ uint8_t irq_index,
9621+ uint8_t *en)
9622+{
9623+ struct mc_command cmd = { 0 };
9624+ int err;
9625+
9626+ /* prepare command */
9627+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_IRQ_ENABLE,
9628+ cmd_flags,
9629+ token);
9630+ DPSW_CMD_GET_IRQ_ENABLE(cmd, irq_index);
9631+
9632+ /* send command to mc*/
9633+ err = mc_send_command(mc_io, &cmd);
9634+ if (err)
9635+ return err;
9636+
9637+ /* retrieve response parameters */
9638+ DPSW_RSP_GET_IRQ_ENABLE(cmd, *en);
9639+
9640+ return 0;
9641+}
9642+
9643+int dpsw_set_irq_mask(struct fsl_mc_io *mc_io,
9644+ uint32_t cmd_flags,
9645+ uint16_t token,
9646+ uint8_t irq_index,
9647+ uint32_t mask)
9648+{
9649+ struct mc_command cmd = { 0 };
9650+
9651+ /* prepare command */
9652+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_IRQ_MASK,
9653+ cmd_flags,
9654+ token);
9655+ DPSW_CMD_SET_IRQ_MASK(cmd, irq_index, mask);
9656+
9657+ /* send command to mc*/
9658+ return mc_send_command(mc_io, &cmd);
9659+}
9660+
9661+int dpsw_get_irq_mask(struct fsl_mc_io *mc_io,
9662+ uint32_t cmd_flags,
9663+ uint16_t token,
9664+ uint8_t irq_index,
9665+ uint32_t *mask)
9666+{
9667+ struct mc_command cmd = { 0 };
9668+ int err;
9669+
9670+ /* prepare command */
9671+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_IRQ_MASK,
9672+ cmd_flags,
9673+ token);
9674+ DPSW_CMD_GET_IRQ_MASK(cmd, irq_index);
9675+
9676+ /* send command to mc*/
9677+ err = mc_send_command(mc_io, &cmd);
9678+ if (err)
9679+ return err;
9680+
9681+ /* retrieve response parameters */
9682+ DPSW_RSP_GET_IRQ_MASK(cmd, *mask);
9683+
9684+ return 0;
9685+}
9686+
9687+int dpsw_get_irq_status(struct fsl_mc_io *mc_io,
9688+ uint32_t cmd_flags,
9689+ uint16_t token,
9690+ uint8_t irq_index,
9691+ uint32_t *status)
9692+{
9693+ struct mc_command cmd = { 0 };
9694+ int err;
9695+
9696+ /* prepare command */
9697+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_IRQ_STATUS,
9698+ cmd_flags,
9699+ token);
9700+ DPSW_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);
9701+
9702+ /* send command to mc*/
9703+ err = mc_send_command(mc_io, &cmd);
9704+ if (err)
9705+ return err;
9706+
9707+ /* retrieve response parameters */
9708+ DPSW_RSP_GET_IRQ_STATUS(cmd, *status);
9709+
9710+ return 0;
9711+}
9712+
9713+int dpsw_clear_irq_status(struct fsl_mc_io *mc_io,
9714+ uint32_t cmd_flags,
9715+ uint16_t token,
9716+ uint8_t irq_index,
9717+ uint32_t status)
9718+{
9719+ struct mc_command cmd = { 0 };
9720+
9721+ /* prepare command */
9722+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CLEAR_IRQ_STATUS,
9723+ cmd_flags,
9724+ token);
9725+ DPSW_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);
9726+
9727+ /* send command to mc*/
9728+ return mc_send_command(mc_io, &cmd);
9729+}
9730+
9731+int dpsw_get_attributes(struct fsl_mc_io *mc_io,
9732+ uint32_t cmd_flags,
9733+ uint16_t token,
9734+ struct dpsw_attr *attr)
9735+{
9736+ struct mc_command cmd = { 0 };
9737+ int err;
9738+
9739+ /* prepare command */
9740+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_ATTR,
9741+ cmd_flags,
9742+ token);
9743+
9744+ /* send command to mc*/
9745+ err = mc_send_command(mc_io, &cmd);
9746+ if (err)
9747+ return err;
9748+
9749+ /* retrieve response parameters */
9750+ DPSW_RSP_GET_ATTR(cmd, attr);
9751+
9752+ return 0;
9753+}
9754+
9755+int dpsw_set_reflection_if(struct fsl_mc_io *mc_io,
9756+ uint32_t cmd_flags,
9757+ uint16_t token,
9758+ uint16_t if_id)
9759+{
9760+ struct mc_command cmd = { 0 };
9761+
9762+ /* prepare command */
9763+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_REFLECTION_IF,
9764+ cmd_flags,
9765+ token);
9766+ DPSW_CMD_SET_REFLECTION_IF(cmd, if_id);
9767+
9768+ /* send command to mc*/
9769+ return mc_send_command(mc_io, &cmd);
9770+}
9771+
9772+int dpsw_if_set_link_cfg(struct fsl_mc_io *mc_io,
9773+ uint32_t cmd_flags,
9774+ uint16_t token,
9775+ uint16_t if_id,
9776+ struct dpsw_link_cfg *cfg)
9777+{
9778+ struct mc_command cmd = { 0 };
9779+
9780+ /* prepare command */
9781+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_LINK_CFG,
9782+ cmd_flags,
9783+ token);
9784+ DPSW_CMD_IF_SET_LINK_CFG(cmd, if_id, cfg);
9785+
9786+ /* send command to mc*/
9787+ return mc_send_command(mc_io, &cmd);
9788+}
9789+
9790+int dpsw_if_get_link_state(struct fsl_mc_io *mc_io,
9791+ uint32_t cmd_flags,
9792+ uint16_t token,
9793+ uint16_t if_id,
9794+ struct dpsw_link_state *state)
9795+{
9796+ struct mc_command cmd = { 0 };
9797+ int err;
9798+
9799+ /* prepare command */
9800+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_LINK_STATE,
9801+ cmd_flags,
9802+ token);
9803+ DPSW_CMD_IF_GET_LINK_STATE(cmd, if_id);
9804+
9805+ /* send command to mc*/
9806+ err = mc_send_command(mc_io, &cmd);
9807+ if (err)
9808+ return err;
9809+
9810+ /* retrieve response parameters */
9811+ DPSW_RSP_IF_GET_LINK_STATE(cmd, state);
9812+
9813+ return 0;
9814+}
9815+
9816+int dpsw_if_set_flooding(struct fsl_mc_io *mc_io,
9817+ uint32_t cmd_flags,
9818+ uint16_t token,
9819+ uint16_t if_id,
9820+ int en)
9821+{
9822+ struct mc_command cmd = { 0 };
9823+
9824+ /* prepare command */
9825+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_FLOODING,
9826+ cmd_flags,
9827+ token);
9828+ DPSW_CMD_IF_SET_FLOODING(cmd, if_id, en);
9829+
9830+ /* send command to mc*/
9831+ return mc_send_command(mc_io, &cmd);
9832+}
9833+
9834+int dpsw_if_set_broadcast(struct fsl_mc_io *mc_io,
9835+ uint32_t cmd_flags,
9836+ uint16_t token,
9837+ uint16_t if_id,
9838+ int en)
9839+{
9840+ struct mc_command cmd = { 0 };
9841+
9842+ /* prepare command */
9843+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_BROADCAST,
9844+ cmd_flags,
9845+ token);
9846+ DPSW_CMD_IF_SET_FLOODING(cmd, if_id, en);
9847+
9848+ /* send command to mc*/
9849+ return mc_send_command(mc_io, &cmd);
9850+}
9851+
9852+int dpsw_if_set_multicast(struct fsl_mc_io *mc_io,
9853+ uint32_t cmd_flags,
9854+ uint16_t token,
9855+ uint16_t if_id,
9856+ int en)
9857+{
9858+ struct mc_command cmd = { 0 };
9859+
9860+ /* prepare command */
9861+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_MULTICAST,
9862+ cmd_flags,
9863+ token);
9864+ DPSW_CMD_IF_SET_FLOODING(cmd, if_id, en);
9865+
9866+ /* send command to mc*/
9867+ return mc_send_command(mc_io, &cmd);
9868+}
9869+
9870+int dpsw_if_set_tci(struct fsl_mc_io *mc_io,
9871+ uint32_t cmd_flags,
9872+ uint16_t token,
9873+ uint16_t if_id,
9874+ const struct dpsw_tci_cfg *cfg)
9875+{
9876+ struct mc_command cmd = { 0 };
9877+
9878+ /* prepare command */
9879+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_TCI,
9880+ cmd_flags,
9881+ token);
9882+ DPSW_CMD_IF_SET_TCI(cmd, if_id, cfg);
9883+
9884+ /* send command to mc*/
9885+ return mc_send_command(mc_io, &cmd);
9886+}
9887+
9888+int dpsw_if_get_tci(struct fsl_mc_io *mc_io,
9889+ uint32_t cmd_flags,
9890+ uint16_t token,
9891+ uint16_t if_id,
9892+ struct dpsw_tci_cfg *cfg)
9893+{
9894+ struct mc_command cmd = { 0 };
9895+ int err = 0;
9896+
9897+ /* prepare command */
9898+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_TCI,
9899+ cmd_flags,
9900+ token);
9901+ DPSW_CMD_IF_GET_TCI(cmd, if_id);
9902+
9903+ /* send command to mc*/
9904+ err = mc_send_command(mc_io, &cmd);
9905+ if (err)
9906+ return err;
9907+
9908+ /* retrieve response parameters */
9909+ DPSW_RSP_IF_GET_TCI(cmd, cfg);
9910+
9911+ return 0;
9912+}
9913+
9914+int dpsw_if_set_stp(struct fsl_mc_io *mc_io,
9915+ uint32_t cmd_flags,
9916+ uint16_t token,
9917+ uint16_t if_id,
9918+ const struct dpsw_stp_cfg *cfg)
9919+{
9920+ struct mc_command cmd = { 0 };
9921+
9922+ /* prepare command */
9923+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_STP,
9924+ cmd_flags,
9925+ token);
9926+ DPSW_CMD_IF_SET_STP(cmd, if_id, cfg);
9927+
9928+ /* send command to mc*/
9929+ return mc_send_command(mc_io, &cmd);
9930+}
9931+
9932+int dpsw_if_set_accepted_frames(struct fsl_mc_io *mc_io,
9933+ uint32_t cmd_flags,
9934+ uint16_t token,
9935+ uint16_t if_id,
9936+ const struct dpsw_accepted_frames_cfg *cfg)
9937+{
9938+ struct mc_command cmd = { 0 };
9939+
9940+ /* prepare command */
9941+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_ACCEPTED_FRAMES,
9942+ cmd_flags,
9943+ token);
9944+ DPSW_CMD_IF_SET_ACCEPTED_FRAMES(cmd, if_id, cfg);
9945+
9946+ /* send command to mc*/
9947+ return mc_send_command(mc_io, &cmd);
9948+}
9949+
9950+int dpsw_if_set_accept_all_vlan(struct fsl_mc_io *mc_io,
9951+ uint32_t cmd_flags,
9952+ uint16_t token,
9953+ uint16_t if_id,
9954+ int accept_all)
9955+{
9956+ struct mc_command cmd = { 0 };
9957+
9958+ /* prepare command */
9959+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_IF_ACCEPT_ALL_VLAN,
9960+ cmd_flags,
9961+ token);
9962+ DPSW_CMD_IF_SET_ACCEPT_ALL_VLAN(cmd, if_id, accept_all);
9963+
9964+ /* send command to mc*/
9965+ return mc_send_command(mc_io, &cmd);
9966+}
9967+
9968+int dpsw_if_get_counter(struct fsl_mc_io *mc_io,
9969+ uint32_t cmd_flags,
9970+ uint16_t token,
9971+ uint16_t if_id,
9972+ enum dpsw_counter type,
9973+ uint64_t *counter)
9974+{
9975+ struct mc_command cmd = { 0 };
9976+ int err;
9977+
9978+ /* prepare command */
9979+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_COUNTER,
9980+ cmd_flags,
9981+ token);
9982+ DPSW_CMD_IF_GET_COUNTER(cmd, if_id, type);
9983+
9984+ /* send command to mc*/
9985+ err = mc_send_command(mc_io, &cmd);
9986+ if (err)
9987+ return err;
9988+
9989+ /* retrieve response parameters */
9990+ DPSW_RSP_IF_GET_COUNTER(cmd, *counter);
9991+
9992+ return 0;
9993+}
9994+
9995+int dpsw_if_set_counter(struct fsl_mc_io *mc_io,
9996+ uint32_t cmd_flags,
9997+ uint16_t token,
9998+ uint16_t if_id,
9999+ enum dpsw_counter type,
10000+ uint64_t counter)
10001+{
10002+ struct mc_command cmd = { 0 };
10003+
10004+ /* prepare command */
10005+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_COUNTER,
10006+ cmd_flags,
10007+ token);
10008+ DPSW_CMD_IF_SET_COUNTER(cmd, if_id, type, counter);
10009+
10010+ /* send command to mc*/
10011+ return mc_send_command(mc_io, &cmd);
10012+}
10013+
10014+int dpsw_if_set_tx_selection(struct fsl_mc_io *mc_io,
10015+ uint32_t cmd_flags,
10016+ uint16_t token,
10017+ uint16_t if_id,
10018+ const struct dpsw_tx_selection_cfg *cfg)
10019+{
10020+ struct mc_command cmd = { 0 };
10021+
10022+ /* prepare command */
10023+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_TX_SELECTION,
10024+ cmd_flags,
10025+ token);
10026+ DPSW_CMD_IF_SET_TX_SELECTION(cmd, if_id, cfg);
10027+
10028+ /* send command to mc*/
10029+ return mc_send_command(mc_io, &cmd);
10030+}
10031+
10032+int dpsw_if_add_reflection(struct fsl_mc_io *mc_io,
10033+ uint32_t cmd_flags,
10034+ uint16_t token,
10035+ uint16_t if_id,
10036+ const struct dpsw_reflection_cfg *cfg)
10037+{
10038+ struct mc_command cmd = { 0 };
10039+
10040+ /* prepare command */
10041+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_ADD_REFLECTION,
10042+ cmd_flags,
10043+ token);
10044+ DPSW_CMD_IF_ADD_REFLECTION(cmd, if_id, cfg);
10045+
10046+ /* send command to mc*/
10047+ return mc_send_command(mc_io, &cmd);
10048+}
10049+
10050+int dpsw_if_remove_reflection(struct fsl_mc_io *mc_io,
10051+ uint32_t cmd_flags,
10052+ uint16_t token,
10053+ uint16_t if_id,
10054+ const struct dpsw_reflection_cfg *cfg)
10055+{
10056+ struct mc_command cmd = { 0 };
10057+
10058+ /* prepare command */
10059+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_REMOVE_REFLECTION,
10060+ cmd_flags,
10061+ token);
10062+ DPSW_CMD_IF_REMOVE_REFLECTION(cmd, if_id, cfg);
10063+
10064+ /* send command to mc*/
10065+ return mc_send_command(mc_io, &cmd);
10066+}
10067+
10068+int dpsw_if_set_flooding_metering(struct fsl_mc_io *mc_io,
10069+ uint32_t cmd_flags,
10070+ uint16_t token,
10071+ uint16_t if_id,
10072+ const struct dpsw_metering_cfg *cfg)
10073+{
10074+ struct mc_command cmd = { 0 };
10075+
10076+ /* prepare command */
10077+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_FLOODING_METERING,
10078+ cmd_flags,
10079+ token);
10080+ DPSW_CMD_IF_SET_FLOODING_METERING(cmd, if_id, cfg);
10081+
10082+ /* send command to mc*/
10083+ return mc_send_command(mc_io, &cmd);
10084+}
10085+
10086+int dpsw_if_set_metering(struct fsl_mc_io *mc_io,
10087+ uint32_t cmd_flags,
10088+ uint16_t token,
10089+ uint16_t if_id,
10090+ uint8_t tc_id,
10091+ const struct dpsw_metering_cfg *cfg)
10092+{
10093+ struct mc_command cmd = { 0 };
10094+
10095+ /* prepare command */
10096+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_METERING,
10097+ cmd_flags,
10098+ token);
10099+ DPSW_CMD_IF_SET_METERING(cmd, if_id, tc_id, cfg);
10100+
10101+ /* send command to mc*/
10102+ return mc_send_command(mc_io, &cmd);
10103+}
10104+
10105+void dpsw_prepare_early_drop(const struct dpsw_early_drop_cfg *cfg,
10106+ uint8_t *early_drop_buf)
10107+{
10108+ uint64_t *ext_params = (uint64_t *)early_drop_buf;
10109+
10110+ DPSW_PREP_EARLY_DROP(ext_params, cfg);
10111+}
10112+
10113+int dpsw_if_set_early_drop(struct fsl_mc_io *mc_io,
10114+ uint32_t cmd_flags,
10115+ uint16_t token,
10116+ uint16_t if_id,
10117+ uint8_t tc_id,
10118+ uint64_t early_drop_iova)
10119+{
10120+ struct mc_command cmd = { 0 };
10121+
10122+ /* prepare command */
10123+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_EARLY_DROP,
10124+ cmd_flags,
10125+ token);
10126+ DPSW_CMD_IF_SET_EARLY_DROP(cmd, if_id, tc_id, early_drop_iova);
10127+
10128+ /* send command to mc*/
10129+ return mc_send_command(mc_io, &cmd);
10130+}
10131+
10132+int dpsw_add_custom_tpid(struct fsl_mc_io *mc_io,
10133+ uint32_t cmd_flags,
10134+ uint16_t token,
10135+ const struct dpsw_custom_tpid_cfg *cfg)
10136+{
10137+ struct mc_command cmd = { 0 };
10138+
10139+ /* prepare command */
10140+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ADD_CUSTOM_TPID,
10141+ cmd_flags,
10142+ token);
10143+ DPSW_CMD_ADD_CUSTOM_TPID(cmd, cfg);
10144+
10145+ /* send command to mc*/
10146+ return mc_send_command(mc_io, &cmd);
10147+}
10148+
10149+int dpsw_remove_custom_tpid(struct fsl_mc_io *mc_io,
10150+ uint32_t cmd_flags,
10151+ uint16_t token,
10152+ const struct dpsw_custom_tpid_cfg *cfg)
10153+{
10154+ struct mc_command cmd = { 0 };
10155+
10156+ /* prepare command */
10157+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_REMOVE_CUSTOM_TPID,
10158+ cmd_flags,
10159+ token);
10160+ DPSW_CMD_REMOVE_CUSTOM_TPID(cmd, cfg);
10161+
10162+ /* send command to mc*/
10163+ return mc_send_command(mc_io, &cmd);
10164+}
10165+
10166+int dpsw_if_enable(struct fsl_mc_io *mc_io,
10167+ uint32_t cmd_flags,
10168+ uint16_t token,
10169+ uint16_t if_id)
10170+{
10171+ struct mc_command cmd = { 0 };
10172+
10173+ /* prepare command */
10174+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_ENABLE,
10175+ cmd_flags,
10176+ token);
10177+ DPSW_CMD_IF_ENABLE(cmd, if_id);
10178+
10179+ /* send command to mc*/
10180+ return mc_send_command(mc_io, &cmd);
10181+}
10182+
10183+int dpsw_if_disable(struct fsl_mc_io *mc_io,
10184+ uint32_t cmd_flags,
10185+ uint16_t token,
10186+ uint16_t if_id)
10187+{
10188+ struct mc_command cmd = { 0 };
10189+
10190+ /* prepare command */
10191+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_DISABLE,
10192+ cmd_flags,
10193+ token);
10194+ DPSW_CMD_IF_DISABLE(cmd, if_id);
10195+
10196+ /* send command to mc*/
10197+ return mc_send_command(mc_io, &cmd);
10198+}
10199+
10200+int dpsw_if_get_attributes(struct fsl_mc_io *mc_io,
10201+ uint32_t cmd_flags,
10202+ uint16_t token,
10203+ uint16_t if_id,
10204+ struct dpsw_if_attr *attr)
10205+{
10206+ struct mc_command cmd = { 0 };
10207+ int err;
10208+
10209+ /* prepare command */
10210+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_ATTR,
10211+ cmd_flags,
10212+ token);
10213+ DPSW_CMD_IF_GET_ATTR(cmd, if_id);
10214+
10215+ /* send command to mc*/
10216+ err = mc_send_command(mc_io, &cmd);
10217+ if (err)
10218+ return err;
10219+
10220+ /* retrieve response parameters */
10221+ DPSW_RSP_IF_GET_ATTR(cmd, attr);
10222+
10223+ return 0;
10224+}
10225+
10226+int dpsw_if_set_max_frame_length(struct fsl_mc_io *mc_io,
10227+ uint32_t cmd_flags,
10228+ uint16_t token,
10229+ uint16_t if_id,
10230+ uint16_t frame_length)
10231+{
10232+ struct mc_command cmd = { 0 };
10233+
10234+ /* prepare command */
10235+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH,
10236+ cmd_flags,
10237+ token);
10238+ DPSW_CMD_IF_SET_MAX_FRAME_LENGTH(cmd, if_id, frame_length);
10239+
10240+ /* send command to mc*/
10241+ return mc_send_command(mc_io, &cmd);
10242+}
10243+
10244+int dpsw_if_get_max_frame_length(struct fsl_mc_io *mc_io,
10245+ uint32_t cmd_flags,
10246+ uint16_t token,
10247+ uint16_t if_id,
10248+ uint16_t *frame_length)
10249+{
10250+ struct mc_command cmd = { 0 };
10251+ int err;
10252+
10253+ /* prepare command */
10254+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_MAX_FRAME_LENGTH,
10255+ cmd_flags,
10256+ token);
10257+ DPSW_CMD_IF_GET_MAX_FRAME_LENGTH(cmd, if_id);
10258+
10259+ /* send command to mc*/
10260+ err = mc_send_command(mc_io, &cmd);
10261+ if (err)
10262+ return err;
10263+
10264+ DPSW_RSP_IF_GET_MAX_FRAME_LENGTH(cmd, *frame_length);
10265+
10266+ return 0;
10267+}
10268+
10269+int dpsw_vlan_add(struct fsl_mc_io *mc_io,
10270+ uint32_t cmd_flags,
10271+ uint16_t token,
10272+ uint16_t vlan_id,
10273+ const struct dpsw_vlan_cfg *cfg)
10274+{
10275+ struct mc_command cmd = { 0 };
10276+
10277+ /* prepare command */
10278+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD,
10279+ cmd_flags,
10280+ token);
10281+ DPSW_CMD_VLAN_ADD(cmd, vlan_id, cfg);
10282+
10283+ /* send command to mc*/
10284+ return mc_send_command(mc_io, &cmd);
10285+}
10286+
10287+int dpsw_vlan_add_if(struct fsl_mc_io *mc_io,
10288+ uint32_t cmd_flags,
10289+ uint16_t token,
10290+ uint16_t vlan_id,
10291+ const struct dpsw_vlan_if_cfg *cfg)
10292+{
10293+ struct mc_command cmd = { 0 };
10294+
10295+ /* prepare command */
10296+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1);
10297+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD_IF,
10298+ cmd_flags,
10299+ token);
10300+ DPSW_CMD_VLAN_ADD_IF(cmd, vlan_id);
10301+
10302+ /* send command to mc*/
10303+ return mc_send_command(mc_io, &cmd);
10304+}
10305+
10306+int dpsw_vlan_add_if_untagged(struct fsl_mc_io *mc_io,
10307+ uint32_t cmd_flags,
10308+ uint16_t token,
10309+ uint16_t vlan_id,
10310+ const struct dpsw_vlan_if_cfg *cfg)
10311+{
10312+ struct mc_command cmd = { 0 };
10313+
10314+ /* prepare command */
10315+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1);
10316+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD_IF_UNTAGGED,
10317+ cmd_flags,
10318+ token);
10319+ DPSW_CMD_VLAN_ADD_IF_UNTAGGED(cmd, vlan_id);
10320+
10321+ /* send command to mc*/
10322+ return mc_send_command(mc_io, &cmd);
10323+}
10324+
10325+int dpsw_vlan_add_if_flooding(struct fsl_mc_io *mc_io,
10326+ uint32_t cmd_flags,
10327+ uint16_t token,
10328+ uint16_t vlan_id,
10329+ const struct dpsw_vlan_if_cfg *cfg)
10330+{
10331+ struct mc_command cmd = { 0 };
10332+
10333+ /* prepare command */
10334+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1);
10335+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD_IF_FLOODING,
10336+ cmd_flags,
10337+ token);
10338+ DPSW_CMD_VLAN_ADD_IF_FLOODING(cmd, vlan_id);
10339+
10340+ /* send command to mc*/
10341+ return mc_send_command(mc_io, &cmd);
10342+}
10343+
10344+int dpsw_vlan_remove_if(struct fsl_mc_io *mc_io,
10345+ uint32_t cmd_flags,
10346+ uint16_t token,
10347+ uint16_t vlan_id,
10348+ const struct dpsw_vlan_if_cfg *cfg)
10349+{
10350+ struct mc_command cmd = { 0 };
10351+
10352+ /* prepare command */
10353+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1);
10354+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE_IF,
10355+ cmd_flags,
10356+ token);
10357+ DPSW_CMD_VLAN_REMOVE_IF(cmd, vlan_id);
10358+
10359+ /* send command to mc*/
10360+ return mc_send_command(mc_io, &cmd);
10361+}
10362+
10363+int dpsw_vlan_remove_if_untagged(struct fsl_mc_io *mc_io,
10364+ uint32_t cmd_flags,
10365+ uint16_t token,
10366+ uint16_t vlan_id,
10367+ const struct dpsw_vlan_if_cfg *cfg)
10368+{
10369+ struct mc_command cmd = { 0 };
10370+
10371+ /* prepare command */
10372+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1);
10373+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED,
10374+ cmd_flags,
10375+ token);
10376+ DPSW_CMD_VLAN_REMOVE_IF_UNTAGGED(cmd, vlan_id);
10377+
10378+ /* send command to mc*/
10379+ return mc_send_command(mc_io, &cmd);
10380+}
10381+
10382+int dpsw_vlan_remove_if_flooding(struct fsl_mc_io *mc_io,
10383+ uint32_t cmd_flags,
10384+ uint16_t token,
10385+ uint16_t vlan_id,
10386+ const struct dpsw_vlan_if_cfg *cfg)
10387+{
10388+ struct mc_command cmd = { 0 };
10389+
10390+ /* prepare command */
10391+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1);
10392+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE_IF_FLOODING,
10393+ cmd_flags,
10394+ token);
10395+ DPSW_CMD_VLAN_REMOVE_IF_FLOODING(cmd, vlan_id);
10396+
10397+ /* send command to mc*/
10398+ return mc_send_command(mc_io, &cmd);
10399+}
10400+
10401+int dpsw_vlan_remove(struct fsl_mc_io *mc_io,
10402+ uint32_t cmd_flags,
10403+ uint16_t token,
10404+ uint16_t vlan_id)
10405+{
10406+ struct mc_command cmd = { 0 };
10407+
10408+ /* prepare command */
10409+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE,
10410+ cmd_flags,
10411+ token);
10412+ DPSW_CMD_VLAN_REMOVE(cmd, vlan_id);
10413+
10414+ /* send command to mc*/
10415+ return mc_send_command(mc_io, &cmd);
10416+}
10417+
10418+int dpsw_vlan_get_attributes(struct fsl_mc_io *mc_io,
10419+ uint32_t cmd_flags,
10420+ uint16_t token,
10421+ uint16_t vlan_id,
10422+ struct dpsw_vlan_attr *attr)
10423+{
10424+ struct mc_command cmd = { 0 };
10425+ int err;
10426+
10427+ /* prepare command */
10428+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_GET_ATTRIBUTES,
10429+ cmd_flags,
10430+ token);
10431+ DPSW_CMD_VLAN_GET_ATTR(cmd, vlan_id);
10432+
10433+ /* send command to mc*/
10434+ err = mc_send_command(mc_io, &cmd);
10435+ if (err)
10436+ return err;
10437+
10438+ /* retrieve response parameters */
10439+ DPSW_RSP_VLAN_GET_ATTR(cmd, attr);
10440+
10441+ return 0;
10442+}
10443+
10444+int dpsw_vlan_get_if(struct fsl_mc_io *mc_io,
10445+ uint32_t cmd_flags,
10446+ uint16_t token,
10447+ uint16_t vlan_id,
10448+ struct dpsw_vlan_if_cfg *cfg)
10449+{
10450+ struct mc_command cmd = { 0 };
10451+ int err;
10452+
10453+ /* prepare command */
10454+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_GET_IF,
10455+ cmd_flags,
10456+ token);
10457+ DPSW_CMD_VLAN_GET_IF(cmd, vlan_id);
10458+
10459+ /* send command to mc*/
10460+ err = mc_send_command(mc_io, &cmd);
10461+ if (err)
10462+ return err;
10463+
10464+ /* retrieve response parameters */
10465+ DPSW_RSP_VLAN_GET_IF(cmd, cfg);
10466+ read_if_id_bitmap(cfg->if_id, &cfg->num_ifs, &cmd, 1);
10467+
10468+ return 0;
10469+}
10470+
10471+int dpsw_vlan_get_if_flooding(struct fsl_mc_io *mc_io,
10472+ uint32_t cmd_flags,
10473+ uint16_t token,
10474+ uint16_t vlan_id,
10475+ struct dpsw_vlan_if_cfg *cfg)
10476+{
10477+ struct mc_command cmd = { 0 };
10478+ int err;
10479+
10480+ /* prepare command */
10481+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_GET_IF_FLOODING,
10482+ cmd_flags,
10483+ token);
10484+ DPSW_CMD_VLAN_GET_IF_FLOODING(cmd, vlan_id);
10485+
10486+ /* send command to mc*/
10487+ err = mc_send_command(mc_io, &cmd);
10488+ if (err)
10489+ return err;
10490+
10491+ /* retrieve response parameters */
10492+ DPSW_RSP_VLAN_GET_IF_FLOODING(cmd, cfg);
10493+ read_if_id_bitmap(cfg->if_id, &cfg->num_ifs, &cmd, 1);
10494+
10495+ return 0;
10496+}
10497+
10498+int dpsw_vlan_get_if_untagged(struct fsl_mc_io *mc_io,
10499+ uint32_t cmd_flags,
10500+ uint16_t token,
10501+ uint16_t vlan_id,
10502+ struct dpsw_vlan_if_cfg *cfg)
10503+{
10504+ struct mc_command cmd = { 0 };
10505+ int err;
10506+
10507+ /* prepare command */
10508+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_GET_IF_UNTAGGED,
10509+ cmd_flags,
10510+ token);
10511+ DPSW_CMD_VLAN_GET_IF_UNTAGGED(cmd, vlan_id);
10512+
10513+ /* send command to mc*/
10514+ err = mc_send_command(mc_io, &cmd);
10515+ if (err)
10516+ return err;
10517+
10518+ /* retrieve response parameters */
10519+ DPSW_RSP_VLAN_GET_IF(cmd, cfg);
10520+ read_if_id_bitmap(cfg->if_id, &cfg->num_ifs, &cmd, 1);
10521+
10522+ return 0;
10523+}
10524+
10525+int dpsw_fdb_add(struct fsl_mc_io *mc_io,
10526+ uint32_t cmd_flags,
10527+ uint16_t token,
10528+ uint16_t *fdb_id,
10529+ const struct dpsw_fdb_cfg *cfg)
10530+{
10531+ struct mc_command cmd = { 0 };
10532+ int err;
10533+
10534+ /* prepare command */
10535+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_ADD,
10536+ cmd_flags,
10537+ token);
10538+ DPSW_CMD_FDB_ADD(cmd, cfg);
10539+
10540+ /* send command to mc*/
10541+ err = mc_send_command(mc_io, &cmd);
10542+ if (err)
10543+ return err;
10544+
10545+ /* retrieve response parameters */
10546+ DPSW_RSP_FDB_ADD(cmd, *fdb_id);
10547+
10548+ return 0;
10549+}
10550+
10551+int dpsw_fdb_remove(struct fsl_mc_io *mc_io,
10552+ uint32_t cmd_flags,
10553+ uint16_t token,
10554+ uint16_t fdb_id)
10555+{
10556+ struct mc_command cmd = { 0 };
10557+
10558+ /* prepare command */
10559+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_REMOVE,
10560+ cmd_flags,
10561+ token);
10562+ DPSW_CMD_FDB_REMOVE(cmd, fdb_id);
10563+
10564+ /* send command to mc*/
10565+ return mc_send_command(mc_io, &cmd);
10566+}
10567+
10568+int dpsw_fdb_add_unicast(struct fsl_mc_io *mc_io,
10569+ uint32_t cmd_flags,
10570+ uint16_t token,
10571+ uint16_t fdb_id,
10572+ const struct dpsw_fdb_unicast_cfg *cfg)
10573+{
10574+ struct mc_command cmd = { 0 };
10575+
10576+ /* prepare command */
10577+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_ADD_UNICAST,
10578+ cmd_flags,
10579+ token);
10580+ DPSW_CMD_FDB_ADD_UNICAST(cmd, fdb_id, cfg);
10581+
10582+ /* send command to mc*/
10583+ return mc_send_command(mc_io, &cmd);
10584+}
10585+
10586+int dpsw_fdb_get_unicast(struct fsl_mc_io *mc_io,
10587+ uint32_t cmd_flags,
10588+ uint16_t token,
10589+ uint16_t fdb_id,
10590+ struct dpsw_fdb_unicast_cfg *cfg)
10591+{
10592+ struct mc_command cmd = { 0 };
10593+ int err;
10594+
10595+ /* prepare command */
10596+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_GET_UNICAST,
10597+ cmd_flags,
10598+ token);
10599+ DPSW_CMD_FDB_GET_UNICAST(cmd, fdb_id);
10600+
10601+ /* send command to mc*/
10602+ err = mc_send_command(mc_io, &cmd);
10603+ if (err)
10604+ return err;
10605+
10606+ /* retrieve response parameters */
10607+ DPSW_RSP_FDB_GET_UNICAST(cmd, cfg);
10608+
10609+ return 0;
10610+}
10611+
10612+int dpsw_fdb_remove_unicast(struct fsl_mc_io *mc_io,
10613+ uint32_t cmd_flags,
10614+ uint16_t token,
10615+ uint16_t fdb_id,
10616+ const struct dpsw_fdb_unicast_cfg *cfg)
10617+{
10618+ struct mc_command cmd = { 0 };
10619+
10620+ /* prepare command */
10621+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_REMOVE_UNICAST,
10622+ cmd_flags,
10623+ token);
10624+ DPSW_CMD_FDB_REMOVE_UNICAST(cmd, fdb_id, cfg);
10625+
10626+ /* send command to mc*/
10627+ return mc_send_command(mc_io, &cmd);
10628+}
10629+
10630+int dpsw_fdb_add_multicast(struct fsl_mc_io *mc_io,
10631+ uint32_t cmd_flags,
10632+ uint16_t token,
10633+ uint16_t fdb_id,
10634+ const struct dpsw_fdb_multicast_cfg *cfg)
10635+{
10636+ struct mc_command cmd = { 0 };
10637+
10638+ /* prepare command */
10639+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 2);
10640+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_ADD_MULTICAST,
10641+ cmd_flags,
10642+ token);
10643+ DPSW_CMD_FDB_ADD_MULTICAST(cmd, fdb_id, cfg);
10644+
10645+ /* send command to mc*/
10646+ return mc_send_command(mc_io, &cmd);
10647+}
10648+
10649+int dpsw_fdb_get_multicast(struct fsl_mc_io *mc_io,
10650+ uint32_t cmd_flags,
10651+ uint16_t token,
10652+ uint16_t fdb_id,
10653+ struct dpsw_fdb_multicast_cfg *cfg)
10654+{
10655+ struct mc_command cmd = { 0 };
10656+ int err;
10657+
10658+ /* prepare command */
10659+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_GET_MULTICAST,
10660+ cmd_flags,
10661+ token);
10662+ DPSW_CMD_FDB_GET_MULTICAST(cmd, fdb_id);
10663+
10664+ /* send command to mc*/
10665+ err = mc_send_command(mc_io, &cmd);
10666+ if (err)
10667+ return err;
10668+
10669+ /* retrieve response parameters */
10670+ DPSW_RSP_FDB_GET_MULTICAST(cmd, cfg);
10671+ read_if_id_bitmap(cfg->if_id, &cfg->num_ifs, &cmd, 2);
10672+
10673+ return 0;
10674+}
10675+
10676+int dpsw_fdb_remove_multicast(struct fsl_mc_io *mc_io,
10677+ uint32_t cmd_flags,
10678+ uint16_t token,
10679+ uint16_t fdb_id,
10680+ const struct dpsw_fdb_multicast_cfg *cfg)
10681+{
10682+ struct mc_command cmd = { 0 };
10683+
10684+ /* prepare command */
10685+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 2);
10686+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_REMOVE_MULTICAST,
10687+ cmd_flags,
10688+ token);
10689+ DPSW_CMD_FDB_REMOVE_MULTICAST(cmd, fdb_id, cfg);
10690+
10691+ /* send command to mc*/
10692+ return mc_send_command(mc_io, &cmd);
10693+}
10694+
10695+int dpsw_fdb_set_learning_mode(struct fsl_mc_io *mc_io,
10696+ uint32_t cmd_flags,
10697+ uint16_t token,
10698+ uint16_t fdb_id,
10699+ enum dpsw_fdb_learning_mode mode)
10700+{
10701+ struct mc_command cmd = { 0 };
10702+
10703+ /* prepare command */
10704+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_SET_LEARNING_MODE,
10705+ cmd_flags,
10706+ token);
10707+ DPSW_CMD_FDB_SET_LEARNING_MODE(cmd, fdb_id, mode);
10708+
10709+ /* send command to mc*/
10710+ return mc_send_command(mc_io, &cmd);
10711+}
10712+
10713+int dpsw_fdb_get_attributes(struct fsl_mc_io *mc_io,
10714+ uint32_t cmd_flags,
10715+ uint16_t token,
10716+ uint16_t fdb_id,
10717+ struct dpsw_fdb_attr *attr)
10718+{
10719+ struct mc_command cmd = { 0 };
10720+ int err;
10721+
10722+ /* prepare command */
10723+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_GET_ATTR,
10724+ cmd_flags,
10725+ token);
10726+ DPSW_CMD_FDB_GET_ATTR(cmd, fdb_id);
10727+
10728+ /* send command to mc*/
10729+ err = mc_send_command(mc_io, &cmd);
10730+ if (err)
10731+ return err;
10732+
10733+ /* retrieve response parameters */
10734+ DPSW_RSP_FDB_GET_ATTR(cmd, attr);
10735+
10736+ return 0;
10737+}
10738+
10739+int dpsw_acl_add(struct fsl_mc_io *mc_io,
10740+ uint32_t cmd_flags,
10741+ uint16_t token,
10742+ uint16_t *acl_id,
10743+ const struct dpsw_acl_cfg *cfg)
10744+{
10745+ struct mc_command cmd = { 0 };
10746+ int err;
10747+
10748+ /* prepare command */
10749+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_ADD,
10750+ cmd_flags,
10751+ token);
10752+ DPSW_CMD_ACL_ADD(cmd, cfg);
10753+
10754+ /* send command to mc*/
10755+ err = mc_send_command(mc_io, &cmd);
10756+ if (err)
10757+ return err;
10758+
10759+ /* retrieve response parameters */
10760+ DPSW_RSP_ACL_ADD(cmd, *acl_id);
10761+
10762+ return 0;
10763+}
10764+
10765+int dpsw_acl_remove(struct fsl_mc_io *mc_io,
10766+ uint32_t cmd_flags,
10767+ uint16_t token,
10768+ uint16_t acl_id)
10769+{
10770+ struct mc_command cmd = { 0 };
10771+
10772+ /* prepare command */
10773+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_REMOVE,
10774+ cmd_flags,
10775+ token);
10776+ DPSW_CMD_ACL_REMOVE(cmd, acl_id);
10777+
10778+ /* send command to mc*/
10779+ return mc_send_command(mc_io, &cmd);
10780+}
10781+
10782+void dpsw_acl_prepare_entry_cfg(const struct dpsw_acl_key *key,
10783+ uint8_t *entry_cfg_buf)
10784+{
10785+ uint64_t *ext_params = (uint64_t *)entry_cfg_buf;
10786+
10787+ DPSW_PREP_ACL_ENTRY(ext_params, key);
10788+}
10789+
10790+int dpsw_acl_add_entry(struct fsl_mc_io *mc_io,
10791+ uint32_t cmd_flags,
10792+ uint16_t token,
10793+ uint16_t acl_id,
10794+ const struct dpsw_acl_entry_cfg *cfg)
10795+{
10796+ struct mc_command cmd = { 0 };
10797+
10798+ /* prepare command */
10799+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_ADD_ENTRY,
10800+ cmd_flags,
10801+ token);
10802+ DPSW_CMD_ACL_ADD_ENTRY(cmd, acl_id, cfg);
10803+
10804+ /* send command to mc*/
10805+ return mc_send_command(mc_io, &cmd);
10806+}
10807+
10808+int dpsw_acl_remove_entry(struct fsl_mc_io *mc_io,
10809+ uint32_t cmd_flags,
10810+ uint16_t token,
10811+ uint16_t acl_id,
10812+ const struct dpsw_acl_entry_cfg *cfg)
10813+{
10814+ struct mc_command cmd = { 0 };
10815+
10816+ /* prepare command */
10817+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_REMOVE_ENTRY,
10818+ cmd_flags,
10819+ token);
10820+ DPSW_CMD_ACL_REMOVE_ENTRY(cmd, acl_id, cfg);
10821+
10822+ /* send command to mc*/
10823+ return mc_send_command(mc_io, &cmd);
10824+}
10825+
10826+int dpsw_acl_add_if(struct fsl_mc_io *mc_io,
10827+ uint32_t cmd_flags,
10828+ uint16_t token,
10829+ uint16_t acl_id,
10830+ const struct dpsw_acl_if_cfg *cfg)
10831+{
10832+ struct mc_command cmd = { 0 };
10833+
10834+ /* prepare command */
10835+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1);
10836+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_ADD_IF,
10837+ cmd_flags,
10838+ token);
10839+ DPSW_CMD_ACL_ADD_IF(cmd, acl_id, cfg);
10840+
10841+ /* send command to mc*/
10842+ return mc_send_command(mc_io, &cmd);
10843+}
10844+
10845+int dpsw_acl_remove_if(struct fsl_mc_io *mc_io,
10846+ uint32_t cmd_flags,
10847+ uint16_t token,
10848+ uint16_t acl_id,
10849+ const struct dpsw_acl_if_cfg *cfg)
10850+{
10851+ struct mc_command cmd = { 0 };
10852+
10853+ /* prepare command */
10854+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1);
10855+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_REMOVE_IF,
10856+ cmd_flags,
10857+ token);
10858+ DPSW_CMD_ACL_REMOVE_IF(cmd, acl_id, cfg);
10859+
10860+ /* send command to mc*/
10861+ return mc_send_command(mc_io, &cmd);
10862+}
10863+
10864+int dpsw_acl_get_attributes(struct fsl_mc_io *mc_io,
10865+ uint32_t cmd_flags,
10866+ uint16_t token,
10867+ uint16_t acl_id,
10868+ struct dpsw_acl_attr *attr)
10869+{
10870+ struct mc_command cmd = { 0 };
10871+ int err;
10872+
10873+ /* prepare command */
10874+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_GET_ATTR,
10875+ cmd_flags,
10876+ token);
10877+ DPSW_CMD_ACL_GET_ATTR(cmd, acl_id);
10878+
10879+ /* send command to mc*/
10880+ err = mc_send_command(mc_io, &cmd);
10881+ if (err)
10882+ return err;
10883+
10884+ /* retrieve response parameters */
10885+ DPSW_RSP_ACL_GET_ATTR(cmd, attr);
10886+
10887+ return 0;
10888+}
10889+
10890+int dpsw_ctrl_if_get_attributes(struct fsl_mc_io *mc_io,
10891+ uint32_t cmd_flags,
10892+ uint16_t token,
10893+ struct dpsw_ctrl_if_attr *attr)
10894+{
10895+ struct mc_command cmd = { 0 };
10896+ int err;
10897+
10898+ /* prepare command */
10899+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CTRL_IF_GET_ATTR,
10900+ cmd_flags,
10901+ token);
10902+
10903+ /* send command to mc*/
10904+ err = mc_send_command(mc_io, &cmd);
10905+ if (err)
10906+ return err;
10907+
10908+ /* retrieve response parameters */
10909+ DPSW_RSP_CTRL_IF_GET_ATTR(cmd, attr);
10910+
10911+ return 0;
10912+}
10913+
10914+int dpsw_ctrl_if_set_pools(struct fsl_mc_io *mc_io,
10915+ uint32_t cmd_flags,
10916+ uint16_t token,
10917+ const struct dpsw_ctrl_if_pools_cfg *pools)
10918+{
10919+ struct mc_command cmd = { 0 };
10920+
10921+ /* prepare command */
10922+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CTRL_IF_SET_POOLS,
10923+ cmd_flags,
10924+ token);
10925+ DPSW_CMD_CTRL_IF_SET_POOLS(cmd, pools);
10926+
10927+ /* send command to mc*/
10928+ return mc_send_command(mc_io, &cmd);
10929+}
10930+
10931+int dpsw_ctrl_if_enable(struct fsl_mc_io *mc_io,
10932+ uint32_t cmd_flags,
10933+ uint16_t token)
10934+{
10935+ struct mc_command cmd = { 0 };
10936+
10937+ /* prepare command */
10938+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CTRL_IF_ENABLE,
10939+ cmd_flags,
10940+ token);
10941+
10942+ /* send command to mc*/
10943+ return mc_send_command(mc_io, &cmd);
10944+}
10945+
10946+/**
10947+* @brief Function disables control interface
10948+* @mc_io: Pointer to MC portal's I/O object
10949+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
10950+* @token: Token of DPSW object
10951+*
10952+* Return: '0' on Success; Error code otherwise.
10953+*/
10954+int dpsw_ctrl_if_disable(struct fsl_mc_io *mc_io,
10955+ uint32_t cmd_flags,
10956+ uint16_t token)
10957+{
10958+ struct mc_command cmd = { 0 };
10959+
10960+ /* prepare command */
10961+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CTRL_IF_DISABLE,
10962+ cmd_flags,
10963+ token);
10964+
10965+ /* send command to mc*/
10966+ return mc_send_command(mc_io, &cmd);
10967+}
10968diff --git a/drivers/net/dpaa2/mc/fsl_dpaiop.h b/drivers/net/dpaa2/mc/fsl_dpaiop.h
10969new file mode 100644
10970index 0000000..b039b2a
10971--- /dev/null
10972+++ b/drivers/net/dpaa2/mc/fsl_dpaiop.h
10973@@ -0,0 +1,494 @@
10974+/* Copyright 2013-2015 Freescale Semiconductor Inc.
10975+ *
10976+ * Redistribution and use in source and binary forms, with or without
10977+ * modification, are permitted provided that the following conditions are met:
10978+ * * Redistributions of source code must retain the above copyright
10979+ * notice, this list of conditions and the following disclaimer.
10980+ * * Redistributions in binary form must reproduce the above copyright
10981+ * notice, this list of conditions and the following disclaimer in the
10982+ * documentation and/or other materials provided with the distribution.
10983+ * * Neither the name of the above-listed copyright holders nor the
10984+ * names of any contributors may be used to endorse or promote products
10985+ * derived from this software without specific prior written permission.
10986+ *
10987+ *
10988+ * ALTERNATIVELY, this software may be distributed under the terms of the
10989+ * GNU General Public License ("GPL") as published by the Free Software
10990+ * Foundation, either version 2 of that License or (at your option) any
10991+ * later version.
10992+ *
10993+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
10994+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10995+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10996+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
10997+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10998+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10999+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
11000+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
11001+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
11002+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
11003+ * POSSIBILITY OF SUCH DAMAGE.
11004+ */
11005+#ifndef __FSL_DPAIOP_H
11006+#define __FSL_DPAIOP_H
11007+
11008+struct fsl_mc_io;
11009+
11010+/* Data Path AIOP API
11011+ * Contains initialization APIs and runtime control APIs for DPAIOP
11012+ */
11013+
11014+/**
11015+ * dpaiop_open() - Open a control session for the specified object.
11016+ * @mc_io: Pointer to MC portal's I/O object
11017+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11018+ * @dpaiop_id: DPAIOP unique ID
11019+ * @token: Returned token; use in subsequent API calls
11020+ *
11021+ * This function can be used to open a control session for an
11022+ * already created object; an object may have been declared in
11023+ * the DPL or by calling the dpaiop_create function.
11024+ * This function returns a unique authentication token,
11025+ * associated with the specific object ID and the specific MC
11026+ * portal; this token must be used in all subsequent commands for
11027+ * this specific object
11028+ *
11029+ * Return: '0' on Success; Error code otherwise.
11030+ */
11031+int dpaiop_open(struct fsl_mc_io *mc_io,
11032+ uint32_t cmd_flags,
11033+ int dpaiop_id,
11034+ uint16_t *token);
11035+
11036+/**
11037+ * dpaiop_close() - Close the control session of the object
11038+ * @mc_io: Pointer to MC portal's I/O object
11039+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11040+ * @token: Token of DPAIOP object
11041+ *
11042+ * After this function is called, no further operations are
11043+ * allowed on the object without opening a new control session.
11044+ *
11045+ * Return: '0' on Success; Error code otherwise.
11046+ */
11047+int dpaiop_close(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token);
11048+
11049+/**
11050+ * struct dpaiop_cfg - Structure representing DPAIOP configuration
11051+ * @aiop_id: AIOP ID
11052+ * @aiop_container_id: AIOP container ID
11053+ */
11054+struct dpaiop_cfg {
11055+ int aiop_id;
11056+ int aiop_container_id;
11057+};
11058+
11059+/**
11060+ * dpaiop_create() - Create the DPAIOP object.
11061+ * @mc_io: Pointer to MC portal's I/O object
11062+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11063+ * @cfg: Configuration structure
11064+ * @token: Returned token; use in subsequent API calls
11065+ *
11066+ * Create the DPAIOP object, allocate required resources and
11067+ * perform required initialization.
11068+ *
11069+ * The object can be created either by declaring it in the
11070+ * DPL file, or by calling this function.
11071+ * This function returns a unique authentication token,
11072+ * associated with the specific object ID and the specific MC
11073+ * portal; this token must be used in all subsequent calls to
11074+ * this specific object. For objects that are created using the
11075+ * DPL file, call dpaiop_open function to get an authentication
11076+ * token first.
11077+ *
11078+ * Return: '0' on Success; Error code otherwise.
11079+ */
11080+int dpaiop_create(struct fsl_mc_io *mc_io,
11081+ uint32_t cmd_flags,
11082+ const struct dpaiop_cfg *cfg,
11083+ uint16_t *token);
11084+
11085+/**
11086+ * dpaiop_destroy() - Destroy the DPAIOP object and release all its resources.
11087+ * @mc_io: Pointer to MC portal's I/O object
11088+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11089+ * @token: Token of DPAIOP object
11090+ *
11091+ * Return: '0' on Success; error code otherwise.
11092+ */
11093+int dpaiop_destroy(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token);
11094+
11095+/**
11096+ * dpaiop_reset() - Reset the DPAIOP, returns the object to initial state.
11097+ * @mc_io: Pointer to MC portal's I/O object
11098+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11099+ * @token: Token of DPAIOP object
11100+ *
11101+ * Return: '0' on Success; Error code otherwise.
11102+ */
11103+int dpaiop_reset(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token);
11104+
11105+/**
11106+ * struct dpaiop_irq_cfg - IRQ configuration
11107+ * @addr: Address that must be written to signal a message-based interrupt
11108+ * @val: Value to write into irq_addr address
11109+ * @irq_num: A user defined number associated with this IRQ
11110+ */
11111+struct dpaiop_irq_cfg {
11112+ uint64_t addr;
11113+ uint32_t val;
11114+ int irq_num;
11115+};
11116+
11117+/**
11118+ * dpaiop_set_irq() - Set IRQ information for the DPAIOP to trigger an interrupt.
11119+ * @mc_io: Pointer to MC portal's I/O object
11120+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11121+ * @token: Token of DPAIOP object
11122+ * @irq_index: Identifies the interrupt index to configure
11123+ * @irq_cfg: IRQ configuration
11124+ *
11125+ * Return: '0' on Success; Error code otherwise.
11126+ */
11127+int dpaiop_set_irq(struct fsl_mc_io *mc_io,
11128+ uint32_t cmd_flags,
11129+ uint16_t token,
11130+ uint8_t irq_index,
11131+ struct dpaiop_irq_cfg *irq_cfg);
11132+
11133+/**
11134+ * dpaiop_get_irq() - Get IRQ information from the DPAIOP.
11135+ * @mc_io: Pointer to MC portal's I/O object
11136+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11137+ * @token: Token of DPAIOP object
11138+ * @irq_index: The interrupt index to configure
11139+ * @type: Interrupt type: 0 represents message interrupt
11140+ * type (both irq_addr and irq_val are valid)
11141+ * @irq_cfg: IRQ attributes
11142+ *
11143+ * Return: '0' on Success; Error code otherwise.
11144+ */
11145+int dpaiop_get_irq(struct fsl_mc_io *mc_io,
11146+ uint32_t cmd_flags,
11147+ uint16_t token,
11148+ uint8_t irq_index,
11149+ int *type,
11150+ struct dpaiop_irq_cfg *irq_cfg);
11151+
11152+/**
11153+ * dpaiop_set_irq_enable() - Set overall interrupt state.
11154+ * @mc_io: Pointer to MC portal's I/O object
11155+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11156+ * @token: Token of DPAIOP object
11157+ * @irq_index: The interrupt index to configure
11158+ * @en: Interrupt state - enable = 1, disable = 0
11159+ *
11160+ * Allows GPP software to control when interrupts are generated.
11161+ * Each interrupt can have up to 32 causes. The enable/disable control's the
11162+ * overall interrupt state. if the interrupt is disabled no causes will cause
11163+ * an interrupt.
11164+ *
11165+ * Return: '0' on Success; Error code otherwise.
11166+ */
11167+int dpaiop_set_irq_enable(struct fsl_mc_io *mc_io,
11168+ uint32_t cmd_flags,
11169+ uint16_t token,
11170+ uint8_t irq_index,
11171+ uint8_t en);
11172+
11173+/**
11174+ * dpaiop_get_irq_enable() - Get overall interrupt state
11175+ * @mc_io: Pointer to MC portal's I/O object
11176+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11177+ * @token: Token of DPAIOP object
11178+ * @irq_index: The interrupt index to configure
11179+ * @en: Returned interrupt state - enable = 1, disable = 0
11180+ *
11181+ * Return: '0' on Success; Error code otherwise.
11182+ */
11183+int dpaiop_get_irq_enable(struct fsl_mc_io *mc_io,
11184+ uint32_t cmd_flags,
11185+ uint16_t token,
11186+ uint8_t irq_index,
11187+ uint8_t *en);
11188+
11189+/**
11190+ * dpaiop_set_irq_mask() - Set interrupt mask.
11191+ * @mc_io: Pointer to MC portal's I/O object
11192+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11193+ * @token: Token of DPAIOP object
11194+ * @irq_index: The interrupt index to configure
11195+ * @mask: Event mask to trigger interrupt;
11196+ * each bit:
11197+ * 0 = ignore event
11198+ * 1 = consider event for asserting IRQ
11199+ *
11200+ * Every interrupt can have up to 32 causes and the interrupt model supports
11201+ * masking/unmasking each cause independently
11202+ *
11203+ * Return: '0' on Success; Error code otherwise.
11204+ */
11205+int dpaiop_set_irq_mask(struct fsl_mc_io *mc_io,
11206+ uint32_t cmd_flags,
11207+ uint16_t token,
11208+ uint8_t irq_index,
11209+ uint32_t mask);
11210+
11211+/**
11212+ * dpaiop_get_irq_mask() - Get interrupt mask.
11213+ * @mc_io: Pointer to MC portal's I/O object
11214+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11215+ * @token: Token of DPAIOP object
11216+ * @irq_index: The interrupt index to configure
11217+ * @mask: Returned event mask to trigger interrupt
11218+ *
11219+ * Every interrupt can have up to 32 causes and the interrupt model supports
11220+ * masking/unmasking each cause independently
11221+ *
11222+ * Return: '0' on Success; Error code otherwise.
11223+ */
11224+int dpaiop_get_irq_mask(struct fsl_mc_io *mc_io,
11225+ uint32_t cmd_flags,
11226+ uint16_t token,
11227+ uint8_t irq_index,
11228+ uint32_t *mask);
11229+
11230+/**
11231+ * dpaiop_get_irq_status() - Get the current status of any pending interrupts.
11232+ *
11233+ * @mc_io: Pointer to MC portal's I/O object
11234+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11235+ * @token: Token of DPAIOP object
11236+ * @irq_index: The interrupt index to configure
11237+ * @status: Returned interrupts status - one bit per cause:
11238+ * 0 = no interrupt pending
11239+ * 1 = interrupt pending
11240+ *
11241+ * Return: '0' on Success; Error code otherwise.
11242+ */
11243+int dpaiop_get_irq_status(struct fsl_mc_io *mc_io,
11244+ uint32_t cmd_flags,
11245+ uint16_t token,
11246+ uint8_t irq_index,
11247+ uint32_t *status);
11248+
11249+/**
11250+ * dpaiop_clear_irq_status() - Clear a pending interrupt's status
11251+ *
11252+ * @mc_io: Pointer to MC portal's I/O object
11253+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11254+ * @token: Token of DPAIOP object
11255+ * @irq_index: The interrupt index to configure
11256+ * @status: Bits to clear (W1C) - one bit per cause:
11257+ * 0 = don't change
11258+ * 1 = clear status bit
11259+ *
11260+ * Return: '0' on Success; Error code otherwise.
11261+ */
11262+int dpaiop_clear_irq_status(struct fsl_mc_io *mc_io,
11263+ uint32_t cmd_flags,
11264+ uint16_t token,
11265+ uint8_t irq_index,
11266+ uint32_t status);
11267+
11268+/**
11269+ * struct dpaiop_attr - Structure representing DPAIOP attributes
11270+ * @id: AIOP ID
11271+ * @version: DPAIOP version
11272+ */
11273+struct dpaiop_attr {
11274+ int id;
11275+ /**
11276+ * struct version - Structure representing DPAIOP version
11277+ * @major: DPAIOP major version
11278+ * @minor: DPAIOP minor version
11279+ */
11280+ struct {
11281+ uint16_t major;
11282+ uint16_t minor;
11283+ } version;
11284+};
11285+
11286+/**
11287+ * dpaiop_get_attributes - Retrieve DPAIOP attributes.
11288+ *
11289+ * @mc_io: Pointer to MC portal's I/O object
11290+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11291+ * @token: Token of DPAIOP object
11292+ * @attr: Returned object's attributes
11293+ *
11294+ * Return: '0' on Success; Error code otherwise.
11295+ */
11296+int dpaiop_get_attributes(struct fsl_mc_io *mc_io,
11297+ uint32_t cmd_flags,
11298+ uint16_t token,
11299+ struct dpaiop_attr *attr);
11300+
11301+/**
11302+ * struct dpaiop_load_cfg - AIOP load configuration
11303+ * @options: AIOP load options
11304+ * @img_iova: I/O virtual address of AIOP ELF image
11305+ * @img_size: Size of AIOP ELF image in memory (in bytes)
11306+ */
11307+struct dpaiop_load_cfg {
11308+ uint64_t options;
11309+ uint64_t img_iova;
11310+ uint32_t img_size;
11311+};
11312+
11313+/**
11314+ * dpaiop_load_aiop() - Loads an image to AIOP
11315+ * @mc_io: Pointer to MC portal's I/O object
11316+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11317+ * @token: Token of DPAIOP object
11318+ * @cfg: AIOP load configurations
11319+ *
11320+ * Return: '0' on Success; Error code otherwise.
11321+ */
11322+int dpaiop_load(struct fsl_mc_io *mc_io,
11323+ uint32_t cmd_flags,
11324+ uint16_t token,
11325+ struct dpaiop_load_cfg *cfg);
11326+
11327+#define DPAIOP_RUN_OPT_DEBUG 0x0000000000000001ULL
11328+
11329+/**
11330+ * struct dpaiop_run_cfg - AIOP run configuration
11331+ * @cores_mask: Mask of AIOP cores to run (core 0 in most significant bit)
11332+ * @options: Execution options (currently none defined)
11333+ * @args_iova: I/O virtual address of AIOP arguments
11334+ * @args_size: Size of AIOP arguments in memory (in bytes)
11335+ */
11336+struct dpaiop_run_cfg {
11337+ uint64_t cores_mask;
11338+ uint64_t options;
11339+ uint64_t args_iova;
11340+ uint32_t args_size;
11341+};
11342+
11343+/**
11344+ * dpaiop_run_aiop() - Starts AIOP execution
11345+ * @mc_io: Pointer to MC portal's I/O object
11346+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11347+ * @token: Token of DPAIOP object
11348+ * @cfg: AIOP run configuration
11349+ *
11350+ * Return: '0' on Success; Error code otherwise.
11351+ */
11352+int dpaiop_run(struct fsl_mc_io *mc_io,
11353+ uint32_t cmd_flags,
11354+ uint16_t token,
11355+ const struct dpaiop_run_cfg *cfg);
11356+
11357+/**
11358+ * struct dpaiop_sl_version - AIOP SL (Service Layer) version
11359+ * @major: AIOP SL major version number
11360+ * @minor: AIOP SL minor version number
11361+ * @revision: AIOP SL revision number
11362+ */
11363+struct dpaiop_sl_version {
11364+ uint32_t major;
11365+ uint32_t minor;
11366+ uint32_t revision;
11367+};
11368+
11369+/**
11370+ * dpaiop_get_sl_version() - Get AIOP SL (Service Layer) version
11371+ * @mc_io: Pointer to MC portal's I/O object
11372+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11373+ * @token: Token of DPAIOP object
11374+ * @version: AIOP SL version number
11375+ *
11376+ * Return: '0' on Success; Error code otherwise.
11377+ */
11378+int dpaiop_get_sl_version(struct fsl_mc_io *mc_io,
11379+ uint32_t cmd_flags,
11380+ uint16_t token,
11381+ struct dpaiop_sl_version *version);
11382+
11383+/**
11384+ * AIOP states
11385+ *
11386+ * AIOP internal states, can be retrieved by calling dpaiop_get_state() routine
11387+ */
11388+
11389+/**
11390+ * AIOP reset successfully completed.
11391+ */
11392+#define DPAIOP_STATE_RESET_DONE 0x00000000
11393+/**
11394+ * AIOP reset is ongoing.
11395+ */
11396+#define DPAIOP_STATE_RESET_ONGOING 0x00000001
11397+
11398+/**
11399+ * AIOP image loading successfully completed.
11400+ */
11401+#define DPAIOP_STATE_LOAD_DONE 0x00000002
11402+/**
11403+ * AIOP image loading is ongoing.
11404+ */
11405+#define DPAIOP_STATE_LOAD_ONGIONG 0x00000004
11406+/**
11407+ * AIOP image loading completed with error.
11408+ */
11409+#define DPAIOP_STATE_LOAD_ERROR 0x00000008
11410+
11411+/**
11412+ * Boot process of AIOP cores is ongoing.
11413+ */
11414+#define DPAIOP_STATE_BOOT_ONGOING 0x00000010
11415+/**
11416+ * Boot process of AIOP cores completed with an error.
11417+ */
11418+#define DPAIOP_STATE_BOOT_ERROR 0x00000020
11419+/**
11420+ * AIOP cores are functional and running
11421+ */
11422+#define DPAIOP_STATE_RUNNING 0x00000040
11423+/** @} */
11424+
11425+/**
11426+ * dpaiop_get_state() - Get AIOP state
11427+ * @mc_io: Pointer to MC portal's I/O object
11428+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11429+ * @token: Token of DPAIOP object
11430+ * @state: AIOP state
11431+ *
11432+ * Return: '0' on Success; Error code otherwise.
11433+ */
11434+int dpaiop_get_state(struct fsl_mc_io *mc_io,
11435+ uint32_t cmd_flags,
11436+ uint16_t token,
11437+ uint32_t *state);
11438+
11439+/**
11440+ * dpaiop_set_time_of_day() - Set AIOP internal time-of-day
11441+ * @mc_io: Pointer to MC portal's I/O object
11442+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11443+ * @token: Token of DPAIOP object
11444+ * @time_of_day: Current number of milliseconds since the Epoch
11445+ *
11446+ * Return: '0' on Success; Error code otherwise.
11447+ */
11448+int dpaiop_set_time_of_day(struct fsl_mc_io *mc_io,
11449+ uint32_t cmd_flags,
11450+ uint16_t token,
11451+ uint64_t time_of_day);
11452+
11453+/**
11454+ * dpaiop_get_time_of_day() - Get AIOP internal time-of-day
11455+ * @mc_io: Pointer to MC portal's I/O object
11456+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11457+ * @token: Token of DPAIOP object
11458+ * @time_of_day: Current number of milliseconds since the Epoch
11459+ *
11460+ * Return: '0' on Success; Error code otherwise.
11461+ */
11462+int dpaiop_get_time_of_day(struct fsl_mc_io *mc_io,
11463+ uint32_t cmd_flags,
11464+ uint16_t token,
11465+ uint64_t *time_of_day);
11466+
11467+#endif /* __FSL_DPAIOP_H */
11468diff --git a/drivers/net/dpaa2/mc/fsl_dpaiop_cmd.h b/drivers/net/dpaa2/mc/fsl_dpaiop_cmd.h
11469new file mode 100644
11470index 0000000..5b77bb8
11471--- /dev/null
11472+++ b/drivers/net/dpaa2/mc/fsl_dpaiop_cmd.h
11473@@ -0,0 +1,190 @@
11474+/* Copyright 2013-2015 Freescale Semiconductor Inc.
11475+ *
11476+ * Redistribution and use in source and binary forms, with or without
11477+ * modification, are permitted provided that the following conditions are met:
11478+ * * Redistributions of source code must retain the above copyright
11479+ * notice, this list of conditions and the following disclaimer.
11480+ * * Redistributions in binary form must reproduce the above copyright
11481+ * notice, this list of conditions and the following disclaimer in the
11482+ * documentation and/or other materials provided with the distribution.
11483+ * * Neither the name of the above-listed copyright holders nor the
11484+ * names of any contributors may be used to endorse or promote products
11485+ * derived from this software without specific prior written permission.
11486+ *
11487+ *
11488+ * ALTERNATIVELY, this software may be distributed under the terms of the
11489+ * GNU General Public License ("GPL") as published by the Free Software
11490+ * Foundation, either version 2 of that License or (at your option) any
11491+ * later version.
11492+ *
11493+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
11494+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
11495+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
11496+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
11497+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
11498+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
11499+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
11500+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
11501+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
11502+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
11503+ * POSSIBILITY OF SUCH DAMAGE.
11504+ */
11505+#ifndef _FSL_DPAIOP_CMD_H
11506+#define _FSL_DPAIOP_CMD_H
11507+
11508+/* DPAIOP Version */
11509+#define DPAIOP_VER_MAJOR 1
11510+#define DPAIOP_VER_MINOR 2
11511+
11512+/* Command IDs */
11513+#define DPAIOP_CMDID_CLOSE 0x800
11514+#define DPAIOP_CMDID_OPEN 0x80a
11515+#define DPAIOP_CMDID_CREATE 0x90a
11516+#define DPAIOP_CMDID_DESTROY 0x900
11517+
11518+#define DPAIOP_CMDID_GET_ATTR 0x004
11519+#define DPAIOP_CMDID_RESET 0x005
11520+
11521+#define DPAIOP_CMDID_SET_IRQ 0x010
11522+#define DPAIOP_CMDID_GET_IRQ 0x011
11523+#define DPAIOP_CMDID_SET_IRQ_ENABLE 0x012
11524+#define DPAIOP_CMDID_GET_IRQ_ENABLE 0x013
11525+#define DPAIOP_CMDID_SET_IRQ_MASK 0x014
11526+#define DPAIOP_CMDID_GET_IRQ_MASK 0x015
11527+#define DPAIOP_CMDID_GET_IRQ_STATUS 0x016
11528+#define DPAIOP_CMDID_CLEAR_IRQ_STATUS 0x017
11529+
11530+#define DPAIOP_CMDID_LOAD 0x280
11531+#define DPAIOP_CMDID_RUN 0x281
11532+#define DPAIOP_CMDID_GET_SL_VERSION 0x282
11533+#define DPAIOP_CMDID_GET_STATE 0x283
11534+#define DPAIOP_CMDID_SET_TIME_OF_DAY 0x284
11535+#define DPAIOP_CMDID_GET_TIME_OF_DAY 0x285
11536+
11537+/* cmd, param, offset, width, type, arg_name */
11538+#define DPAIOP_CMD_OPEN(cmd, dpaiop_id) \
11539+ MC_CMD_OP(cmd, 0, 0, 32, int, dpaiop_id)
11540+
11541+/* cmd, param, offset, width, type, arg_name */
11542+#define DPAIOP_CMD_CREATE(cmd, cfg) \
11543+do { \
11544+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->aiop_id);\
11545+ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->aiop_container_id);\
11546+} while (0)
11547+
11548+/* cmd, param, offset, width, type, arg_name */
11549+#define DPAIOP_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
11550+do { \
11551+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
11552+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
11553+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
11554+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
11555+} while (0)
11556+
11557+/* cmd, param, offset, width, type, arg_name */
11558+#define DPAIOP_CMD_GET_IRQ(cmd, irq_index) \
11559+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
11560+
11561+/* cmd, param, offset, width, type, arg_name */
11562+#define DPAIOP_RSP_GET_IRQ(cmd, type, irq_cfg) \
11563+do { \
11564+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
11565+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
11566+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
11567+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
11568+} while (0)
11569+
11570+/* cmd, param, offset, width, type, arg_name */
11571+#define DPAIOP_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \
11572+do { \
11573+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \
11574+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
11575+} while (0)
11576+
11577+/* cmd, param, offset, width, type, arg_name */
11578+#define DPAIOP_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
11579+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
11580+
11581+/* cmd, param, offset, width, type, arg_name */
11582+#define DPAIOP_RSP_GET_IRQ_ENABLE(cmd, en) \
11583+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en)
11584+
11585+/* cmd, param, offset, width, type, arg_name */
11586+#define DPAIOP_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
11587+do { \
11588+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask);\
11589+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
11590+} while (0)
11591+
11592+/* cmd, param, offset, width, type, arg_name */
11593+#define DPAIOP_CMD_GET_IRQ_MASK(cmd, irq_index) \
11594+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
11595+
11596+/* cmd, param, offset, width, type, arg_name */
11597+#define DPAIOP_RSP_GET_IRQ_MASK(cmd, mask) \
11598+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
11599+
11600+/* cmd, param, offset, width, type, arg_name */
11601+#define DPAIOP_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
11602+do { \
11603+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
11604+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
11605+} while (0)
11606+
11607+/* cmd, param, offset, width, type, arg_name */
11608+#define DPAIOP_RSP_GET_IRQ_STATUS(cmd, status) \
11609+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
11610+
11611+/* cmd, param, offset, width, type, arg_name */
11612+#define DPAIOP_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
11613+do { \
11614+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
11615+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
11616+} while (0)
11617+
11618+/* cmd, param, offset, width, type, arg_name */
11619+#define DPAIOP_RSP_GET_ATTRIBUTES(cmd, attr) \
11620+do { \
11621+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\
11622+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
11623+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
11624+} while (0)
11625+
11626+/* cmd, param, offset, width, type, arg_name */
11627+#define DPAIOP_CMD_LOAD(cmd, cfg) \
11628+do { \
11629+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->img_size); \
11630+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->img_iova); \
11631+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options); \
11632+} while (0)
11633+
11634+/* cmd, param, offset, width, type, arg_name */
11635+#define DPAIOP_CMD_RUN(cmd, cfg) \
11636+do { \
11637+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, cfg->args_size); \
11638+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->cores_mask); \
11639+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options); \
11640+ MC_CMD_OP(cmd, 3, 0, 64, uint64_t, cfg->args_iova); \
11641+} while (0)
11642+
11643+/* cmd, param, offset, width, type, arg_name */
11644+#define DPAIOP_RSP_GET_SL_VERSION(cmd, version) \
11645+do { \
11646+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, version->major);\
11647+ MC_RSP_OP(cmd, 0, 32, 32, uint32_t, version->minor);\
11648+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, version->revision);\
11649+} while (0)
11650+
11651+/* cmd, param, offset, width, type, arg_name */
11652+#define DPAIOP_RSP_GET_STATE(cmd, state) \
11653+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, state)
11654+
11655+/* cmd, param, offset, width, type, arg_name */
11656+#define DPAIOP_CMD_SET_TIME_OF_DAY(cmd, time_of_day) \
11657+ MC_CMD_OP(cmd, 0, 0, 64, uint64_t, time_of_day)
11658+
11659+/* cmd, param, offset, width, type, arg_name */
11660+#define DPAIOP_RSP_GET_TIME_OF_DAY(cmd, time_of_day) \
11661+ MC_RSP_OP(cmd, 0, 0, 64, uint64_t, time_of_day)
11662+
11663+#endif /* _FSL_DPAIOP_CMD_H */
11664diff --git a/drivers/net/dpaa2/mc/fsl_dpbp.h b/drivers/net/dpaa2/mc/fsl_dpbp.h
11665new file mode 100644
11666index 0000000..9856bb8
11667--- /dev/null
11668+++ b/drivers/net/dpaa2/mc/fsl_dpbp.h
11669@@ -0,0 +1,438 @@
11670+/* Copyright 2013-2015 Freescale Semiconductor Inc.
11671+ *
11672+ * Redistribution and use in source and binary forms, with or without
11673+ * modification, are permitted provided that the following conditions are met:
11674+ * * Redistributions of source code must retain the above copyright
11675+ * notice, this list of conditions and the following disclaimer.
11676+ * * Redistributions in binary form must reproduce the above copyright
11677+ * notice, this list of conditions and the following disclaimer in the
11678+ * documentation and/or other materials provided with the distribution.
11679+ * * Neither the name of the above-listed copyright holders nor the
11680+ * names of any contributors may be used to endorse or promote products
11681+ * derived from this software without specific prior written permission.
11682+ *
11683+ *
11684+ * ALTERNATIVELY, this software may be distributed under the terms of the
11685+ * GNU General Public License ("GPL") as published by the Free Software
11686+ * Foundation, either version 2 of that License or (at your option) any
11687+ * later version.
11688+ *
11689+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
11690+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
11691+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
11692+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
11693+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
11694+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
11695+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
11696+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
11697+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
11698+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
11699+ * POSSIBILITY OF SUCH DAMAGE.
11700+ */
11701+#ifndef __FSL_DPBP_H
11702+#define __FSL_DPBP_H
11703+
11704+/* Data Path Buffer Pool API
11705+ * Contains initialization APIs and runtime control APIs for DPBP
11706+ */
11707+
11708+struct fsl_mc_io;
11709+
11710+/**
11711+ * dpbp_open() - Open a control session for the specified object.
11712+ * @mc_io: Pointer to MC portal's I/O object
11713+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11714+ * @dpbp_id: DPBP unique ID
11715+ * @token: Returned token; use in subsequent API calls
11716+ *
11717+ * This function can be used to open a control session for an
11718+ * already created object; an object may have been declared in
11719+ * the DPL or by calling the dpbp_create function.
11720+ * This function returns a unique authentication token,
11721+ * associated with the specific object ID and the specific MC
11722+ * portal; this token must be used in all subsequent commands for
11723+ * this specific object
11724+ *
11725+ * Return: '0' on Success; Error code otherwise.
11726+ */
11727+int dpbp_open(struct fsl_mc_io *mc_io,
11728+ uint32_t cmd_flags,
11729+ int dpbp_id,
11730+ uint16_t *token);
11731+
11732+/**
11733+ * dpbp_close() - Close the control session of the object
11734+ * @mc_io: Pointer to MC portal's I/O object
11735+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11736+ * @token: Token of DPBP object
11737+ *
11738+ * After this function is called, no further operations are
11739+ * allowed on the object without opening a new control session.
11740+ *
11741+ * Return: '0' on Success; Error code otherwise.
11742+ */
11743+int dpbp_close(struct fsl_mc_io *mc_io,
11744+ uint32_t cmd_flags,
11745+ uint16_t token);
11746+
11747+/**
11748+ * struct dpbp_cfg - Structure representing DPBP configuration
11749+ * @options: place holder
11750+ */
11751+struct dpbp_cfg {
11752+ uint32_t options;
11753+};
11754+
11755+/**
11756+ * dpbp_create() - Create the DPBP object.
11757+ * @mc_io: Pointer to MC portal's I/O object
11758+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11759+ * @cfg: Configuration structure
11760+ * @token: Returned token; use in subsequent API calls
11761+ *
11762+ * Create the DPBP object, allocate required resources and
11763+ * perform required initialization.
11764+ *
11765+ * The object can be created either by declaring it in the
11766+ * DPL file, or by calling this function.
11767+ * This function returns a unique authentication token,
11768+ * associated with the specific object ID and the specific MC
11769+ * portal; this token must be used in all subsequent calls to
11770+ * this specific object. For objects that are created using the
11771+ * DPL file, call dpbp_open function to get an authentication
11772+ * token first.
11773+ *
11774+ * Return: '0' on Success; Error code otherwise.
11775+ */
11776+int dpbp_create(struct fsl_mc_io *mc_io,
11777+ uint32_t cmd_flags,
11778+ const struct dpbp_cfg *cfg,
11779+ uint16_t *token);
11780+
11781+/**
11782+ * dpbp_destroy() - Destroy the DPBP object and release all its resources.
11783+ * @mc_io: Pointer to MC portal's I/O object
11784+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11785+ * @token: Token of DPBP object
11786+ *
11787+ * Return: '0' on Success; error code otherwise.
11788+ */
11789+int dpbp_destroy(struct fsl_mc_io *mc_io,
11790+ uint32_t cmd_flags,
11791+ uint16_t token);
11792+
11793+/**
11794+ * dpbp_enable() - Enable the DPBP.
11795+ * @mc_io: Pointer to MC portal's I/O object
11796+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11797+ * @token: Token of DPBP object
11798+ *
11799+ * Return: '0' on Success; Error code otherwise.
11800+ */
11801+int dpbp_enable(struct fsl_mc_io *mc_io,
11802+ uint32_t cmd_flags,
11803+ uint16_t token);
11804+
11805+/**
11806+ * dpbp_disable() - Disable the DPBP.
11807+ * @mc_io: Pointer to MC portal's I/O object
11808+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11809+ * @token: Token of DPBP object
11810+ *
11811+ * Return: '0' on Success; Error code otherwise.
11812+ */
11813+int dpbp_disable(struct fsl_mc_io *mc_io,
11814+ uint32_t cmd_flags,
11815+ uint16_t token);
11816+
11817+/**
11818+ * dpbp_is_enabled() - Check if the DPBP is enabled.
11819+ * @mc_io: Pointer to MC portal's I/O object
11820+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11821+ * @token: Token of DPBP object
11822+ * @en: Returns '1' if object is enabled; '0' otherwise
11823+ *
11824+ * Return: '0' on Success; Error code otherwise.
11825+ */
11826+int dpbp_is_enabled(struct fsl_mc_io *mc_io,
11827+ uint32_t cmd_flags,
11828+ uint16_t token,
11829+ int *en);
11830+
11831+/**
11832+ * dpbp_reset() - Reset the DPBP, returns the object to initial state.
11833+ * @mc_io: Pointer to MC portal's I/O object
11834+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11835+ * @token: Token of DPBP object
11836+ *
11837+ * Return: '0' on Success; Error code otherwise.
11838+ */
11839+int dpbp_reset(struct fsl_mc_io *mc_io,
11840+ uint32_t cmd_flags,
11841+ uint16_t token);
11842+
11843+/**
11844+ * struct dpbp_irq_cfg - IRQ configuration
11845+ * @addr: Address that must be written to signal a message-based interrupt
11846+ * @val: Value to write into irq_addr address
11847+ * @irq_num: A user defined number associated with this IRQ
11848+ */
11849+struct dpbp_irq_cfg {
11850+ uint64_t addr;
11851+ uint32_t val;
11852+ int irq_num;
11853+};
11854+
11855+/**
11856+ * dpbp_set_irq() - Set IRQ information for the DPBP to trigger an interrupt.
11857+ * @mc_io: Pointer to MC portal's I/O object
11858+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11859+ * @token: Token of DPBP object
11860+ * @irq_index: Identifies the interrupt index to configure
11861+ * @irq_cfg: IRQ configuration
11862+ *
11863+ * Return: '0' on Success; Error code otherwise.
11864+ */
11865+int dpbp_set_irq(struct fsl_mc_io *mc_io,
11866+ uint32_t cmd_flags,
11867+ uint16_t token,
11868+ uint8_t irq_index,
11869+ struct dpbp_irq_cfg *irq_cfg);
11870+
11871+/**
11872+ * dpbp_get_irq() - Get IRQ information from the DPBP.
11873+ * @mc_io: Pointer to MC portal's I/O object
11874+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11875+ * @token: Token of DPBP object
11876+ * @irq_index: The interrupt index to configure
11877+ * @type: Interrupt type: 0 represents message interrupt
11878+ * type (both irq_addr and irq_val are valid)
11879+ * @irq_cfg: IRQ attributes
11880+ *
11881+ * Return: '0' on Success; Error code otherwise.
11882+ */
11883+int dpbp_get_irq(struct fsl_mc_io *mc_io,
11884+ uint32_t cmd_flags,
11885+ uint16_t token,
11886+ uint8_t irq_index,
11887+ int *type,
11888+ struct dpbp_irq_cfg *irq_cfg);
11889+
11890+/**
11891+ * dpbp_set_irq_enable() - Set overall interrupt state.
11892+ * @mc_io: Pointer to MC portal's I/O object
11893+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11894+ * @token: Token of DPBP object
11895+ * @irq_index: The interrupt index to configure
11896+ * @en: Interrupt state - enable = 1, disable = 0
11897+ *
11898+ * Allows GPP software to control when interrupts are generated.
11899+ * Each interrupt can have up to 32 causes. The enable/disable control's the
11900+ * overall interrupt state. if the interrupt is disabled no causes will cause
11901+ * an interrupt.
11902+ *
11903+ * Return: '0' on Success; Error code otherwise.
11904+ */
11905+int dpbp_set_irq_enable(struct fsl_mc_io *mc_io,
11906+ uint32_t cmd_flags,
11907+ uint16_t token,
11908+ uint8_t irq_index,
11909+ uint8_t en);
11910+
11911+/**
11912+ * dpbp_get_irq_enable() - Get overall interrupt state
11913+ * @mc_io: Pointer to MC portal's I/O object
11914+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11915+ * @token: Token of DPBP object
11916+ * @irq_index: The interrupt index to configure
11917+ * @en: Returned interrupt state - enable = 1, disable = 0
11918+ *
11919+ * Return: '0' on Success; Error code otherwise.
11920+ */
11921+int dpbp_get_irq_enable(struct fsl_mc_io *mc_io,
11922+ uint32_t cmd_flags,
11923+ uint16_t token,
11924+ uint8_t irq_index,
11925+ uint8_t *en);
11926+
11927+/**
11928+ * dpbp_set_irq_mask() - Set interrupt mask.
11929+ * @mc_io: Pointer to MC portal's I/O object
11930+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11931+ * @token: Token of DPBP object
11932+ * @irq_index: The interrupt index to configure
11933+ * @mask: Event mask to trigger interrupt;
11934+ * each bit:
11935+ * 0 = ignore event
11936+ * 1 = consider event for asserting IRQ
11937+ *
11938+ * Every interrupt can have up to 32 causes and the interrupt model supports
11939+ * masking/unmasking each cause independently
11940+ *
11941+ * Return: '0' on Success; Error code otherwise.
11942+ */
11943+int dpbp_set_irq_mask(struct fsl_mc_io *mc_io,
11944+ uint32_t cmd_flags,
11945+ uint16_t token,
11946+ uint8_t irq_index,
11947+ uint32_t mask);
11948+
11949+/**
11950+ * dpbp_get_irq_mask() - Get interrupt mask.
11951+ * @mc_io: Pointer to MC portal's I/O object
11952+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11953+ * @token: Token of DPBP object
11954+ * @irq_index: The interrupt index to configure
11955+ * @mask: Returned event mask to trigger interrupt
11956+ *
11957+ * Every interrupt can have up to 32 causes and the interrupt model supports
11958+ * masking/unmasking each cause independently
11959+ *
11960+ * Return: '0' on Success; Error code otherwise.
11961+ */
11962+int dpbp_get_irq_mask(struct fsl_mc_io *mc_io,
11963+ uint32_t cmd_flags,
11964+ uint16_t token,
11965+ uint8_t irq_index,
11966+ uint32_t *mask);
11967+
11968+/**
11969+ * dpbp_get_irq_status() - Get the current status of any pending interrupts.
11970+ *
11971+ * @mc_io: Pointer to MC portal's I/O object
11972+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11973+ * @token: Token of DPBP object
11974+ * @irq_index: The interrupt index to configure
11975+ * @status: Returned interrupts status - one bit per cause:
11976+ * 0 = no interrupt pending
11977+ * 1 = interrupt pending
11978+ *
11979+ * Return: '0' on Success; Error code otherwise.
11980+ */
11981+int dpbp_get_irq_status(struct fsl_mc_io *mc_io,
11982+ uint32_t cmd_flags,
11983+ uint16_t token,
11984+ uint8_t irq_index,
11985+ uint32_t *status);
11986+
11987+/**
11988+ * dpbp_clear_irq_status() - Clear a pending interrupt's status
11989+ *
11990+ * @mc_io: Pointer to MC portal's I/O object
11991+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
11992+ * @token: Token of DPBP object
11993+ * @irq_index: The interrupt index to configure
11994+ * @status: Bits to clear (W1C) - one bit per cause:
11995+ * 0 = don't change
11996+ * 1 = clear status bit
11997+ *
11998+ * Return: '0' on Success; Error code otherwise.
11999+ */
12000+int dpbp_clear_irq_status(struct fsl_mc_io *mc_io,
12001+ uint32_t cmd_flags,
12002+ uint16_t token,
12003+ uint8_t irq_index,
12004+ uint32_t status);
12005+
12006+/**
12007+ * struct dpbp_attr - Structure representing DPBP attributes
12008+ * @id: DPBP object ID
12009+ * @version: DPBP version
12010+ * @bpid: Hardware buffer pool ID; should be used as an argument in
12011+ * acquire/release operations on buffers
12012+ */
12013+struct dpbp_attr {
12014+ int id;
12015+ /**
12016+ * struct version - Structure representing DPBP version
12017+ * @major: DPBP major version
12018+ * @minor: DPBP minor version
12019+ */
12020+ struct {
12021+ uint16_t major;
12022+ uint16_t minor;
12023+ } version;
12024+ uint16_t bpid;
12025+};
12026+
12027+/**
12028+ * dpbp_get_attributes - Retrieve DPBP attributes.
12029+ *
12030+ * @mc_io: Pointer to MC portal's I/O object
12031+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12032+ * @token: Token of DPBP object
12033+ * @attr: Returned object's attributes
12034+ *
12035+ * Return: '0' on Success; Error code otherwise.
12036+ */
12037+int dpbp_get_attributes(struct fsl_mc_io *mc_io,
12038+ uint32_t cmd_flags,
12039+ uint16_t token,
12040+ struct dpbp_attr *attr);
12041+
12042+/**
12043+ * DPBP notifications options
12044+ */
12045+
12046+/**
12047+ * BPSCN write will attempt to allocate into a cache (coherent write)
12048+ */
12049+#define DPBP_NOTIF_OPT_COHERENT_WRITE 0x00000001
12050+
12051+/**
12052+ * struct dpbp_notification_cfg - Structure representing DPBP notifications
12053+ * towards software
12054+ * @depletion_entry: below this threshold the pool is "depleted";
12055+ * set it to '0' to disable it
12056+ * @depletion_exit: greater than or equal to this threshold the pool exit its
12057+ * "depleted" state
12058+ * @surplus_entry: above this threshold the pool is in "surplus" state;
12059+ * set it to '0' to disable it
12060+ * @surplus_exit: less than or equal to this threshold the pool exit its
12061+ * "surplus" state
12062+ * @message_iova: MUST be given if either 'depletion_entry' or 'surplus_entry'
12063+ * is not '0' (enable); I/O virtual address (must be in DMA-able memory),
12064+ * must be 16B aligned.
12065+ * @message_ctx: The context that will be part of the BPSCN message and will
12066+ * be written to 'message_iova'
12067+ * @options: Mask of available options; use 'DPBP_NOTIF_OPT_<X>' values
12068+ */
12069+struct dpbp_notification_cfg {
12070+ uint32_t depletion_entry;
12071+ uint32_t depletion_exit;
12072+ uint32_t surplus_entry;
12073+ uint32_t surplus_exit;
12074+ uint64_t message_iova;
12075+ uint64_t message_ctx;
12076+ uint16_t options;
12077+};
12078+
12079+/**
12080+ * dpbp_set_notifications() - Set notifications towards software
12081+ * @mc_io: Pointer to MC portal's I/O object
12082+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12083+ * @token: Token of DPBP object
12084+ * @cfg: notifications configuration
12085+ *
12086+ * Return: '0' on Success; Error code otherwise.
12087+ */
12088+int dpbp_set_notifications(struct fsl_mc_io *mc_io,
12089+ uint32_t cmd_flags,
12090+ uint16_t token,
12091+ struct dpbp_notification_cfg *cfg);
12092+
12093+/**
12094+ * dpbp_get_notifications() - Get the notifications configuration
12095+ * @mc_io: Pointer to MC portal's I/O object
12096+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12097+ * @token: Token of DPBP object
12098+ * @cfg: notifications configuration
12099+ *
12100+ * Return: '0' on Success; Error code otherwise.
12101+ */
12102+int dpbp_get_notifications(struct fsl_mc_io *mc_io,
12103+ uint32_t cmd_flags,
12104+ uint16_t token,
12105+ struct dpbp_notification_cfg *cfg);
12106+
12107+#endif /* __FSL_DPBP_H */
12108diff --git a/drivers/net/dpaa2/mc/fsl_dpbp_cmd.h b/drivers/net/dpaa2/mc/fsl_dpbp_cmd.h
12109new file mode 100644
12110index 0000000..71ad96a
12111--- /dev/null
12112+++ b/drivers/net/dpaa2/mc/fsl_dpbp_cmd.h
12113@@ -0,0 +1,172 @@
12114+/* Copyright 2013-2015 Freescale Semiconductor Inc.
12115+ *
12116+ * Redistribution and use in source and binary forms, with or without
12117+ * modification, are permitted provided that the following conditions are met:
12118+ * * Redistributions of source code must retain the above copyright
12119+ * notice, this list of conditions and the following disclaimer.
12120+ * * Redistributions in binary form must reproduce the above copyright
12121+ * notice, this list of conditions and the following disclaimer in the
12122+ * documentation and/or other materials provided with the distribution.
12123+ * * Neither the name of the above-listed copyright holders nor the
12124+ * names of any contributors may be used to endorse or promote products
12125+ * derived from this software without specific prior written permission.
12126+ *
12127+ *
12128+ * ALTERNATIVELY, this software may be distributed under the terms of the
12129+ * GNU General Public License ("GPL") as published by the Free Software
12130+ * Foundation, either version 2 of that License or (at your option) any
12131+ * later version.
12132+ *
12133+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
12134+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
12135+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
12136+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
12137+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
12138+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
12139+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
12140+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
12141+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
12142+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
12143+ * POSSIBILITY OF SUCH DAMAGE.
12144+ */
12145+#ifndef _FSL_DPBP_CMD_H
12146+#define _FSL_DPBP_CMD_H
12147+
12148+/* DPBP Version */
12149+#define DPBP_VER_MAJOR 2
12150+#define DPBP_VER_MINOR 2
12151+
12152+/* Command IDs */
12153+#define DPBP_CMDID_CLOSE 0x800
12154+#define DPBP_CMDID_OPEN 0x804
12155+#define DPBP_CMDID_CREATE 0x904
12156+#define DPBP_CMDID_DESTROY 0x900
12157+
12158+#define DPBP_CMDID_ENABLE 0x002
12159+#define DPBP_CMDID_DISABLE 0x003
12160+#define DPBP_CMDID_GET_ATTR 0x004
12161+#define DPBP_CMDID_RESET 0x005
12162+#define DPBP_CMDID_IS_ENABLED 0x006
12163+
12164+#define DPBP_CMDID_SET_IRQ 0x010
12165+#define DPBP_CMDID_GET_IRQ 0x011
12166+#define DPBP_CMDID_SET_IRQ_ENABLE 0x012
12167+#define DPBP_CMDID_GET_IRQ_ENABLE 0x013
12168+#define DPBP_CMDID_SET_IRQ_MASK 0x014
12169+#define DPBP_CMDID_GET_IRQ_MASK 0x015
12170+#define DPBP_CMDID_GET_IRQ_STATUS 0x016
12171+#define DPBP_CMDID_CLEAR_IRQ_STATUS 0x017
12172+
12173+#define DPBP_CMDID_SET_NOTIFICATIONS 0x01b0
12174+#define DPBP_CMDID_GET_NOTIFICATIONS 0x01b1
12175+
12176+/* cmd, param, offset, width, type, arg_name */
12177+#define DPBP_CMD_OPEN(cmd, dpbp_id) \
12178+ MC_CMD_OP(cmd, 0, 0, 32, int, dpbp_id)
12179+
12180+/* cmd, param, offset, width, type, arg_name */
12181+#define DPBP_RSP_IS_ENABLED(cmd, en) \
12182+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
12183+
12184+/* cmd, param, offset, width, type, arg_name */
12185+#define DPBP_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
12186+do { \
12187+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
12188+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
12189+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
12190+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
12191+} while (0)
12192+
12193+/* cmd, param, offset, width, type, arg_name */
12194+#define DPBP_CMD_GET_IRQ(cmd, irq_index) \
12195+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
12196+
12197+/* cmd, param, offset, width, type, arg_name */
12198+#define DPBP_RSP_GET_IRQ(cmd, type, irq_cfg) \
12199+do { \
12200+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
12201+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
12202+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
12203+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
12204+} while (0)
12205+
12206+/* cmd, param, offset, width, type, arg_name */
12207+#define DPBP_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \
12208+do { \
12209+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \
12210+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
12211+} while (0)
12212+
12213+/* cmd, param, offset, width, type, arg_name */
12214+#define DPBP_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
12215+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
12216+
12217+/* cmd, param, offset, width, type, arg_name */
12218+#define DPBP_RSP_GET_IRQ_ENABLE(cmd, en) \
12219+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en)
12220+
12221+/* cmd, param, offset, width, type, arg_name */
12222+#define DPBP_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
12223+do { \
12224+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask);\
12225+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
12226+} while (0)
12227+
12228+/* cmd, param, offset, width, type, arg_name */
12229+#define DPBP_CMD_GET_IRQ_MASK(cmd, irq_index) \
12230+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
12231+
12232+/* cmd, param, offset, width, type, arg_name */
12233+#define DPBP_RSP_GET_IRQ_MASK(cmd, mask) \
12234+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
12235+
12236+/* cmd, param, offset, width, type, arg_name */
12237+#define DPBP_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
12238+do { \
12239+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
12240+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
12241+} while (0)
12242+/* cmd, param, offset, width, type, arg_name */
12243+#define DPBP_RSP_GET_IRQ_STATUS(cmd, status) \
12244+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
12245+
12246+/* cmd, param, offset, width, type, arg_name */
12247+#define DPBP_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
12248+do { \
12249+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
12250+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
12251+} while (0)
12252+
12253+/* cmd, param, offset, width, type, arg_name */
12254+#define DPBP_RSP_GET_ATTRIBUTES(cmd, attr) \
12255+do { \
12256+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->bpid); \
12257+ MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\
12258+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
12259+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
12260+} while (0)
12261+
12262+/* cmd, param, offset, width, type, arg_name */
12263+#define DPBP_CMD_SET_NOTIFICATIONS(cmd, cfg) \
12264+do { \
12265+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->depletion_entry); \
12266+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, cfg->depletion_exit);\
12267+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->surplus_entry);\
12268+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->surplus_exit);\
12269+ MC_CMD_OP(cmd, 2, 0, 16, uint16_t, cfg->options);\
12270+ MC_CMD_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx);\
12271+ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova);\
12272+} while (0)
12273+
12274+/* cmd, param, offset, width, type, arg_name */
12275+#define DPBP_CMD_GET_NOTIFICATIONS(cmd, cfg) \
12276+do { \
12277+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, cfg->depletion_entry); \
12278+ MC_RSP_OP(cmd, 0, 32, 32, uint32_t, cfg->depletion_exit);\
12279+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->surplus_entry);\
12280+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, cfg->surplus_exit);\
12281+ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, cfg->options);\
12282+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx);\
12283+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova);\
12284+} while (0)
12285+#endif /* _FSL_DPBP_CMD_H */
12286diff --git a/drivers/net/dpaa2/mc/fsl_dpci.h b/drivers/net/dpaa2/mc/fsl_dpci.h
12287new file mode 100644
12288index 0000000..d885935
12289--- /dev/null
12290+++ b/drivers/net/dpaa2/mc/fsl_dpci.h
12291@@ -0,0 +1,594 @@
12292+/* Copyright 2013-2015 Freescale Semiconductor Inc.
12293+ *
12294+ * Redistribution and use in source and binary forms, with or without
12295+ * modification, are permitted provided that the following conditions are met:
12296+ * * Redistributions of source code must retain the above copyright
12297+ * notice, this list of conditions and the following disclaimer.
12298+ * * Redistributions in binary form must reproduce the above copyright
12299+ * notice, this list of conditions and the following disclaimer in the
12300+ * documentation and/or other materials provided with the distribution.
12301+ * * Neither the name of the above-listed copyright holders nor the
12302+ * names of any contributors may be used to endorse or promote products
12303+ * derived from this software without specific prior written permission.
12304+ *
12305+ *
12306+ * ALTERNATIVELY, this software may be distributed under the terms of the
12307+ * GNU General Public License ("GPL") as published by the Free Software
12308+ * Foundation, either version 2 of that License or (at your option) any
12309+ * later version.
12310+ *
12311+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
12312+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
12313+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
12314+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
12315+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
12316+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
12317+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
12318+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
12319+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
12320+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
12321+ * POSSIBILITY OF SUCH DAMAGE.
12322+ */
12323+#ifndef __FSL_DPCI_H
12324+#define __FSL_DPCI_H
12325+
12326+/* Data Path Communication Interface API
12327+ * Contains initialization APIs and runtime control APIs for DPCI
12328+ */
12329+
12330+struct fsl_mc_io;
12331+
12332+/** General DPCI macros */
12333+
12334+/**
12335+ * Maximum number of Tx/Rx priorities per DPCI object
12336+ */
12337+#define DPCI_PRIO_NUM 2
12338+
12339+/**
12340+ * Indicates an invalid frame queue
12341+ */
12342+#define DPCI_FQID_NOT_VALID (uint32_t)(-1)
12343+
12344+/**
12345+ * All queues considered; see dpci_set_rx_queue()
12346+ */
12347+#define DPCI_ALL_QUEUES (uint8_t)(-1)
12348+
12349+/**
12350+ * dpci_open() - Open a control session for the specified object
12351+ * @mc_io: Pointer to MC portal's I/O object
12352+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12353+ * @dpci_id: DPCI unique ID
12354+ * @token: Returned token; use in subsequent API calls
12355+ *
12356+ * This function can be used to open a control session for an
12357+ * already created object; an object may have been declared in
12358+ * the DPL or by calling the dpci_create() function.
12359+ * This function returns a unique authentication token,
12360+ * associated with the specific object ID and the specific MC
12361+ * portal; this token must be used in all subsequent commands for
12362+ * this specific object.
12363+ *
12364+ * Return: '0' on Success; Error code otherwise.
12365+ */
12366+int dpci_open(struct fsl_mc_io *mc_io,
12367+ uint32_t cmd_flags,
12368+ int dpci_id,
12369+ uint16_t *token);
12370+
12371+/**
12372+ * dpci_close() - Close the control session of the object
12373+ * @mc_io: Pointer to MC portal's I/O object
12374+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12375+ * @token: Token of DPCI object
12376+ *
12377+ * After this function is called, no further operations are
12378+ * allowed on the object without opening a new control session.
12379+ *
12380+ * Return: '0' on Success; Error code otherwise.
12381+ */
12382+int dpci_close(struct fsl_mc_io *mc_io,
12383+ uint32_t cmd_flags,
12384+ uint16_t token);
12385+
12386+/**
12387+ * struct dpci_cfg - Structure representing DPCI configuration
12388+ * @num_of_priorities: Number of receive priorities (queues) for the DPCI;
12389+ * note, that the number of transmit priorities (queues)
12390+ * is determined by the number of receive priorities of
12391+ * the peer DPCI object
12392+ */
12393+struct dpci_cfg {
12394+ uint8_t num_of_priorities;
12395+};
12396+
12397+/**
12398+ * dpci_create() - Create the DPCI object.
12399+ * @mc_io: Pointer to MC portal's I/O object
12400+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12401+ * @cfg: Configuration structure
12402+ * @token: Returned token; use in subsequent API calls
12403+ *
12404+ * Create the DPCI object, allocate required resources and perform required
12405+ * initialization.
12406+ *
12407+ * The object can be created either by declaring it in the
12408+ * DPL file, or by calling this function.
12409+ *
12410+ * This function returns a unique authentication token,
12411+ * associated with the specific object ID and the specific MC
12412+ * portal; this token must be used in all subsequent calls to
12413+ * this specific object. For objects that are created using the
12414+ * DPL file, call dpci_open() function to get an authentication
12415+ * token first.
12416+ *
12417+ * Return: '0' on Success; Error code otherwise.
12418+ */
12419+int dpci_create(struct fsl_mc_io *mc_io,
12420+ uint32_t cmd_flags,
12421+ const struct dpci_cfg *cfg,
12422+ uint16_t *token);
12423+
12424+/**
12425+ * dpci_destroy() - Destroy the DPCI object and release all its resources.
12426+ * @mc_io: Pointer to MC portal's I/O object
12427+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12428+ * @token: Token of DPCI object
12429+ *
12430+ * Return: '0' on Success; error code otherwise.
12431+ */
12432+int dpci_destroy(struct fsl_mc_io *mc_io,
12433+ uint32_t cmd_flags,
12434+ uint16_t token);
12435+
12436+/**
12437+ * dpci_enable() - Enable the DPCI, allow sending and receiving frames.
12438+ * @mc_io: Pointer to MC portal's I/O object
12439+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12440+ * @token: Token of DPCI object
12441+ *
12442+ * Return: '0' on Success; Error code otherwise.
12443+ */
12444+int dpci_enable(struct fsl_mc_io *mc_io,
12445+ uint32_t cmd_flags,
12446+ uint16_t token);
12447+
12448+/**
12449+ * dpci_disable() - Disable the DPCI, stop sending and receiving frames.
12450+ * @mc_io: Pointer to MC portal's I/O object
12451+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12452+ * @token: Token of DPCI object
12453+ *
12454+ * Return: '0' on Success; Error code otherwise.
12455+ */
12456+int dpci_disable(struct fsl_mc_io *mc_io,
12457+ uint32_t cmd_flags,
12458+ uint16_t token);
12459+
12460+/**
12461+ * dpci_is_enabled() - Check if the DPCI is enabled.
12462+ * @mc_io: Pointer to MC portal's I/O object
12463+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12464+ * @token: Token of DPCI object
12465+ * @en: Returns '1' if object is enabled; '0' otherwise
12466+ *
12467+ * Return: '0' on Success; Error code otherwise.
12468+ */
12469+int dpci_is_enabled(struct fsl_mc_io *mc_io,
12470+ uint32_t cmd_flags,
12471+ uint16_t token,
12472+ int *en);
12473+
12474+/**
12475+ * dpci_reset() - Reset the DPCI, returns the object to initial state.
12476+ * @mc_io: Pointer to MC portal's I/O object
12477+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12478+ * @token: Token of DPCI object
12479+ *
12480+ * Return: '0' on Success; Error code otherwise.
12481+ */
12482+int dpci_reset(struct fsl_mc_io *mc_io,
12483+ uint32_t cmd_flags,
12484+ uint16_t token);
12485+
12486+/** DPCI IRQ Index and Events */
12487+
12488+/**
12489+ * IRQ index
12490+ */
12491+#define DPCI_IRQ_INDEX 0
12492+
12493+/**
12494+ * IRQ event - indicates a change in link state
12495+ */
12496+#define DPCI_IRQ_EVENT_LINK_CHANGED 0x00000001
12497+/**
12498+ * IRQ event - indicates a connection event
12499+ */
12500+#define DPCI_IRQ_EVENT_CONNECTED 0x00000002
12501+/**
12502+ * IRQ event - indicates a disconnection event
12503+ */
12504+#define DPCI_IRQ_EVENT_DISCONNECTED 0x00000004
12505+
12506+/**
12507+ * struct dpci_irq_cfg - IRQ configuration
12508+ * @addr: Address that must be written to signal a message-based interrupt
12509+ * @val: Value to write into irq_addr address
12510+ * @irq_num: A user defined number associated with this IRQ
12511+ */
12512+struct dpci_irq_cfg {
12513+ uint64_t addr;
12514+ uint32_t val;
12515+ int irq_num;
12516+};
12517+
12518+/**
12519+ * dpci_set_irq() - Set IRQ information for the DPCI to trigger an interrupt.
12520+ * @mc_io: Pointer to MC portal's I/O object
12521+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12522+ * @token: Token of DPCI object
12523+ * @irq_index: Identifies the interrupt index to configure
12524+ * @irq_cfg: IRQ configuration
12525+ *
12526+ * Return: '0' on Success; Error code otherwise.
12527+ */
12528+int dpci_set_irq(struct fsl_mc_io *mc_io,
12529+ uint32_t cmd_flags,
12530+ uint16_t token,
12531+ uint8_t irq_index,
12532+ struct dpci_irq_cfg *irq_cfg);
12533+
12534+/**
12535+ * dpci_get_irq() - Get IRQ information from the DPCI.
12536+ * @mc_io: Pointer to MC portal's I/O object
12537+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12538+ * @token: Token of DPCI object
12539+ * @irq_index: The interrupt index to configure
12540+ * @type: Interrupt type: 0 represents message interrupt
12541+ * type (both irq_addr and irq_val are valid)
12542+ * @irq_cfg: IRQ attributes
12543+ *
12544+ * Return: '0' on Success; Error code otherwise.
12545+ */
12546+int dpci_get_irq(struct fsl_mc_io *mc_io,
12547+ uint32_t cmd_flags,
12548+ uint16_t token,
12549+ uint8_t irq_index,
12550+ int *type,
12551+ struct dpci_irq_cfg *irq_cfg);
12552+
12553+/**
12554+ * dpci_set_irq_enable() - Set overall interrupt state.
12555+ * @mc_io: Pointer to MC portal's I/O object
12556+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12557+ * @token: Token of DPCI object
12558+ * @irq_index: The interrupt index to configure
12559+ * @en: Interrupt state - enable = 1, disable = 0
12560+ *
12561+ * Allows GPP software to control when interrupts are generated.
12562+ * Each interrupt can have up to 32 causes. The enable/disable control's the
12563+ * overall interrupt state. if the interrupt is disabled no causes will cause
12564+ * an interrupt.
12565+ *
12566+ * Return: '0' on Success; Error code otherwise.
12567+ */
12568+int dpci_set_irq_enable(struct fsl_mc_io *mc_io,
12569+ uint32_t cmd_flags,
12570+ uint16_t token,
12571+ uint8_t irq_index,
12572+ uint8_t en);
12573+
12574+/**
12575+ * dpci_get_irq_enable() - Get overall interrupt state.
12576+ * @mc_io: Pointer to MC portal's I/O object
12577+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12578+ * @token: Token of DPCI object
12579+ * @irq_index: The interrupt index to configure
12580+ * @en: Returned interrupt state - enable = 1, disable = 0
12581+ *
12582+ * Return: '0' on Success; Error code otherwise.
12583+ */
12584+int dpci_get_irq_enable(struct fsl_mc_io *mc_io,
12585+ uint32_t cmd_flags,
12586+ uint16_t token,
12587+ uint8_t irq_index,
12588+ uint8_t *en);
12589+
12590+/**
12591+ * dpci_set_irq_mask() - Set interrupt mask.
12592+ * @mc_io: Pointer to MC portal's I/O object
12593+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12594+ * @token: Token of DPCI object
12595+ * @irq_index: The interrupt index to configure
12596+ * @mask: event mask to trigger interrupt;
12597+ * each bit:
12598+ * 0 = ignore event
12599+ * 1 = consider event for asserting IRQ
12600+ *
12601+ * Every interrupt can have up to 32 causes and the interrupt model supports
12602+ * masking/unmasking each cause independently
12603+ *
12604+ * Return: '0' on Success; Error code otherwise.
12605+ */
12606+int dpci_set_irq_mask(struct fsl_mc_io *mc_io,
12607+ uint32_t cmd_flags,
12608+ uint16_t token,
12609+ uint8_t irq_index,
12610+ uint32_t mask);
12611+
12612+/**
12613+ * dpci_get_irq_mask() - Get interrupt mask.
12614+ * @mc_io: Pointer to MC portal's I/O object
12615+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12616+ * @token: Token of DPCI object
12617+ * @irq_index: The interrupt index to configure
12618+ * @mask: Returned event mask to trigger interrupt
12619+ *
12620+ * Every interrupt can have up to 32 causes and the interrupt model supports
12621+ * masking/unmasking each cause independently
12622+ *
12623+ * Return: '0' on Success; Error code otherwise.
12624+ */
12625+int dpci_get_irq_mask(struct fsl_mc_io *mc_io,
12626+ uint32_t cmd_flags,
12627+ uint16_t token,
12628+ uint8_t irq_index,
12629+ uint32_t *mask);
12630+
12631+/**
12632+ * dpci_get_irq_status() - Get the current status of any pending interrupts.
12633+ * @mc_io: Pointer to MC portal's I/O object
12634+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12635+ * @token: Token of DPCI object
12636+ * @irq_index: The interrupt index to configure
12637+ * @status: Returned interrupts status - one bit per cause:
12638+ * 0 = no interrupt pending
12639+ * 1 = interrupt pending
12640+ *
12641+ * Return: '0' on Success; Error code otherwise.
12642+ */
12643+int dpci_get_irq_status(struct fsl_mc_io *mc_io,
12644+ uint32_t cmd_flags,
12645+ uint16_t token,
12646+ uint8_t irq_index,
12647+ uint32_t *status);
12648+
12649+/**
12650+ * dpci_clear_irq_status() - Clear a pending interrupt's status
12651+ * @mc_io: Pointer to MC portal's I/O object
12652+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12653+ * @token: Token of DPCI object
12654+ * @irq_index: The interrupt index to configure
12655+ * @status: bits to clear (W1C) - one bit per cause:
12656+ * 0 = don't change
12657+ * 1 = clear status bit
12658+ *
12659+ * Return: '0' on Success; Error code otherwise.
12660+ */
12661+int dpci_clear_irq_status(struct fsl_mc_io *mc_io,
12662+ uint32_t cmd_flags,
12663+ uint16_t token,
12664+ uint8_t irq_index,
12665+ uint32_t status);
12666+
12667+/**
12668+ * struct dpci_attr - Structure representing DPCI attributes
12669+ * @id: DPCI object ID
12670+ * @version: DPCI version
12671+ * @num_of_priorities: Number of receive priorities
12672+ */
12673+struct dpci_attr {
12674+ int id;
12675+ /**
12676+ * struct version - Structure representing DPCI attributes
12677+ * @major: DPCI major version
12678+ * @minor: DPCI minor version
12679+ */
12680+ struct {
12681+ uint16_t major;
12682+ uint16_t minor;
12683+ } version;
12684+ uint8_t num_of_priorities;
12685+};
12686+
12687+/**
12688+ * dpci_get_attributes() - Retrieve DPCI attributes.
12689+ * @mc_io: Pointer to MC portal's I/O object
12690+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12691+ * @token: Token of DPCI object
12692+ * @attr: Returned object's attributes
12693+ *
12694+ * Return: '0' on Success; Error code otherwise.
12695+ */
12696+int dpci_get_attributes(struct fsl_mc_io *mc_io,
12697+ uint32_t cmd_flags,
12698+ uint16_t token,
12699+ struct dpci_attr *attr);
12700+
12701+/**
12702+ * struct dpci_peer_attr - Structure representing the peer DPCI attributes
12703+ * @peer_id: DPCI peer id; if no peer is connected returns (-1)
12704+ * @num_of_priorities: The pper's number of receive priorities; determines the
12705+ * number of transmit priorities for the local DPCI object
12706+ */
12707+struct dpci_peer_attr {
12708+ int peer_id;
12709+ uint8_t num_of_priorities;
12710+};
12711+
12712+/**
12713+ * dpci_get_peer_attributes() - Retrieve peer DPCI attributes.
12714+ * @mc_io: Pointer to MC portal's I/O object
12715+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12716+ * @token: Token of DPCI object
12717+ * @attr: Returned peer attributes
12718+ *
12719+ * Return: '0' on Success; Error code otherwise.
12720+ */
12721+int dpci_get_peer_attributes(struct fsl_mc_io *mc_io,
12722+ uint32_t cmd_flags,
12723+ uint16_t token,
12724+ struct dpci_peer_attr *attr);
12725+
12726+/**
12727+ * dpci_get_link_state() - Retrieve the DPCI link state.
12728+ * @mc_io: Pointer to MC portal's I/O object
12729+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12730+ * @token: Token of DPCI object
12731+ * @up: Returned link state; returns '1' if link is up, '0' otherwise
12732+ *
12733+ * DPCI can be connected to another DPCI, together they
12734+ * create a 'link'. In order to use the DPCI Tx and Rx queues,
12735+ * both objects must be enabled.
12736+ *
12737+ * Return: '0' on Success; Error code otherwise.
12738+ */
12739+int dpci_get_link_state(struct fsl_mc_io *mc_io,
12740+ uint32_t cmd_flags,
12741+ uint16_t token,
12742+ int *up);
12743+
12744+/**
12745+ * enum dpci_dest - DPCI destination types
12746+ * @DPCI_DEST_NONE: Unassigned destination; The queue is set in parked mode
12747+ * and does not generate FQDAN notifications; user is
12748+ * expected to dequeue from the queue based on polling or
12749+ * other user-defined method
12750+ * @DPCI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN
12751+ * notifications to the specified DPIO; user is expected
12752+ * to dequeue from the queue only after notification is
12753+ * received
12754+ * @DPCI_DEST_DPCON: The queue is set in schedule mode and does not generate
12755+ * FQDAN notifications, but is connected to the specified
12756+ * DPCON object;
12757+ * user is expected to dequeue from the DPCON channel
12758+ */
12759+enum dpci_dest {
12760+ DPCI_DEST_NONE = 0,
12761+ DPCI_DEST_DPIO = 1,
12762+ DPCI_DEST_DPCON = 2
12763+};
12764+
12765+/**
12766+ * struct dpci_dest_cfg - Structure representing DPCI destination configuration
12767+ * @dest_type: Destination type
12768+ * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type
12769+ * @priority: Priority selection within the DPIO or DPCON channel; valid
12770+ * values are 0-1 or 0-7, depending on the number of priorities
12771+ * in that channel; not relevant for 'DPCI_DEST_NONE' option
12772+ */
12773+struct dpci_dest_cfg {
12774+ enum dpci_dest dest_type;
12775+ int dest_id;
12776+ uint8_t priority;
12777+};
12778+
12779+/** DPCI queue modification options */
12780+
12781+/**
12782+ * Select to modify the user's context associated with the queue
12783+ */
12784+#define DPCI_QUEUE_OPT_USER_CTX 0x00000001
12785+
12786+/**
12787+ * Select to modify the queue's destination
12788+ */
12789+#define DPCI_QUEUE_OPT_DEST 0x00000002
12790+
12791+/**
12792+ * struct dpci_rx_queue_cfg - Structure representing RX queue configuration
12793+ * @options: Flags representing the suggested modifications to the queue;
12794+ * Use any combination of 'DPCI_QUEUE_OPT_<X>' flags
12795+ * @user_ctx: User context value provided in the frame descriptor of each
12796+ * dequeued frame;
12797+ * valid only if 'DPCI_QUEUE_OPT_USER_CTX' is contained in
12798+ * 'options'
12799+ * @dest_cfg: Queue destination parameters;
12800+ * valid only if 'DPCI_QUEUE_OPT_DEST' is contained in 'options'
12801+ */
12802+struct dpci_rx_queue_cfg {
12803+ uint32_t options;
12804+ uint64_t user_ctx;
12805+ struct dpci_dest_cfg dest_cfg;
12806+};
12807+
12808+/**
12809+ * dpci_set_rx_queue() - Set Rx queue configuration
12810+ * @mc_io: Pointer to MC portal's I/O object
12811+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12812+ * @token: Token of DPCI object
12813+ * @priority: Select the queue relative to number of
12814+ * priorities configured at DPCI creation; use
12815+ * DPCI_ALL_QUEUES to configure all Rx queues
12816+ * identically.
12817+ * @cfg: Rx queue configuration
12818+ *
12819+ * Return: '0' on Success; Error code otherwise.
12820+ */
12821+int dpci_set_rx_queue(struct fsl_mc_io *mc_io,
12822+ uint32_t cmd_flags,
12823+ uint16_t token,
12824+ uint8_t priority,
12825+ const struct dpci_rx_queue_cfg *cfg);
12826+
12827+/**
12828+ * struct dpci_rx_queue_attr - Structure representing Rx queue attributes
12829+ * @user_ctx: User context value provided in the frame descriptor of each
12830+ * dequeued frame
12831+ * @dest_cfg: Queue destination configuration
12832+ * @fqid: Virtual FQID value to be used for dequeue operations
12833+ */
12834+struct dpci_rx_queue_attr {
12835+ uint64_t user_ctx;
12836+ struct dpci_dest_cfg dest_cfg;
12837+ uint32_t fqid;
12838+};
12839+
12840+/**
12841+ * dpci_get_rx_queue() - Retrieve Rx queue attributes.
12842+ * @mc_io: Pointer to MC portal's I/O object
12843+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12844+ * @token: Token of DPCI object
12845+ * @priority: Select the queue relative to number of
12846+ * priorities configured at DPCI creation
12847+ * @attr: Returned Rx queue attributes
12848+ *
12849+ * Return: '0' on Success; Error code otherwise.
12850+ */
12851+int dpci_get_rx_queue(struct fsl_mc_io *mc_io,
12852+ uint32_t cmd_flags,
12853+ uint16_t token,
12854+ uint8_t priority,
12855+ struct dpci_rx_queue_attr *attr);
12856+
12857+/**
12858+ * struct dpci_tx_queue_attr - Structure representing attributes of Tx queues
12859+ * @fqid: Virtual FQID to be used for sending frames to peer DPCI;
12860+ * returns 'DPCI_FQID_NOT_VALID' if a no peer is connected or if
12861+ * the selected priority exceeds the number of priorities of the
12862+ * peer DPCI object
12863+ */
12864+struct dpci_tx_queue_attr {
12865+ uint32_t fqid;
12866+};
12867+
12868+/**
12869+ * dpci_get_tx_queue() - Retrieve Tx queue attributes.
12870+ * @mc_io: Pointer to MC portal's I/O object
12871+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
12872+ * @token: Token of DPCI object
12873+ * @priority: Select the queue relative to number of
12874+ * priorities of the peer DPCI object
12875+ * @attr: Returned Tx queue attributes
12876+ *
12877+ * Return: '0' on Success; Error code otherwise.
12878+ */
12879+int dpci_get_tx_queue(struct fsl_mc_io *mc_io,
12880+ uint32_t cmd_flags,
12881+ uint16_t token,
12882+ uint8_t priority,
12883+ struct dpci_tx_queue_attr *attr);
12884+
12885+#endif /* __FSL_DPCI_H */
12886diff --git a/drivers/net/dpaa2/mc/fsl_dpci_cmd.h b/drivers/net/dpaa2/mc/fsl_dpci_cmd.h
12887new file mode 100644
12888index 0000000..f45e435
12889--- /dev/null
12890+++ b/drivers/net/dpaa2/mc/fsl_dpci_cmd.h
12891@@ -0,0 +1,200 @@
12892+/* Copyright 2013-2015 Freescale Semiconductor Inc.
12893+ *
12894+ * Redistribution and use in source and binary forms, with or without
12895+ * modification, are permitted provided that the following conditions are met:
12896+ * * Redistributions of source code must retain the above copyright
12897+ * notice, this list of conditions and the following disclaimer.
12898+ * * Redistributions in binary form must reproduce the above copyright
12899+ * notice, this list of conditions and the following disclaimer in the
12900+ * documentation and/or other materials provided with the distribution.
12901+ * * Neither the name of the above-listed copyright holders nor the
12902+ * names of any contributors may be used to endorse or promote products
12903+ * derived from this software without specific prior written permission.
12904+ *
12905+ *
12906+ * ALTERNATIVELY, this software may be distributed under the terms of the
12907+ * GNU General Public License ("GPL") as published by the Free Software
12908+ * Foundation, either version 2 of that License or (at your option) any
12909+ * later version.
12910+ *
12911+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
12912+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
12913+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
12914+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
12915+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
12916+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
12917+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
12918+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
12919+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
12920+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
12921+ * POSSIBILITY OF SUCH DAMAGE.
12922+ */
12923+#ifndef _FSL_DPCI_CMD_H
12924+#define _FSL_DPCI_CMD_H
12925+
12926+/* DPCI Version */
12927+#define DPCI_VER_MAJOR 2
12928+#define DPCI_VER_MINOR 2
12929+
12930+/* Command IDs */
12931+#define DPCI_CMDID_CLOSE 0x800
12932+#define DPCI_CMDID_OPEN 0x807
12933+#define DPCI_CMDID_CREATE 0x907
12934+#define DPCI_CMDID_DESTROY 0x900
12935+
12936+#define DPCI_CMDID_ENABLE 0x002
12937+#define DPCI_CMDID_DISABLE 0x003
12938+#define DPCI_CMDID_GET_ATTR 0x004
12939+#define DPCI_CMDID_RESET 0x005
12940+#define DPCI_CMDID_IS_ENABLED 0x006
12941+
12942+#define DPCI_CMDID_SET_IRQ 0x010
12943+#define DPCI_CMDID_GET_IRQ 0x011
12944+#define DPCI_CMDID_SET_IRQ_ENABLE 0x012
12945+#define DPCI_CMDID_GET_IRQ_ENABLE 0x013
12946+#define DPCI_CMDID_SET_IRQ_MASK 0x014
12947+#define DPCI_CMDID_GET_IRQ_MASK 0x015
12948+#define DPCI_CMDID_GET_IRQ_STATUS 0x016
12949+#define DPCI_CMDID_CLEAR_IRQ_STATUS 0x017
12950+
12951+#define DPCI_CMDID_SET_RX_QUEUE 0x0e0
12952+#define DPCI_CMDID_GET_LINK_STATE 0x0e1
12953+#define DPCI_CMDID_GET_PEER_ATTR 0x0e2
12954+#define DPCI_CMDID_GET_RX_QUEUE 0x0e3
12955+#define DPCI_CMDID_GET_TX_QUEUE 0x0e4
12956+
12957+/* cmd, param, offset, width, type, arg_name */
12958+#define DPCI_CMD_OPEN(cmd, dpci_id) \
12959+ MC_CMD_OP(cmd, 0, 0, 32, int, dpci_id)
12960+
12961+/* cmd, param, offset, width, type, arg_name */
12962+#define DPCI_CMD_CREATE(cmd, cfg) \
12963+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_of_priorities)
12964+
12965+/* cmd, param, offset, width, type, arg_name */
12966+#define DPCI_RSP_IS_ENABLED(cmd, en) \
12967+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
12968+
12969+/* cmd, param, offset, width, type, arg_name */
12970+#define DPCI_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
12971+do { \
12972+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
12973+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
12974+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
12975+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
12976+} while (0)
12977+
12978+/* cmd, param, offset, width, type, arg_name */
12979+#define DPCI_CMD_GET_IRQ(cmd, irq_index) \
12980+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
12981+
12982+/* cmd, param, offset, width, type, arg_name */
12983+#define DPCI_RSP_GET_IRQ(cmd, type, irq_cfg) \
12984+do { \
12985+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
12986+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
12987+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
12988+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
12989+} while (0)
12990+
12991+/* cmd, param, offset, width, type, arg_name */
12992+#define DPCI_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \
12993+do { \
12994+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \
12995+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
12996+} while (0)
12997+
12998+/* cmd, param, offset, width, type, arg_name */
12999+#define DPCI_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
13000+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
13001+
13002+/* cmd, param, offset, width, type, arg_name */
13003+#define DPCI_RSP_GET_IRQ_ENABLE(cmd, en) \
13004+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en)
13005+
13006+/* cmd, param, offset, width, type, arg_name */
13007+#define DPCI_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
13008+do { \
13009+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
13010+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
13011+} while (0)
13012+
13013+/* cmd, param, offset, width, type, arg_name */
13014+#define DPCI_CMD_GET_IRQ_MASK(cmd, irq_index) \
13015+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
13016+
13017+/* cmd, param, offset, width, type, arg_name */
13018+#define DPCI_RSP_GET_IRQ_MASK(cmd, mask) \
13019+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
13020+
13021+/* cmd, param, offset, width, type, arg_name */
13022+#define DPCI_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
13023+do { \
13024+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
13025+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
13026+} while (0)
13027+/* cmd, param, offset, width, type, arg_name */
13028+#define DPCI_RSP_GET_IRQ_STATUS(cmd, status) \
13029+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
13030+
13031+/* cmd, param, offset, width, type, arg_name */
13032+#define DPCI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
13033+do { \
13034+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
13035+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
13036+} while (0)
13037+
13038+/* cmd, param, offset, width, type, arg_name */
13039+#define DPCI_RSP_GET_ATTR(cmd, attr) \
13040+do { \
13041+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\
13042+ MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->num_of_priorities);\
13043+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
13044+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
13045+} while (0)
13046+
13047+/* cmd, param, offset, width, type, arg_name */
13048+#define DPCI_RSP_GET_PEER_ATTR(cmd, attr) \
13049+do { \
13050+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->peer_id);\
13051+ MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->num_of_priorities);\
13052+} while (0)
13053+
13054+/* cmd, param, offset, width, type, arg_name */
13055+#define DPCI_RSP_GET_LINK_STATE(cmd, up) \
13056+ MC_RSP_OP(cmd, 0, 0, 1, int, up)
13057+
13058+/* cmd, param, offset, width, type, arg_name */
13059+#define DPCI_CMD_SET_RX_QUEUE(cmd, priority, cfg) \
13060+do { \
13061+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id);\
13062+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority);\
13063+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, priority);\
13064+ MC_CMD_OP(cmd, 0, 48, 4, enum dpci_dest, cfg->dest_cfg.dest_type);\
13065+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx);\
13066+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
13067+} while (0)
13068+
13069+/* cmd, param, offset, width, type, arg_name */
13070+#define DPCI_CMD_GET_RX_QUEUE(cmd, priority) \
13071+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, priority)
13072+
13073+/* cmd, param, offset, width, type, arg_name */
13074+#define DPCI_RSP_GET_RX_QUEUE(cmd, attr) \
13075+do { \
13076+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id);\
13077+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
13078+ MC_RSP_OP(cmd, 0, 48, 4, enum dpci_dest, attr->dest_cfg.dest_type);\
13079+ MC_RSP_OP(cmd, 1, 0, 8, uint64_t, attr->user_ctx);\
13080+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->fqid);\
13081+} while (0)
13082+
13083+/* cmd, param, offset, width, type, arg_name */
13084+#define DPCI_CMD_GET_TX_QUEUE(cmd, priority) \
13085+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, priority)
13086+
13087+/* cmd, param, offset, width, type, arg_name */
13088+#define DPCI_RSP_GET_TX_QUEUE(cmd, attr) \
13089+ MC_RSP_OP(cmd, 0, 32, 32, uint32_t, attr->fqid)
13090+
13091+#endif /* _FSL_DPCI_CMD_H */
13092diff --git a/drivers/net/dpaa2/mc/fsl_dpcon.h b/drivers/net/dpaa2/mc/fsl_dpcon.h
13093new file mode 100644
13094index 0000000..2555be5
13095--- /dev/null
13096+++ b/drivers/net/dpaa2/mc/fsl_dpcon.h
13097@@ -0,0 +1,407 @@
13098+/* Copyright 2013-2015 Freescale Semiconductor Inc.
13099+ *
13100+ * Redistribution and use in source and binary forms, with or without
13101+ * modification, are permitted provided that the following conditions are met:
13102+ * * Redistributions of source code must retain the above copyright
13103+ * notice, this list of conditions and the following disclaimer.
13104+ * * Redistributions in binary form must reproduce the above copyright
13105+ * notice, this list of conditions and the following disclaimer in the
13106+ * documentation and/or other materials provided with the distribution.
13107+ * * Neither the name of the above-listed copyright holders nor the
13108+ * names of any contributors may be used to endorse or promote products
13109+ * derived from this software without specific prior written permission.
13110+ *
13111+ *
13112+ * ALTERNATIVELY, this software may be distributed under the terms of the
13113+ * GNU General Public License ("GPL") as published by the Free Software
13114+ * Foundation, either version 2 of that License or (at your option) any
13115+ * later version.
13116+ *
13117+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
13118+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13119+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13120+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
13121+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
13122+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
13123+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
13124+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
13125+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
13126+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
13127+ * POSSIBILITY OF SUCH DAMAGE.
13128+ */
13129+#ifndef __FSL_DPCON_H
13130+#define __FSL_DPCON_H
13131+
13132+/* Data Path Concentrator API
13133+ * Contains initialization APIs and runtime control APIs for DPCON
13134+ */
13135+
13136+struct fsl_mc_io;
13137+
13138+/** General DPCON macros */
13139+
13140+/**
13141+ * Use it to disable notifications; see dpcon_set_notification()
13142+ */
13143+#define DPCON_INVALID_DPIO_ID (int)(-1)
13144+
13145+/**
13146+ * dpcon_open() - Open a control session for the specified object
13147+ * @mc_io: Pointer to MC portal's I/O object
13148+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13149+ * @dpcon_id: DPCON unique ID
13150+ * @token: Returned token; use in subsequent API calls
13151+ *
13152+ * This function can be used to open a control session for an
13153+ * already created object; an object may have been declared in
13154+ * the DPL or by calling the dpcon_create() function.
13155+ * This function returns a unique authentication token,
13156+ * associated with the specific object ID and the specific MC
13157+ * portal; this token must be used in all subsequent commands for
13158+ * this specific object.
13159+ *
13160+ * Return: '0' on Success; Error code otherwise.
13161+ */
13162+int dpcon_open(struct fsl_mc_io *mc_io,
13163+ uint32_t cmd_flags,
13164+ int dpcon_id,
13165+ uint16_t *token);
13166+
13167+/**
13168+ * dpcon_close() - Close the control session of the object
13169+ * @mc_io: Pointer to MC portal's I/O object
13170+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13171+ * @token: Token of DPCON object
13172+ *
13173+ * After this function is called, no further operations are
13174+ * allowed on the object without opening a new control session.
13175+ *
13176+ * Return: '0' on Success; Error code otherwise.
13177+ */
13178+int dpcon_close(struct fsl_mc_io *mc_io,
13179+ uint32_t cmd_flags,
13180+ uint16_t token);
13181+
13182+/**
13183+ * struct dpcon_cfg - Structure representing DPCON configuration
13184+ * @num_priorities: Number of priorities for the DPCON channel (1-8)
13185+ */
13186+struct dpcon_cfg {
13187+ uint8_t num_priorities;
13188+};
13189+
13190+/**
13191+ * dpcon_create() - Create the DPCON object.
13192+ * @mc_io: Pointer to MC portal's I/O object
13193+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13194+ * @cfg: Configuration structure
13195+ * @token: Returned token; use in subsequent API calls
13196+ *
13197+ * Create the DPCON object, allocate required resources and
13198+ * perform required initialization.
13199+ *
13200+ * The object can be created either by declaring it in the
13201+ * DPL file, or by calling this function.
13202+ *
13203+ * This function returns a unique authentication token,
13204+ * associated with the specific object ID and the specific MC
13205+ * portal; this token must be used in all subsequent calls to
13206+ * this specific object. For objects that are created using the
13207+ * DPL file, call dpcon_open() function to get an authentication
13208+ * token first.
13209+ *
13210+ * Return: '0' on Success; Error code otherwise.
13211+ */
13212+int dpcon_create(struct fsl_mc_io *mc_io,
13213+ uint32_t cmd_flags,
13214+ const struct dpcon_cfg *cfg,
13215+ uint16_t *token);
13216+
13217+/**
13218+ * dpcon_destroy() - Destroy the DPCON object and release all its resources.
13219+ * @mc_io: Pointer to MC portal's I/O object
13220+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13221+ * @token: Token of DPCON object
13222+ *
13223+ * Return: '0' on Success; error code otherwise.
13224+ */
13225+int dpcon_destroy(struct fsl_mc_io *mc_io,
13226+ uint32_t cmd_flags,
13227+ uint16_t token);
13228+
13229+/**
13230+ * dpcon_enable() - Enable the DPCON
13231+ * @mc_io: Pointer to MC portal's I/O object
13232+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13233+ * @token: Token of DPCON object
13234+ *
13235+ * Return: '0' on Success; Error code otherwise
13236+ */
13237+int dpcon_enable(struct fsl_mc_io *mc_io,
13238+ uint32_t cmd_flags,
13239+ uint16_t token);
13240+
13241+/**
13242+ * dpcon_disable() - Disable the DPCON
13243+ * @mc_io: Pointer to MC portal's I/O object
13244+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13245+ * @token: Token of DPCON object
13246+ *
13247+ * Return: '0' on Success; Error code otherwise
13248+ */
13249+int dpcon_disable(struct fsl_mc_io *mc_io,
13250+ uint32_t cmd_flags,
13251+ uint16_t token);
13252+
13253+/**
13254+ * dpcon_is_enabled() - Check if the DPCON is enabled.
13255+ * @mc_io: Pointer to MC portal's I/O object
13256+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13257+ * @token: Token of DPCON object
13258+ * @en: Returns '1' if object is enabled; '0' otherwise
13259+ *
13260+ * Return: '0' on Success; Error code otherwise.
13261+ */
13262+int dpcon_is_enabled(struct fsl_mc_io *mc_io,
13263+ uint32_t cmd_flags,
13264+ uint16_t token,
13265+ int *en);
13266+
13267+/**
13268+ * dpcon_reset() - Reset the DPCON, returns the object to initial state.
13269+ * @mc_io: Pointer to MC portal's I/O object
13270+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13271+ * @token: Token of DPCON object
13272+ *
13273+ * Return: '0' on Success; Error code otherwise.
13274+ */
13275+int dpcon_reset(struct fsl_mc_io *mc_io,
13276+ uint32_t cmd_flags,
13277+ uint16_t token);
13278+
13279+/**
13280+ * struct dpcon_irq_cfg - IRQ configuration
13281+ * @addr: Address that must be written to signal a message-based interrupt
13282+ * @val: Value to write into irq_addr address
13283+ * @irq_num: A user defined number associated with this IRQ
13284+ */
13285+struct dpcon_irq_cfg {
13286+ uint64_t addr;
13287+ uint32_t val;
13288+ int irq_num;
13289+};
13290+
13291+/**
13292+ * dpcon_set_irq() - Set IRQ information for the DPCON to trigger an interrupt.
13293+ * @mc_io: Pointer to MC portal's I/O object
13294+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13295+ * @token: Token of DPCON object
13296+ * @irq_index: Identifies the interrupt index to configure
13297+ * @irq_cfg: IRQ configuration
13298+ * Return: '0' on Success; Error code otherwise.
13299+ */
13300+int dpcon_set_irq(struct fsl_mc_io *mc_io,
13301+ uint32_t cmd_flags,
13302+ uint16_t token,
13303+ uint8_t irq_index,
13304+ struct dpcon_irq_cfg *irq_cfg);
13305+
13306+/**
13307+ * dpcon_get_irq() - Get IRQ information from the DPCON.
13308+ *
13309+ * @mc_io: Pointer to MC portal's I/O object
13310+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13311+ * @token: Token of DPCON object
13312+ * @irq_index: The interrupt index to configure
13313+ * @type: Interrupt type: 0 represents message interrupt
13314+ * type (both irq_addr and irq_val are valid)
13315+ * @irq_cfg: IRQ attributes
13316+ *
13317+ * Return: '0' on Success; Error code otherwise.
13318+ */
13319+int dpcon_get_irq(struct fsl_mc_io *mc_io,
13320+ uint32_t cmd_flags,
13321+ uint16_t token,
13322+ uint8_t irq_index,
13323+ int *type,
13324+ struct dpcon_irq_cfg *irq_cfg);
13325+
13326+/**
13327+ * dpcon_set_irq_enable() - Set overall interrupt state.
13328+ * @mc_io: Pointer to MC portal's I/O object
13329+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13330+ * @token: Token of DPCON object
13331+ * @irq_index: The interrupt index to configure
13332+ * @en: Interrupt state - enable = 1, disable = 0
13333+ *
13334+ * Allows GPP software to control when interrupts are generated.
13335+ * Each interrupt can have up to 32 causes. The enable/disable control's the
13336+ * overall interrupt state. if the interrupt is disabled no causes will cause
13337+ * an interrupt.
13338+ *
13339+ * Return: '0' on Success; Error code otherwise.
13340+ */
13341+int dpcon_set_irq_enable(struct fsl_mc_io *mc_io,
13342+ uint32_t cmd_flags,
13343+ uint16_t token,
13344+ uint8_t irq_index,
13345+ uint8_t en);
13346+
13347+/**
13348+ * dpcon_get_irq_enable() - Get overall interrupt state.
13349+ * @mc_io: Pointer to MC portal's I/O object
13350+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13351+ * @token: Token of DPCON object
13352+ * @irq_index: The interrupt index to configure
13353+ * @en: Returned interrupt state - enable = 1, disable = 0
13354+ *
13355+ * Return: '0' on Success; Error code otherwise.
13356+ */
13357+int dpcon_get_irq_enable(struct fsl_mc_io *mc_io,
13358+ uint32_t cmd_flags,
13359+ uint16_t token,
13360+ uint8_t irq_index,
13361+ uint8_t *en);
13362+
13363+/**
13364+ * dpcon_set_irq_mask() - Set interrupt mask.
13365+ * @mc_io: Pointer to MC portal's I/O object
13366+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13367+ * @token: Token of DPCON object
13368+ * @irq_index: The interrupt index to configure
13369+ * @mask: Event mask to trigger interrupt;
13370+ * each bit:
13371+ * 0 = ignore event
13372+ * 1 = consider event for asserting IRQ
13373+ *
13374+ * Every interrupt can have up to 32 causes and the interrupt model supports
13375+ * masking/unmasking each cause independently
13376+ *
13377+ * Return: '0' on Success; Error code otherwise.
13378+ */
13379+int dpcon_set_irq_mask(struct fsl_mc_io *mc_io,
13380+ uint32_t cmd_flags,
13381+ uint16_t token,
13382+ uint8_t irq_index,
13383+ uint32_t mask);
13384+
13385+/**
13386+ * dpcon_get_irq_mask() - Get interrupt mask.
13387+ * @mc_io: Pointer to MC portal's I/O object
13388+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13389+ * @token: Token of DPCON object
13390+ * @irq_index: The interrupt index to configure
13391+ * @mask: Returned event mask to trigger interrupt
13392+ *
13393+ * Every interrupt can have up to 32 causes and the interrupt model supports
13394+ * masking/unmasking each cause independently
13395+ *
13396+ * Return: '0' on Success; Error code otherwise.
13397+ */
13398+int dpcon_get_irq_mask(struct fsl_mc_io *mc_io,
13399+ uint32_t cmd_flags,
13400+ uint16_t token,
13401+ uint8_t irq_index,
13402+ uint32_t *mask);
13403+
13404+/**
13405+ * dpcon_get_irq_status() - Get the current status of any pending interrupts.
13406+ * @mc_io: Pointer to MC portal's I/O object
13407+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13408+ * @token: Token of DPCON object
13409+ * @irq_index: The interrupt index to configure
13410+ * @status: interrupts status - one bit per cause:
13411+ * 0 = no interrupt pending
13412+ * 1 = interrupt pending
13413+ *
13414+ * Return: '0' on Success; Error code otherwise.
13415+ */
13416+int dpcon_get_irq_status(struct fsl_mc_io *mc_io,
13417+ uint32_t cmd_flags,
13418+ uint16_t token,
13419+ uint8_t irq_index,
13420+ uint32_t *status);
13421+
13422+/**
13423+ * dpcon_clear_irq_status() - Clear a pending interrupt's status
13424+ * @mc_io: Pointer to MC portal's I/O object
13425+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13426+ * @token: Token of DPCON object
13427+ * @irq_index: The interrupt index to configure
13428+ * @status: bits to clear (W1C) - one bit per cause:
13429+ * 0 = don't change
13430+ * 1 = clear status bit
13431+ *
13432+ * Return: '0' on Success; Error code otherwise.
13433+ */
13434+int dpcon_clear_irq_status(struct fsl_mc_io *mc_io,
13435+ uint32_t cmd_flags,
13436+ uint16_t token,
13437+ uint8_t irq_index,
13438+ uint32_t status);
13439+
13440+/**
13441+ * struct dpcon_attr - Structure representing DPCON attributes
13442+ * @id: DPCON object ID
13443+ * @version: DPCON version
13444+ * @qbman_ch_id: Channel ID to be used by dequeue operation
13445+ * @num_priorities: Number of priorities for the DPCON channel (1-8)
13446+ */
13447+struct dpcon_attr {
13448+ int id;
13449+ /**
13450+ * struct version - DPCON version
13451+ * @major: DPCON major version
13452+ * @minor: DPCON minor version
13453+ */
13454+ struct {
13455+ uint16_t major;
13456+ uint16_t minor;
13457+ } version;
13458+ uint16_t qbman_ch_id;
13459+ uint8_t num_priorities;
13460+};
13461+
13462+/**
13463+ * dpcon_get_attributes() - Retrieve DPCON attributes.
13464+ * @mc_io: Pointer to MC portal's I/O object
13465+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13466+ * @token: Token of DPCON object
13467+ * @attr: Object's attributes
13468+ *
13469+ * Return: '0' on Success; Error code otherwise.
13470+ */
13471+int dpcon_get_attributes(struct fsl_mc_io *mc_io,
13472+ uint32_t cmd_flags,
13473+ uint16_t token,
13474+ struct dpcon_attr *attr);
13475+
13476+/**
13477+ * struct dpcon_notification_cfg - Structure representing notification parameters
13478+ * @dpio_id: DPIO object ID; must be configured with a notification channel;
13479+ * to disable notifications set it to 'DPCON_INVALID_DPIO_ID';
13480+ * @priority: Priority selection within the DPIO channel; valid values
13481+ * are 0-7, depending on the number of priorities in that channel
13482+ * @user_ctx: User context value provided with each CDAN message
13483+ */
13484+struct dpcon_notification_cfg {
13485+ int dpio_id;
13486+ uint8_t priority;
13487+ uint64_t user_ctx;
13488+};
13489+
13490+/**
13491+ * dpcon_set_notification() - Set DPCON notification destination
13492+ * @mc_io: Pointer to MC portal's I/O object
13493+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13494+ * @token: Token of DPCON object
13495+ * @cfg: Notification parameters
13496+ *
13497+ * Return: '0' on Success; Error code otherwise
13498+ */
13499+int dpcon_set_notification(struct fsl_mc_io *mc_io,
13500+ uint32_t cmd_flags,
13501+ uint16_t token,
13502+ struct dpcon_notification_cfg *cfg);
13503+
13504+#endif /* __FSL_DPCON_H */
13505diff --git a/drivers/net/dpaa2/mc/fsl_dpcon_cmd.h b/drivers/net/dpaa2/mc/fsl_dpcon_cmd.h
13506new file mode 100644
13507index 0000000..ecb40d0
13508--- /dev/null
13509+++ b/drivers/net/dpaa2/mc/fsl_dpcon_cmd.h
13510@@ -0,0 +1,162 @@
13511+/* Copyright 2013-2015 Freescale Semiconductor Inc.
13512+ *
13513+ * Redistribution and use in source and binary forms, with or without
13514+ * modification, are permitted provided that the following conditions are met:
13515+ * * Redistributions of source code must retain the above copyright
13516+ * notice, this list of conditions and the following disclaimer.
13517+ * * Redistributions in binary form must reproduce the above copyright
13518+ * notice, this list of conditions and the following disclaimer in the
13519+ * documentation and/or other materials provided with the distribution.
13520+ * * Neither the name of the above-listed copyright holders nor the
13521+ * names of any contributors may be used to endorse or promote products
13522+ * derived from this software without specific prior written permission.
13523+ *
13524+ *
13525+ * ALTERNATIVELY, this software may be distributed under the terms of the
13526+ * GNU General Public License ("GPL") as published by the Free Software
13527+ * Foundation, either version 2 of that License or (at your option) any
13528+ * later version.
13529+ *
13530+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
13531+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13532+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13533+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
13534+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
13535+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
13536+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
13537+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
13538+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
13539+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
13540+ * POSSIBILITY OF SUCH DAMAGE.
13541+ */
13542+#ifndef _FSL_DPCON_CMD_H
13543+#define _FSL_DPCON_CMD_H
13544+
13545+/* DPCON Version */
13546+#define DPCON_VER_MAJOR 2
13547+#define DPCON_VER_MINOR 2
13548+
13549+/* Command IDs */
13550+#define DPCON_CMDID_CLOSE 0x800
13551+#define DPCON_CMDID_OPEN 0x808
13552+#define DPCON_CMDID_CREATE 0x908
13553+#define DPCON_CMDID_DESTROY 0x900
13554+
13555+#define DPCON_CMDID_ENABLE 0x002
13556+#define DPCON_CMDID_DISABLE 0x003
13557+#define DPCON_CMDID_GET_ATTR 0x004
13558+#define DPCON_CMDID_RESET 0x005
13559+#define DPCON_CMDID_IS_ENABLED 0x006
13560+
13561+#define DPCON_CMDID_SET_IRQ 0x010
13562+#define DPCON_CMDID_GET_IRQ 0x011
13563+#define DPCON_CMDID_SET_IRQ_ENABLE 0x012
13564+#define DPCON_CMDID_GET_IRQ_ENABLE 0x013
13565+#define DPCON_CMDID_SET_IRQ_MASK 0x014
13566+#define DPCON_CMDID_GET_IRQ_MASK 0x015
13567+#define DPCON_CMDID_GET_IRQ_STATUS 0x016
13568+#define DPCON_CMDID_CLEAR_IRQ_STATUS 0x017
13569+
13570+#define DPCON_CMDID_SET_NOTIFICATION 0x100
13571+
13572+/* cmd, param, offset, width, type, arg_name */
13573+#define DPCON_CMD_OPEN(cmd, dpcon_id) \
13574+ MC_CMD_OP(cmd, 0, 0, 32, int, dpcon_id)
13575+
13576+/* cmd, param, offset, width, type, arg_name */
13577+#define DPCON_CMD_CREATE(cmd, cfg) \
13578+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_priorities)
13579+
13580+/* cmd, param, offset, width, type, arg_name */
13581+#define DPCON_RSP_IS_ENABLED(cmd, en) \
13582+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
13583+
13584+/* cmd, param, offset, width, type, arg_name */
13585+#define DPCON_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
13586+do { \
13587+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
13588+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
13589+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
13590+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
13591+} while (0)
13592+
13593+/* cmd, param, offset, width, type, arg_name */
13594+#define DPCON_CMD_GET_IRQ(cmd, irq_index) \
13595+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
13596+
13597+/* cmd, param, offset, width, type, arg_name */
13598+#define DPCON_RSP_GET_IRQ(cmd, type, irq_cfg) \
13599+do { \
13600+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val);\
13601+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
13602+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
13603+ MC_RSP_OP(cmd, 2, 32, 32, int, type);\
13604+} while (0)
13605+
13606+/* cmd, param, offset, width, type, arg_name */
13607+#define DPCON_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \
13608+do { \
13609+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \
13610+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
13611+} while (0)
13612+
13613+/* cmd, param, offset, width, type, arg_name */
13614+#define DPCON_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
13615+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
13616+
13617+/* cmd, param, offset, width, type, arg_name */
13618+#define DPCON_RSP_GET_IRQ_ENABLE(cmd, en) \
13619+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en)
13620+
13621+/* cmd, param, offset, width, type, arg_name */
13622+#define DPCON_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
13623+do { \
13624+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
13625+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
13626+} while (0)
13627+
13628+/* cmd, param, offset, width, type, arg_name */
13629+#define DPCON_CMD_GET_IRQ_MASK(cmd, irq_index) \
13630+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
13631+
13632+/* cmd, param, offset, width, type, arg_name */
13633+#define DPCON_RSP_GET_IRQ_MASK(cmd, mask) \
13634+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
13635+
13636+/* cmd, param, offset, width, type, arg_name */
13637+#define DPCON_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
13638+do { \
13639+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
13640+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
13641+} while (0)
13642+
13643+/* cmd, param, offset, width, type, arg_name */
13644+#define DPCON_RSP_GET_IRQ_STATUS(cmd, status) \
13645+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
13646+
13647+/* cmd, param, offset, width, type, arg_name */
13648+#define DPCON_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
13649+do { \
13650+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
13651+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
13652+} while (0)
13653+
13654+/* cmd, param, offset, width, type, arg_name */
13655+#define DPCON_RSP_GET_ATTR(cmd, attr) \
13656+do { \
13657+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\
13658+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qbman_ch_id);\
13659+ MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->num_priorities);\
13660+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
13661+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
13662+} while (0)
13663+
13664+/* cmd, param, offset, width, type, arg_name */
13665+#define DPCON_CMD_SET_NOTIFICATION(cmd, cfg) \
13666+do { \
13667+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dpio_id);\
13668+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->priority);\
13669+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx);\
13670+} while (0)
13671+
13672+#endif /* _FSL_DPCON_CMD_H */
13673diff --git a/drivers/net/dpaa2/mc/fsl_dpdbg.h b/drivers/net/dpaa2/mc/fsl_dpdbg.h
13674new file mode 100644
13675index 0000000..ead22e8
13676--- /dev/null
13677+++ b/drivers/net/dpaa2/mc/fsl_dpdbg.h
13678@@ -0,0 +1,635 @@
13679+/* Copyright 2013-2015 Freescale Semiconductor Inc.
13680+ *
13681+ * Redistribution and use in source and binary forms, with or without
13682+ * modification, are permitted provided that the following conditions are met:
13683+ * * Redistributions of source code must retain the above copyright
13684+ * notice, this list of conditions and the following disclaimer.
13685+ * * Redistributions in binary form must reproduce the above copyright
13686+ * notice, this list of conditions and the following disclaimer in the
13687+ * documentation and/or other materials provided with the distribution.
13688+ * * Neither the name of the above-listed copyright holders nor the
13689+ * names of any contributors may be used to endorse or promote products
13690+ * derived from this software without specific prior written permission.
13691+ *
13692+ *
13693+ * ALTERNATIVELY, this software may be distributed under the terms of the
13694+ * GNU General Public License ("GPL") as published by the Free Software
13695+ * Foundation, either version 2 of that License or (at your option) any
13696+ * later version.
13697+ *
13698+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
13699+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13700+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13701+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
13702+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
13703+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
13704+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
13705+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
13706+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
13707+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
13708+ * POSSIBILITY OF SUCH DAMAGE.
13709+ */
13710+#ifndef __FSL_DPDBG_H
13711+#define __FSL_DPDBG_H
13712+
13713+#include <fsl_dpkg.h>
13714+#include <fsl_dpmac.h>
13715+#include <fsl_dpni.h>
13716+
13717+/* Data Path Debug API
13718+ * Contains initialization APIs and runtime control APIs for DPDBG
13719+ */
13720+
13721+struct fsl_mc_io;
13722+
13723+/**
13724+ * dpdbg_open() - Open a control session for the specified object.
13725+ * @mc_io: Pointer to MC portal's I/O object
13726+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13727+ * @dpdbg_id: DPDBG unique ID
13728+ * @token: Returned token; use in subsequent API calls
13729+ *
13730+ * This function can be used to open a control session for an
13731+ * already created object;
13732+ * This function returns a unique authentication token,
13733+ * associated with the specific object ID and the specific MC
13734+ * portal; this token must be used in all subsequent commands for
13735+ * this specific object
13736+ *
13737+ * Return: '0' on Success; Error code otherwise.
13738+ */
13739+int dpdbg_open(struct fsl_mc_io *mc_io,
13740+ uint32_t cmd_flags,
13741+ int dpdbg_id,
13742+ uint16_t *token);
13743+
13744+/**
13745+ * dpdbg_close() - Close the control session of the object
13746+ * @mc_io: Pointer to MC portal's I/O object
13747+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13748+ * @token: Token of DPDBG object
13749+ *
13750+ * After this function is called, no further operations are
13751+ * allowed on the object without opening a new control session.
13752+ *
13753+ * Return: '0' on Success; Error code otherwise.
13754+ */
13755+int dpdbg_close(struct fsl_mc_io *mc_io,
13756+ uint32_t cmd_flags,
13757+ uint16_t token);
13758+
13759+/**
13760+ * struct dpdbg_attr - Structure representing DPDBG attributes
13761+ * @id: DPDBG object ID
13762+ * @version: DPDBG version
13763+ */
13764+struct dpdbg_attr {
13765+ int id;
13766+ /**
13767+ * struct version - Structure representing DPDBG version
13768+ * @major: DPDBG major version
13769+ * @minor: DPDBG minor version
13770+ */
13771+ struct {
13772+ uint16_t major;
13773+ uint16_t minor;
13774+ } version;
13775+};
13776+
13777+/**
13778+ * dpdbg_get_attributes - Retrieve DPDBG attributes.
13779+ * @mc_io: Pointer to MC portal's I/O object
13780+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13781+ * @token: Token of DPDBG object
13782+ * @attr: Returned object's attributes
13783+ *
13784+ * Return: '0' on Success; Error code otherwise.
13785+ */
13786+int dpdbg_get_attributes(struct fsl_mc_io *mc_io,
13787+ uint32_t cmd_flags,
13788+ uint16_t token,
13789+ struct dpdbg_attr *attr);
13790+
13791+/**
13792+ * struct dpdbg_dpni_info - Info of DPNI
13793+ * @max_senders: Maximum number of different senders; used as the number
13794+ * of dedicated Tx flows; Non-power-of-2 values are rounded
13795+ * up to the next power-of-2 value as hardware demands it;
13796+ * '0' will be treated as '1'
13797+ * @qdid: Virtual QDID.
13798+ * @err_fqid: Virtual FQID for error queues
13799+ * @tx_conf_fqid: Virtual FQID for global TX confirmation queue
13800+ */
13801+struct dpdbg_dpni_info {
13802+ uint8_t max_senders;
13803+ uint32_t qdid;
13804+ uint32_t err_fqid;
13805+ uint32_t tx_conf_fqid;
13806+};
13807+
13808+/**
13809+ * dpdbg_get_dpni_info() - Retrieve info for a specific DPNI
13810+ * @mc_io: Pointer to MC portal's I/O object
13811+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13812+ * @token: Token of DPDBG object
13813+ * @dpni_id: The requested DPNI ID
13814+ * @info: The returned info
13815+ *
13816+ * Return: '0' on Success; Error code otherwise.
13817+ */
13818+int dpdbg_get_dpni_info(struct fsl_mc_io *mc_io,
13819+ uint32_t cmd_flags,
13820+ uint16_t token,
13821+ int dpni_id,
13822+ struct dpdbg_dpni_info *info);
13823+
13824+/**
13825+ * dpdbg_get_dpni_private_fqid() - Retrieve the virtual TX confirmation queue
13826+ * FQID of the required DPNI
13827+ * @mc_io: Pointer to MC portal's I/O object
13828+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13829+ * @token: Token of DPDBG object
13830+ * @dpni_id: The requested DPNI ID
13831+ * @sender_id: The requested sender ID
13832+ * @fqid: The returned virtual private TX confirmation FQID.
13833+ *
13834+ * Return: '0' on Success; Error code otherwise.
13835+ */
13836+int dpdbg_get_dpni_priv_tx_conf_fqid(struct fsl_mc_io *mc_io,
13837+ uint32_t cmd_flags,
13838+ uint16_t token,
13839+ int dpni_id,
13840+ uint8_t sender_id,
13841+ uint32_t *fqid);
13842+
13843+/**
13844+ * struct dpdbg_dpcon_info - Info of DPCON
13845+ * @ch_id: Channel ID
13846+ */
13847+struct dpdbg_dpcon_info {
13848+ uint32_t ch_id;
13849+};
13850+
13851+/**
13852+ * dpdbg_get_dpcon_info() - Retrieve info of DPCON
13853+ * @mc_io: Pointer to MC portal's I/O object
13854+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13855+ * @token: Token of DPDBG object
13856+ * @dpcon_id: The requested DPCON ID
13857+ * @info: The returned info.
13858+ *
13859+ * Return: '0' on Success; Error code otherwise.
13860+ */
13861+int dpdbg_get_dpcon_info(struct fsl_mc_io *mc_io,
13862+ uint32_t cmd_flags,
13863+ uint16_t token,
13864+ int dpcon_id,
13865+ struct dpdbg_dpcon_info *info);
13866+
13867+/**
13868+ * struct dpdbg_dpbp_info - Info of DPBP
13869+ * @bpid: Virtual buffer pool ID
13870+ */
13871+struct dpdbg_dpbp_info {
13872+ uint32_t bpid;
13873+};
13874+
13875+/**
13876+ * dpdbg_get_dpbp_info() - Retrieve info of DPBP
13877+ * @mc_io: Pointer to MC portal's I/O object
13878+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13879+ * @token: Token of DPDBG object
13880+ * @dpbp_id: The requested DPBP ID
13881+ * @info: The returned info.
13882+ *
13883+ * Return: '0' on Success; Error code otherwise.
13884+ */
13885+int dpdbg_get_dpbp_info(struct fsl_mc_io *mc_io,
13886+ uint32_t cmd_flags,
13887+ uint16_t token,
13888+ int dpbp_id,
13889+ struct dpdbg_dpbp_info *info);
13890+
13891+/**
13892+ * dpdbg_get_dpci_fqid() - Retrieve the virtual FQID of the required DPCI
13893+ * @mc_io: Pointer to MC portal's I/O object
13894+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13895+ * @token: Token of DPDBG object
13896+ * @dpci_id: The requested DPCI ID
13897+ * @priority: Select the queue relative to number of priorities configured at
13898+ * DPCI creation
13899+ * @fqid: The returned virtual FQID.
13900+ *
13901+ * Return: '0' on Success; Error code otherwise.
13902+ */
13903+int dpdbg_get_dpci_fqid(struct fsl_mc_io *mc_io,
13904+ uint32_t cmd_flags,
13905+ uint16_t token,
13906+ int dpci_id,
13907+ uint8_t priority,
13908+ uint32_t *fqid);
13909+
13910+/**
13911+ * Maximum size for rule match (in bytes)
13912+ */
13913+#define DPDBG_MAX_RULE_SIZE 56
13914+/**
13915+ * Disable marking
13916+ */
13917+#define DPDBG_DISABLE_MARKING 0xFF
13918+
13919+/**
13920+ * dpdbg_prepare_ctlu_global_rule() - function prepare extract parameters
13921+ * @dpkg_rule: defining a full Key Generation profile (rule)
13922+ * @rule_buf: Zeroed 256 bytes of memory before mapping it to DMA
13923+ *
13924+ * This function has to be called before dpdbg_set_global_marking()
13925+ */
13926+int dpdbg_prepare_ctlu_global_rule(struct dpkg_profile_cfg *dpkg_rule,
13927+ uint8_t *rule_buf);
13928+
13929+/**
13930+ * struct dpdbg_rule_cfg - Rule configuration for table lookup
13931+ * @key_iova: I/O virtual address of the key (must be in DMA-able memory)
13932+ * @rule_iova: I/O virtual address of the rule (must be in DMA-able memory)
13933+ * @mask_iova: I/O virtual address of the mask (must be in DMA-able memory)
13934+ * @key_size: key and mask size (in bytes)
13935+ */
13936+struct dpdbg_rule_cfg {
13937+ uint64_t key_iova;
13938+ uint64_t mask_iova;
13939+ uint64_t rule_iova;
13940+ uint8_t key_size;
13941+};
13942+
13943+/**
13944+ * dpdbg_set_ctlu_global_marking() - Set marking for all match rule frames
13945+ * @mc_io: Pointer to MC portal's I/O object
13946+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13947+ * @token: Token of DPDBG object
13948+ * @marking: The requested Debug marking
13949+ * @cfg: Marking rule to add
13950+ *
13951+ * Warning: must be called after dpdbg_prepare_global_rule()
13952+ *
13953+ * Return: '0' on Success; Error code otherwise.
13954+ */
13955+int dpdbg_set_ctlu_global_marking(struct fsl_mc_io *mc_io,
13956+ uint32_t cmd_flags,
13957+ uint16_t token,
13958+ uint8_t marking,
13959+ struct dpdbg_rule_cfg *cfg);
13960+
13961+/**
13962+ * All traffic classes considered
13963+ */
13964+#define DPDBG_DPNI_ALL_TCS (uint8_t)(-1)
13965+/**
13966+ * All flows within traffic class considered
13967+ */
13968+#define DPDBG_DPNI_ALL_TC_FLOWS (uint8_t)(-1)
13969+/**
13970+ * All buffer pools considered
13971+ */
13972+#define DPDBG_DPNI_ALL_DPBP (uint8_t)(-1)
13973+
13974+/**
13975+ * struct dpdbg_dpni_rx_marking_cfg - Ingress frame configuration
13976+ * @tc_id: Traffic class ID (0-7); DPDBG_DPNI_ALL_TCS for all traffic classes.
13977+ * @flow_id: Rx flow id within the traffic class; use
13978+ * 'DPDBG_DPNI_ALL_TC_FLOWS' to set all flows within this tc_id;
13979+ * ignored if tc_id is set to 'DPDBG_DPNI_ALL_TCS';
13980+ * @dpbp_id: buffer pool ID; 'DPDBG_DPNI_ALL_DPBP' to set all DPBP
13981+ * @marking: Marking for match frames;
13982+ * 'DPDBG_DISABLE_MARKING' for disable marking
13983+ */
13984+struct dpdbg_dpni_rx_marking_cfg {
13985+ uint8_t tc_id;
13986+ uint16_t flow_id;
13987+ uint16_t dpbp_id;
13988+ uint8_t marking;
13989+};
13990+
13991+/**
13992+ * dpdbg_set_dpni_rx_marking() - Set Rx frame marking for DPNI
13993+ * @mc_io: Pointer to MC portal's I/O object
13994+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
13995+ * @token: Token of DPDBG object
13996+ * @dpni_id: The requested DPNI ID
13997+ * @cfg: RX frame marking configuration
13998+ *
13999+ * Return: '0' on Success; Error code otherwise.
14000+ */
14001+int dpdbg_set_dpni_rx_marking(struct fsl_mc_io *mc_io,
14002+ uint32_t cmd_flags,
14003+ uint16_t token,
14004+ int dpni_id,
14005+ struct dpdbg_dpni_rx_marking_cfg *cfg);
14006+
14007+/* selects global confirmation queues */
14008+#define DPDBG_DPNI_GLOBAL_TX_CONF_QUEUE (uint16_t)(-1)
14009+
14010+/**
14011+ * dpdbg_set_dpni_tx_conf_marking() - Set Tx frame marking for DPNI
14012+ *
14013+ * @mc_io: Pointer to MC portal's I/O object
14014+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14015+ * @token: Token of DPDBG object
14016+ * @dpni_id: The requested DPNI ID
14017+ * @sender_id: Sender Id for the confirmation queue;
14018+ * 'DPDBG_DPNI_GLOBAL_TX_CONF_QUEUE' for global confirmation queue
14019+ * @marking: The requested marking;
14020+ * 'DPDBG_DISABLE_MARKING' for disable marking
14021+ *
14022+ * Return: '0' on Success; Error code otherwise.
14023+ */
14024+int dpdbg_set_dpni_tx_conf_marking(struct fsl_mc_io *mc_io,
14025+ uint32_t cmd_flags,
14026+ uint16_t token,
14027+ int dpni_id,
14028+ uint16_t sender_id,
14029+ uint8_t marking);
14030+
14031+/**
14032+ * dpdbg_set_dpio_marking() - Set debug frame marking on enqueue
14033+ * @mc_io: Pointer to MC portal's I/O object
14034+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14035+ * @token: Token of DPDBG object
14036+ * @dpio_id: The requested DPIO ID
14037+ * @marking: The requested marking;
14038+ * 'DPDBG_DISABLE_MARKING' for disable marking
14039+ * Return: '0' on Success; Error code otherwise.
14040+ */
14041+int dpdbg_set_dpio_marking(struct fsl_mc_io *mc_io,
14042+ uint32_t cmd_flags,
14043+ uint16_t token,
14044+ int dpio_id,
14045+ uint8_t marking);
14046+
14047+/**
14048+ * enum dpdbg_verbosity_level - Trace verbosity level
14049+ * @DPDBG_VERBOSITY_LEVEL_DISABLE: Trace disabled
14050+ * @DPDBG_VERBOSITY_LEVEL_TERSE: Terse trace
14051+ * @DPDBG_VERBOSITY_LEVEL_VERBOSE: Verbose trace
14052+ */
14053+enum dpdbg_verbosity_level {
14054+ DPDBG_VERBOSITY_LEVEL_DISABLE = 0,
14055+ DPDBG_VERBOSITY_LEVEL_TERSE,
14056+ DPDBG_VERBOSITY_LEVEL_VERBOSE
14057+};
14058+
14059+/**
14060+ * dpdbg_set_ctlu_global_trace() - Set global trace configuration for CTLU trace
14061+ *
14062+ * @mc_io: Pointer to MC portal's I/O object
14063+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14064+ * @token: Token of DPDBG object
14065+ * @cfg: trace rule to add
14066+ *
14067+ * Warning: must be called after dpdbg_prepare_global_rule()
14068+ *
14069+ * Return: '0' on Success; Error code otherwise.
14070+ */
14071+int dpdbg_set_ctlu_global_trace(struct fsl_mc_io *mc_io,
14072+ uint32_t cmd_flags,
14073+ uint16_t token,
14074+ struct dpdbg_rule_cfg *cfg);
14075+
14076+/**
14077+ * Number of DPIO trace points
14078+ */
14079+#define DPDBG_NUM_OF_DPIO_TRACE_POINTS 2
14080+
14081+/**
14082+ * enum dpdbg_dpio_trace_type - Define Trace point type
14083+ * @DPDBG_DPIO_TRACE_TYPE_ENQUEUE: This trace point triggers when an enqueue
14084+ * command, received via this portal,
14085+ * and containing a marked frame, is executed
14086+ * @DPDBG_DPIO_TRACE_TYPE_DEFERRED: This trace point triggers when the deferred
14087+ * enqueue of a marked frame received via this
14088+ * portal completes
14089+ */
14090+enum dpdbg_dpio_trace_type {
14091+ DPDBG_DPIO_TRACE_TYPE_ENQUEUE = 0,
14092+ DPDBG_DPIO_TRACE_TYPE_DEFERRED = 1
14093+};
14094+
14095+/**
14096+ * struct dpdbg_dpio_trace_cfg - Configure the behavior of a trace point
14097+ * when a frame marked with the specified DD code point is
14098+ * encountered
14099+ * @marking: this field will be written into the DD field of every FD
14100+ * enqueued in this DPIO.
14101+ * 'DPDBG_DISABLE_MARKING' for disable marking
14102+ * @verbosity: Verbosity level
14103+ * @enqueue_type: Enqueue trace point type defining a full Key Generation
14104+ * profile (rule)
14105+ */
14106+struct dpdbg_dpio_trace_cfg {
14107+ uint8_t marking;
14108+ enum dpdbg_verbosity_level verbosity;
14109+ enum dpdbg_dpio_trace_type enqueue_type;
14110+};
14111+
14112+/**
14113+ * dpdbg_set_dpio_trace() - Set trace for DPIO for every enqueued frame to
14114+ * the portal
14115+ *
14116+ * @mc_io: Pointer to MC portal's I/O object
14117+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14118+ * @token: Token of DPDBG object
14119+ * @dpio_id: The requested DPIO ID
14120+ * @trace_point: Trace points configuration
14121+ *
14122+ * Return: '0' on Success; Error code otherwise.
14123+ */
14124+int dpdbg_set_dpio_trace(struct fsl_mc_io *mc_io,
14125+ uint32_t cmd_flags,
14126+ uint16_t token,
14127+ int dpio_id,
14128+ struct dpdbg_dpio_trace_cfg
14129+ trace_point[DPDBG_NUM_OF_DPIO_TRACE_POINTS]);
14130+
14131+/**
14132+ * struct dpdbg_dpni_trace_cfg - Configure the behavior of a trace point when a
14133+ * @tc_id: Traffic class ID (0-7); DPDBG_DPNI_ALL_TCS for all traffic classes.
14134+ * @flow_id: Rx flow id within the traffic class; use
14135+ * 'DPDBG_DPNI_ALL_TC_FLOWS' to set all flows within this tc_id;
14136+ * ignored if tc_id is set to 'DPDBG_DPNI_ALL_TCS';
14137+ * @dpbp_id: buffer pool ID; 'DPDBG_DPNI_ALL_DPBP' to set all DPBP
14138+ * @marking: Marking for match frames;
14139+ * 'DPDBG_DISABLE_MARKING' for disable marking
14140+ */
14141+struct dpdbg_dpni_rx_trace_cfg {
14142+ uint8_t tc_id;
14143+ uint16_t flow_id;
14144+ uint16_t dpbp_id;
14145+ uint8_t marking;
14146+};
14147+
14148+/**
14149+ * dpdbg_set_dpni_rx_trace() - Set trace for DPNI ingress (WRIOP ingress).
14150+ * in case of multiple requests for different DPNIs - the trace
14151+ * will be for the latest DPNI requested.
14152+ *
14153+ * @mc_io: Pointer to MC portal's I/O object
14154+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14155+ * @token: Token of DPDBG object
14156+ * @dpni_id: The requested DPNI ID
14157+ * @trace_cfg: Trace configuration
14158+ *
14159+ * Return: '0' on Success; Error code otherwise.
14160+ */
14161+int dpdbg_set_dpni_rx_trace(struct fsl_mc_io *mc_io,
14162+ uint32_t cmd_flags,
14163+ uint16_t token,
14164+ int dpni_id,
14165+ struct dpdbg_dpni_rx_trace_cfg *trace_cfg);
14166+
14167+/**
14168+ * All DPNI senders
14169+ */
14170+#define DPDBG_DPNI_ALL_SENDERS (uint16_t)(-1)
14171+
14172+/**
14173+ * struct dpdbg_dpni_trace_cfg - Configure the behavior of a trace point when a
14174+ * frame marked with the specified DD code point is encountered
14175+ * @marking: The requested debug marking;
14176+ * 'DPDBG_DISABLE_MARKING' for disable marking
14177+ */
14178+struct dpdbg_dpni_tx_trace_cfg {
14179+ uint8_t marking;
14180+};
14181+
14182+/**
14183+ * dpdbg_set_dpni_tx_trace() - Set trace for DPNI dequeued frames
14184+ *
14185+ * @mc_io: Pointer to MC portal's I/O object
14186+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14187+ * @token: Token of DPDBG object
14188+ * @dpni_id: The requested DPNI ID
14189+ * @sender_id: Sender ID; 'DPDBG_DPNI_ALL_SENDERS' for all senders
14190+ * @trace_cfg: Trace configuration
14191+ *
14192+ * Return: '0' on Success; Error code otherwise.
14193+ */
14194+int dpdbg_set_dpni_tx_trace(struct fsl_mc_io *mc_io,
14195+ uint32_t cmd_flags,
14196+ uint16_t token,
14197+ int dpni_id,
14198+ uint16_t sender_id,
14199+ struct dpdbg_dpni_tx_trace_cfg *trace_cfg);
14200+
14201+/**
14202+ * Number of DPCON trace points
14203+ */
14204+#define DPDBG_NUM_OF_DPCON_TRACE_POINTS 2
14205+
14206+/**
14207+ * struct dpdbg_dpcon_trace_cfg - Configure the behavior of a trace point when a
14208+ * frame marked with the specified DD code point is encountered
14209+ * @marking: The requested debug marking;
14210+ * 'DPDBG_DISABLE_MARKING' for disable marking
14211+ * @verbosity: Verbosity level
14212+ */
14213+struct dpdbg_dpcon_trace_cfg {
14214+ uint8_t marking;
14215+ enum dpdbg_verbosity_level verbosity;
14216+};
14217+
14218+/**
14219+ * dpdbg_set_dpcon_trace() - Set trace for DPCON when a frame marked with a
14220+ * specified marking is dequeued from a WQ in the
14221+ * channel selected
14222+ *
14223+ * @mc_io: Pointer to MC portal's I/O object
14224+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14225+ * @token: Token of DPDBG object
14226+ * @dpcon_id: The requested DPCON ID
14227+ * @trace_point: Trace points configuration
14228+ *
14229+ * Return: '0' on Success; Error code otherwise.
14230+ */
14231+int dpdbg_set_dpcon_trace(struct fsl_mc_io *mc_io,
14232+ uint32_t cmd_flags,
14233+ uint16_t token,
14234+ int dpcon_id,
14235+ struct dpdbg_dpcon_trace_cfg
14236+ trace_point[DPDBG_NUM_OF_DPCON_TRACE_POINTS]);
14237+
14238+/**
14239+ * Number of DPSECI trace points
14240+ */
14241+#define DPDBG_NUM_OF_DPSECI_TRACE_POINTS 2
14242+
14243+/**
14244+ * struct dpdbg_dpseci_trace_cfg - Configure the behavior of a trace point when
14245+ * a frame marked with the specified DD code point is
14246+ * encountered
14247+ * @marking: The requested debug marking;
14248+ * 'DPDBG_DISABLE_MARKING' for disable marking
14249+ * @verbosity: Verbosity level
14250+ */
14251+struct dpdbg_dpseci_trace_cfg {
14252+ uint8_t marking;
14253+ enum dpdbg_verbosity_level verbosity;
14254+};
14255+
14256+/**
14257+ * dpdbg_set_dpseci_trace() - Set trace for DPSECI when a frame marked with the
14258+ * specific marking is enqueued via this portal.
14259+ *
14260+ * @mc_io: Pointer to MC portal's I/O object
14261+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14262+ * @token: Token of DPDBG object
14263+ * @dpseci_id: The requested DPSECI ID
14264+ * @trace_point: Trace points configuration
14265+ *
14266+ * Return: '0' on Success; Error code otherwise.
14267+ */
14268+int dpdbg_set_dpseci_trace(struct fsl_mc_io *mc_io,
14269+ uint32_t cmd_flags,
14270+ uint16_t token,
14271+ int dpseci_id,
14272+ struct dpdbg_dpseci_trace_cfg
14273+ trace_point[DPDBG_NUM_OF_DPSECI_TRACE_POINTS]);
14274+
14275+/**
14276+ * dpdbg_get_dpmac_counter() - DPMAC packet throughput
14277+ *
14278+ * @mc_io: Pointer to MC portal's I/O object
14279+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14280+ * @token: Token of DPDBG object
14281+ * @dpmac_id: The requested DPMAC ID
14282+ * @counter_type: The requested DPMAC counter
14283+ * @counter: Returned counter value
14284+ *
14285+ * Return: '0' on Success; Error code otherwise.
14286+ */
14287+int dpdbg_get_dpmac_counter(struct fsl_mc_io *mc_io,
14288+ uint32_t cmd_flags,
14289+ uint16_t token,
14290+ int dpmac_id,
14291+ enum dpmac_counter counter_type,
14292+ uint64_t *counter);
14293+
14294+/**
14295+ * dpdbg_get_dpni_counter() - DPNI packet throughput
14296+ *
14297+ * @mc_io: Pointer to MC portal's I/O object
14298+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14299+ * @token: Token of DPDBG object
14300+ * @dpni_id: The requested DPNI ID
14301+ * @counter_type: The requested DPNI counter
14302+ * @counter: Returned counter value
14303+ *
14304+ * Return: '0' on Success; Error code otherwise.
14305+ */
14306+int dpdbg_get_dpni_counter(struct fsl_mc_io *mc_io,
14307+ uint32_t cmd_flags,
14308+ uint16_t token,
14309+ int dpni_id,
14310+ enum dpni_counter counter_type,
14311+ uint64_t *counter);
14312+
14313+#endif /* __FSL_DPDBG_H */
14314diff --git a/drivers/net/dpaa2/mc/fsl_dpdbg_cmd.h b/drivers/net/dpaa2/mc/fsl_dpdbg_cmd.h
14315new file mode 100644
14316index 0000000..b672788
14317--- /dev/null
14318+++ b/drivers/net/dpaa2/mc/fsl_dpdbg_cmd.h
14319@@ -0,0 +1,249 @@
14320+/* Copyright 2013-2015 Freescale Semiconductor Inc.
14321+ *
14322+ * Redistribution and use in source and binary forms, with or without
14323+ * modification, are permitted provided that the following conditions are met:
14324+ * * Redistributions of source code must retain the above copyright
14325+ * notice, this list of conditions and the following disclaimer.
14326+ * * Redistributions in binary form must reproduce the above copyright
14327+ * notice, this list of conditions and the following disclaimer in the
14328+ * documentation and/or other materials provided with the distribution.
14329+ * * Neither the name of the above-listed copyright holders nor the
14330+ * names of any contributors may be used to endorse or promote products
14331+ * derived from this software without specific prior written permission.
14332+ *
14333+ *
14334+ * ALTERNATIVELY, this software may be distributed under the terms of the
14335+ * GNU General Public License ("GPL") as published by the Free Software
14336+ * Foundation, either version 2 of that License or (at your option) any
14337+ * later version.
14338+ *
14339+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
14340+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
14341+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
14342+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
14343+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
14344+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
14345+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
14346+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
14347+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
14348+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
14349+ * POSSIBILITY OF SUCH DAMAGE.
14350+ */
14351+#ifndef _FSL_DPDBG_CMD_H
14352+#define _FSL_DPDBG_CMD_H
14353+
14354+/* DPDBG Version */
14355+#define DPDBG_VER_MAJOR 1
14356+#define DPDBG_VER_MINOR 0
14357+
14358+/* Command IDs */
14359+#define DPDBG_CMDID_CLOSE 0x800
14360+#define DPDBG_CMDID_OPEN 0x80F
14361+
14362+#define DPDBG_CMDID_GET_ATTR 0x004
14363+
14364+#define DPDBG_CMDID_GET_DPNI_INFO 0x130
14365+#define DPDBG_CMDID_GET_DPNI_PRIV_TX_CONF_FQID 0x131
14366+#define DPDBG_CMDID_GET_DPCON_INFO 0x132
14367+#define DPDBG_CMDID_GET_DPBP_INFO 0x133
14368+#define DPDBG_CMDID_GET_DPCI_FQID 0x134
14369+
14370+#define DPDBG_CMDID_SET_CTLU_GLOBAL_MARKING 0x135
14371+#define DPDBG_CMDID_SET_DPNI_RX_MARKING 0x136
14372+#define DPDBG_CMDID_SET_DPNI_TX_CONF_MARKING 0x137
14373+#define DPDBG_CMDID_SET_DPIO_MARKING 0x138
14374+
14375+#define DPDBG_CMDID_SET_CTLU_GLOBAL_TRACE 0x140
14376+#define DPDBG_CMDID_SET_DPIO_TRACE 0x141
14377+#define DPDBG_CMDID_SET_DPNI_RX_TRACE 0x142
14378+#define DPDBG_CMDID_SET_DPNI_TX_TRACE 0x143
14379+#define DPDBG_CMDID_SET_DPCON_TRACE 0x145
14380+#define DPDBG_CMDID_SET_DPSECI_TRACE 0x146
14381+
14382+#define DPDBG_CMDID_GET_DPMAC_COUNTER 0x150
14383+#define DPDBG_CMDID_GET_DPNI_COUNTER 0x151
14384+
14385+/* cmd, param, offset, width, type, arg_name */
14386+#define DPDBG_CMD_OPEN(cmd, dpdbg_id) \
14387+ MC_CMD_OP(cmd, 0, 0, 32, int, dpdbg_id)
14388+
14389+/* cmd, param, offset, width, type, arg_name */
14390+#define DPDBG_RSP_GET_ATTRIBUTES(cmd, attr) \
14391+do { \
14392+ MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\
14393+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
14394+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
14395+} while (0)
14396+
14397+/* cmd, param, offset, width, type, arg_name */
14398+#define DPDBG_CMD_GET_DPNI_INFO(cmd, dpni_id) \
14399+ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id)
14400+
14401+/* cmd, param, offset, width, type, arg_name */
14402+#define DPDBG_RSP_GET_DPNI_INFO(cmd, info) \
14403+do { \
14404+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, info->qdid);\
14405+ MC_RSP_OP(cmd, 1, 32, 8, uint8_t, info->max_senders);\
14406+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, info->err_fqid);\
14407+ MC_RSP_OP(cmd, 2, 32, 32, uint32_t, info->tx_conf_fqid);\
14408+} while (0)
14409+
14410+/* cmd, param, offset, width, type, arg_name */
14411+#define DPDBG_CMD_GET_DPNI_PRIV_TX_CONF_FQID(cmd, dpni_id, sender_id) \
14412+do { \
14413+ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id);\
14414+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, sender_id);\
14415+} while (0)
14416+
14417+/* cmd, param, offset, width, type, arg_name */
14418+#define DPDBG_RSP_GET_DPNI_PRIV_TX_CONF_FQID(cmd, fqid) \
14419+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, fqid)
14420+
14421+/* cmd, param, offset, width, type, arg_name */
14422+#define DPDBG_CMD_GET_DPCON_INFO(cmd, dpcon_id) \
14423+ MC_CMD_OP(cmd, 0, 0, 32, int, dpcon_id)
14424+
14425+/* cmd, param, offset, width, type, arg_name */
14426+#define DPDBG_RSP_GET_DPCON_INFO(cmd, info) \
14427+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, info->ch_id)
14428+
14429+/* cmd, param, offset, width, type, arg_name */
14430+#define DPDBG_CMD_GET_DPBP_INFO(cmd, dpbp_id) \
14431+ MC_CMD_OP(cmd, 0, 0, 32, int, dpbp_id)
14432+
14433+/* cmd, param, offset, width, type, arg_name */
14434+#define DPDBG_RSP_GET_DPBP_INFO(cmd, info) \
14435+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, info->bpid)
14436+
14437+/* cmd, param, offset, width, type, arg_name */
14438+#define DPDBG_CMD_GET_DPCI_FQID(cmd, dpci_id, priority) \
14439+do { \
14440+ MC_CMD_OP(cmd, 0, 0, 32, int, dpci_id);\
14441+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, priority);\
14442+} while (0)
14443+/* cmd, param, offset, width, type, arg_name */
14444+#define DPDBG_RSP_GET_DPCI_FQID(cmd, fqid) \
14445+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, fqid)
14446+
14447+/* cmd, param, offset, width, type, arg_name */
14448+#define DPDBG_CMD_SET_CTLU_GLOBAL_MARKING(cmd, marking, cfg) \
14449+do { \
14450+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, marking);\
14451+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->key_size); \
14452+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->key_iova); \
14453+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->mask_iova); \
14454+ MC_CMD_OP(cmd, 3, 0, 64, uint64_t, cfg->rule_iova); \
14455+} while (0)
14456+
14457+#define DPDBG_CMD_SET_DPNI_RX_MARKING(cmd, dpni_id, cfg) \
14458+do { \
14459+ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id);\
14460+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->tc_id);\
14461+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, cfg->flow_id);\
14462+ MC_CMD_OP(cmd, 1, 0, 16, uint16_t, cfg->dpbp_id);\
14463+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->marking);\
14464+} while (0)
14465+
14466+#define DPDBG_CMD_SET_DPNI_TX_CONF_MARKING(cmd, dpni_id, sender_id, marking) \
14467+do { \
14468+ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id);\
14469+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, sender_id);\
14470+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, marking);\
14471+} while (0)
14472+
14473+#define DPDBG_CMD_SET_DPIO_MARKING(cmd, dpio_id, marking) \
14474+do { \
14475+ MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id);\
14476+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, marking);\
14477+} while (0)
14478+
14479+/* cmd, param, offset, width, type, arg_name */
14480+#define DPDBG_CMD_SET_CTLU_GLOBAL_TRACE(cmd, cfg) \
14481+do { \
14482+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->key_size); \
14483+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->key_iova); \
14484+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->mask_iova); \
14485+ MC_CMD_OP(cmd, 3, 0, 64, uint64_t, cfg->rule_iova); \
14486+} while (0)
14487+
14488+/* cmd, param, offset, width, type, arg_name */
14489+#define DPDBG_CMD_SET_DPIO_TRACE(cmd, dpio_id, trace_point) \
14490+do { \
14491+ MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id);\
14492+ MC_CMD_OP(cmd, 1, 0, 4, enum dpdbg_verbosity_level, \
14493+ trace_point[0].verbosity); \
14494+ MC_CMD_OP(cmd, 1, 4, 4, enum dpdbg_dpio_trace_type, \
14495+ trace_point[0].enqueue_type); \
14496+ MC_CMD_OP(cmd, 1, 8, 8, uint8_t, trace_point[0].marking); \
14497+ MC_CMD_OP(cmd, 1, 32, 4, enum dpdbg_verbosity_level, \
14498+ trace_point[1].verbosity); \
14499+ MC_CMD_OP(cmd, 1, 36, 4, enum dpdbg_dpio_trace_type, \
14500+ trace_point[1].enqueue_type); \
14501+ MC_CMD_OP(cmd, 1, 40, 8, uint8_t, trace_point[1].marking); \
14502+} while (0)
14503+
14504+/* cmd, param, offset, width, type, arg_name */
14505+#define DPDBG_CMD_SET_DPNI_RX_TRACE(cmd, dpni_id, trace_cfg) \
14506+do { \
14507+ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id);\
14508+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, trace_cfg->tc_id);\
14509+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, trace_cfg->flow_id);\
14510+ MC_CMD_OP(cmd, 1, 0, 16, uint16_t, trace_cfg->dpbp_id);\
14511+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, trace_cfg->marking);\
14512+} while (0)
14513+
14514+/* cmd, param, offset, width, type, arg_name */
14515+#define DPDBG_CMD_SET_DPNI_TX_TRACE(cmd, dpni_id, sender_id, trace_cfg) \
14516+do { \
14517+ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id);\
14518+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, sender_id);\
14519+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, trace_cfg->marking);\
14520+} while (0)
14521+
14522+/* cmd, param, offset, width, type, arg_name */
14523+#define DPDBG_CMD_SET_DPCON_TRACE(cmd, dpcon_id, trace_point) \
14524+do { \
14525+ MC_CMD_OP(cmd, 0, 0, 32, int, dpcon_id);\
14526+ MC_CMD_OP(cmd, 1, 0, 4, enum dpdbg_verbosity_level, \
14527+ trace_point[0].verbosity); \
14528+ MC_CMD_OP(cmd, 1, 8, 8, uint8_t, trace_point[0].marking); \
14529+ MC_CMD_OP(cmd, 1, 32, 4, enum dpdbg_verbosity_level, \
14530+ trace_point[1].verbosity); \
14531+ MC_CMD_OP(cmd, 1, 40, 8, uint8_t, trace_point[1].marking); \
14532+} while (0)
14533+
14534+/* cmd, param, offset, width, type, arg_name */
14535+#define DPDBG_CMD_SET_DPSECI_TRACE(cmd, dpseci_id, trace_point) \
14536+do { \
14537+ MC_CMD_OP(cmd, 0, 0, 32, int, dpseci_id);\
14538+ MC_CMD_OP(cmd, 1, 0, 4, enum dpdbg_verbosity_level, \
14539+ trace_point[0].verbosity); \
14540+ MC_CMD_OP(cmd, 1, 8, 8, uint8_t, trace_point[0].marking); \
14541+ MC_CMD_OP(cmd, 1, 32, 4, enum dpdbg_verbosity_level, \
14542+ trace_point[1].verbosity); \
14543+ MC_CMD_OP(cmd, 1, 40, 8, uint8_t, trace_point[1].marking); \
14544+} while (0)
14545+
14546+/* cmd, param, offset, width, type, arg_name */
14547+#define DPDBG_CMD_GET_DPMAC_COUNTER(cmd, dpmac_id, counter_type) \
14548+do { \
14549+ MC_CMD_OP(cmd, 0, 0, 32, int, dpmac_id);\
14550+ MC_CMD_OP(cmd, 0, 32, 16, enum dpmac_counter, counter_type);\
14551+} while (0)
14552+
14553+/* cmd, param, offset, width, type, arg_name */
14554+#define DPDBG_RSP_GET_DPMAC_COUNTER(cmd, counter) \
14555+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter)
14556+
14557+/* cmd, param, offset, width, type, arg_name */
14558+#define DPDBG_CMD_GET_DPNI_COUNTER(cmd, dpni_id, counter_type) \
14559+do { \
14560+ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id);\
14561+ MC_CMD_OP(cmd, 0, 32, 16, enum dpni_counter, counter_type);\
14562+} while (0)
14563+
14564+/* cmd, param, offset, width, type, arg_name */
14565+#define DPDBG_RSP_GET_DPNI_COUNTER(cmd, counter) \
14566+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter)
14567+
14568+#endif /* _FSL_DPDBG_CMD_H */
14569diff --git a/drivers/net/dpaa2/mc/fsl_dpdcei.h b/drivers/net/dpaa2/mc/fsl_dpdcei.h
14570new file mode 100644
14571index 0000000..319795c
14572--- /dev/null
14573+++ b/drivers/net/dpaa2/mc/fsl_dpdcei.h
14574@@ -0,0 +1,515 @@
14575+/* Copyright 2013-2015 Freescale Semiconductor Inc.
14576+ *
14577+ * Redistribution and use in source and binary forms, with or without
14578+ * modification, are permitted provided that the following conditions are met:
14579+ * * Redistributions of source code must retain the above copyright
14580+ * notice, this list of conditions and the following disclaimer.
14581+ * * Redistributions in binary form must reproduce the above copyright
14582+ * notice, this list of conditions and the following disclaimer in the
14583+ * documentation and/or other materials provided with the distribution.
14584+ * * Neither the name of the above-listed copyright holders nor the
14585+ * names of any contributors may be used to endorse or promote products
14586+ * derived from this software without specific prior written permission.
14587+ *
14588+ *
14589+ * ALTERNATIVELY, this software may be distributed under the terms of the
14590+ * GNU General Public License ("GPL") as published by the Free Software
14591+ * Foundation, either version 2 of that License or (at your option) any
14592+ * later version.
14593+ *
14594+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
14595+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
14596+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
14597+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
14598+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
14599+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
14600+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
14601+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
14602+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
14603+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
14604+ * POSSIBILITY OF SUCH DAMAGE.
14605+ */
14606+#ifndef __FSL_DPDCEI_H
14607+#define __FSL_DPDCEI_H
14608+
14609+/* Data Path DCE Interface API
14610+ * Contains initialization APIs and runtime control APIs for DPDCEI
14611+ */
14612+
14613+struct fsl_mc_io;
14614+
14615+/** General DPDCEI macros */
14616+
14617+/**
14618+ * Indicates an invalid frame queue
14619+ */
14620+#define DPDCEI_FQID_NOT_VALID (uint32_t)(-1)
14621+
14622+/**
14623+ * enum dpdcei_engine - DCE engine block
14624+ * @DPDCEI_ENGINE_COMPRESSION: Engine compression
14625+ * @DPDCEI_ENGINE_DECOMPRESSION: Engine decompression
14626+ */
14627+enum dpdcei_engine {
14628+ DPDCEI_ENGINE_COMPRESSION,
14629+ DPDCEI_ENGINE_DECOMPRESSION
14630+};
14631+
14632+/**
14633+ * dpdcei_open() - Open a control session for the specified object
14634+ * @mc_io: Pointer to MC portal's I/O object
14635+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14636+ * @token: Token of DPDCEI object
14637+ * @dpdcei_id: DPDCEI unique ID
14638+ *
14639+ * This function can be used to open a control session for an
14640+ * already created object; an object may have been declared in
14641+ * the DPL or by calling the dpdcei_create() function.
14642+ * This function returns a unique authentication token,
14643+ * associated with the specific object ID and the specific MC
14644+ * portal; this token must be used in all subsequent commands for
14645+ * this specific object.
14646+ *
14647+ * Return: '0' on Success; Error code otherwise.
14648+ */
14649+int dpdcei_open(struct fsl_mc_io *mc_io,
14650+ uint32_t cmd_flags,
14651+ int dpdcei_id,
14652+ uint16_t *token);
14653+
14654+/**
14655+ * dpdcei_close() - Close the control session of the object
14656+ * @mc_io: Pointer to MC portal's I/O object
14657+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14658+ * @token: Token of DPDCEI object
14659+ *
14660+ * After this function is called, no further operations are
14661+ * allowed on the object without opening a new control session.
14662+ *
14663+ * Return: '0' on Success; Error code otherwise.
14664+ */
14665+int dpdcei_close(struct fsl_mc_io *mc_io,
14666+ uint32_t cmd_flags,
14667+ uint16_t token);
14668+
14669+/**
14670+ * struct dpdcei_cfg - Structure representing DPDCEI configuration
14671+ * @engine: compression or decompression engine to be selected
14672+ * @priority: Priority for the DCE hardware processing (valid values 1-8).
14673+ */
14674+struct dpdcei_cfg {
14675+ enum dpdcei_engine engine;
14676+ uint8_t priority;
14677+};
14678+
14679+/**
14680+ * dpdcei_create() - Create the DPDCEI object
14681+ * @mc_io: Pointer to MC portal's I/O object
14682+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14683+ * @token: Token of DPDCEI object
14684+ * @cfg: configuration parameters
14685+ *
14686+ * Create the DPDCEI object, allocate required resources and
14687+ * perform required initialization.
14688+ *
14689+ * The object can be created either by declaring it in the
14690+ * DPL file, or by calling this function.
14691+ *
14692+ * This function returns a unique authentication token,
14693+ * associated with the specific object ID and the specific MC
14694+ * portal; this token must be used in all subsequent calls to
14695+ * this specific object. For objects that are created using the
14696+ * DPL file, call dpdcei_open() function to get an authentication
14697+ * token first.
14698+ *
14699+ * Return: '0' on Success; Error code otherwise.
14700+ */
14701+int dpdcei_create(struct fsl_mc_io *mc_io,
14702+ uint32_t cmd_flags,
14703+ const struct dpdcei_cfg *cfg,
14704+ uint16_t *token);
14705+
14706+/**
14707+ * dpdcei_destroy() - Destroy the DPDCEI object and release all its resources.
14708+ * @mc_io: Pointer to MC portal's I/O object
14709+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14710+ * @token: Token of DPDCEI object
14711+ *
14712+ * Return: '0' on Success; error code otherwise.
14713+ */
14714+int dpdcei_destroy(struct fsl_mc_io *mc_io,
14715+ uint32_t cmd_flags,
14716+ uint16_t token);
14717+
14718+/**
14719+ * dpdcei_enable() - Enable the DPDCEI, allow sending and receiving frames.
14720+ * @mc_io: Pointer to MC portal's I/O object
14721+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14722+ * @token: Token of DPDCEI object
14723+ *
14724+ * Return: '0' on Success; Error code otherwise.
14725+ */
14726+int dpdcei_enable(struct fsl_mc_io *mc_io,
14727+ uint32_t cmd_flags,
14728+ uint16_t token);
14729+
14730+/**
14731+ * dpdcei_disable() - Disable the DPDCEI, stop sending and receiving frames.
14732+ * @mc_io: Pointer to MC portal's I/O object
14733+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14734+ * @token: Token of DPDCEI object
14735+ *
14736+ * Return: '0' on Success; Error code otherwise.
14737+ */
14738+int dpdcei_disable(struct fsl_mc_io *mc_io,
14739+ uint32_t cmd_flags,
14740+ uint16_t token);
14741+
14742+/**
14743+ * dpdcei_is_enabled() - Check if the DPDCEI is enabled.
14744+ * @mc_io: Pointer to MC portal's I/O object
14745+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14746+ * @token: Token of DPDCEI object
14747+ * @en: Return '1' for object enabled/'0' otherwise
14748+ *
14749+ * Return: '0' on Success; Error code otherwise.
14750+ */
14751+int dpdcei_is_enabled(struct fsl_mc_io *mc_io,
14752+ uint32_t cmd_flags,
14753+ uint16_t token,
14754+ int *en);
14755+
14756+/**
14757+ * dpdcei_reset() - Reset the DPDCEI, returns the object to initial state.
14758+ * @mc_io: Pointer to MC portal's I/O object
14759+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14760+ * @token: Token of DPDCEI object
14761+ *
14762+ * Return: '0' on Success; Error code otherwise.
14763+ */
14764+int dpdcei_reset(struct fsl_mc_io *mc_io,
14765+ uint32_t cmd_flags,
14766+ uint16_t token);
14767+
14768+/**
14769+ * struct dpdcei_irq_cfg - IRQ configuration
14770+ * @addr: Address that must be written to signal a message-based interrupt
14771+ * @val: Value to write into irq_addr address
14772+ * @irq_num: A user defined number associated with this IRQ
14773+ */
14774+struct dpdcei_irq_cfg {
14775+ uint64_t addr;
14776+ uint32_t val;
14777+ int irq_num;
14778+};
14779+
14780+/**
14781+ * dpdcei_set_irq() - Set IRQ information for the DPDCEI to trigger an interrupt
14782+ * @mc_io: Pointer to MC portal's I/O object
14783+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14784+ * @token: Token of DPDCEI object
14785+ * @irq_index: Identifies the interrupt index to configure
14786+ * @irq_cfg: IRQ configuration
14787+ *
14788+ * Return: '0' on Success; Error code otherwise.
14789+ */
14790+int dpdcei_set_irq(struct fsl_mc_io *mc_io,
14791+ uint32_t cmd_flags,
14792+ uint16_t token,
14793+ uint8_t irq_index,
14794+ struct dpdcei_irq_cfg *irq_cfg);
14795+
14796+/**
14797+ * dpdcei_get_irq() - Get IRQ information from the DPDCEI
14798+ *
14799+ * @mc_io: Pointer to MC portal's I/O object
14800+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14801+ * @token: Token of DPDCEI object
14802+ * @irq_index: The interrupt index to configure
14803+ * @type: Interrupt type: 0 represents message interrupt
14804+ * type (both irq_addr and irq_val are valid)
14805+ * @irq_cfg: IRQ attributes
14806+ *
14807+ * Return: '0' on Success; Error code otherwise.
14808+ */
14809+int dpdcei_get_irq(struct fsl_mc_io *mc_io,
14810+ uint32_t cmd_flags,
14811+ uint16_t token,
14812+ uint8_t irq_index,
14813+ int *type,
14814+ struct dpdcei_irq_cfg *irq_cfg);
14815+
14816+/**
14817+ * dpdcei_set_irq_enable() - Set overall interrupt state.
14818+ * @mc_io: Pointer to MC portal's I/O object
14819+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14820+ * @token: Token of DPCI object
14821+ * @irq_index: The interrupt index to configure
14822+ * @en: Interrupt state - enable = 1, disable = 0
14823+ *
14824+ * Allows GPP software to control when interrupts are generated.
14825+ * Each interrupt can have up to 32 causes. The enable/disable control's the
14826+ * overall interrupt state. if the interrupt is disabled no causes will cause
14827+ * an interrupt
14828+ *
14829+ * Return: '0' on Success; Error code otherwise.
14830+ */
14831+int dpdcei_set_irq_enable(struct fsl_mc_io *mc_io,
14832+ uint32_t cmd_flags,
14833+ uint16_t token,
14834+ uint8_t irq_index,
14835+ uint8_t en);
14836+
14837+/**
14838+ * dpdcei_get_irq_enable() - Get overall interrupt state
14839+ * @mc_io: Pointer to MC portal's I/O object
14840+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14841+ * @token: Token of DPDCEI object
14842+ * @irq_index: The interrupt index to configure
14843+ * @en: Returned Interrupt state - enable = 1, disable = 0
14844+ *
14845+ * Return: '0' on Success; Error code otherwise.
14846+ */
14847+int dpdcei_get_irq_enable(struct fsl_mc_io *mc_io,
14848+ uint32_t cmd_flags,
14849+ uint16_t token,
14850+ uint8_t irq_index,
14851+ uint8_t *en);
14852+
14853+/**
14854+ * dpdcei_set_irq_mask() - Set interrupt mask.
14855+ * @mc_io: Pointer to MC portal's I/O object
14856+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14857+ * @token: Token of DPCI object
14858+ * @irq_index: The interrupt index to configure
14859+ * @mask: event mask to trigger interrupt;
14860+ * each bit:
14861+ * 0 = ignore event
14862+ * 1 = consider event for asserting IRQ
14863+ *
14864+ * Every interrupt can have up to 32 causes and the interrupt model supports
14865+ * masking/unmasking each cause independently
14866+ *
14867+ * Return: '0' on Success; Error code otherwise.
14868+ */
14869+int dpdcei_set_irq_mask(struct fsl_mc_io *mc_io,
14870+ uint32_t cmd_flags,
14871+ uint16_t token,
14872+ uint8_t irq_index,
14873+ uint32_t mask);
14874+
14875+/**
14876+ * dpdcei_get_irq_mask() - Get interrupt mask.
14877+ * @mc_io: Pointer to MC portal's I/O object
14878+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14879+ * @token: Token of DPDCEI object
14880+ * @irq_index: The interrupt index to configure
14881+ * @mask: Returned event mask to trigger interrupt
14882+ *
14883+ * Every interrupt can have up to 32 causes and the interrupt model supports
14884+ * masking/unmasking each cause independently
14885+ *
14886+ * Return: '0' on Success; Error code otherwise.
14887+ */
14888+int dpdcei_get_irq_mask(struct fsl_mc_io *mc_io,
14889+ uint32_t cmd_flags,
14890+ uint16_t token,
14891+ uint8_t irq_index,
14892+ uint32_t *mask);
14893+
14894+/**
14895+ * dpdcei_get_irq_status() - Get the current status of any pending interrupts
14896+ * @mc_io: Pointer to MC portal's I/O object
14897+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14898+ * @token: Token of DPDCEI object
14899+ * @irq_index: The interrupt index to configure
14900+ * @status: Returned interrupts status - one bit per cause:
14901+ * 0 = no interrupt pending
14902+ * 1 = interrupt pending
14903+ *
14904+ * Return: '0' on Success; Error code otherwise.
14905+ */
14906+int dpdcei_get_irq_status(struct fsl_mc_io *mc_io,
14907+ uint32_t cmd_flags,
14908+ uint16_t token,
14909+ uint8_t irq_index,
14910+ uint32_t *status);
14911+
14912+/**
14913+ * dpdcei_clear_irq_status() - Clear a pending interrupt's status
14914+ * @mc_io: Pointer to MC portal's I/O object
14915+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14916+ * @token: Token of DPDCEI object
14917+ * @irq_index: The interrupt index to configure
14918+ * @status: bits to clear (W1C) - one bit per cause:
14919+ * 0 = don't change
14920+ * 1 = clear status bit
14921+ *
14922+ * Return: '0' on Success; Error code otherwise.
14923+ */
14924+int dpdcei_clear_irq_status(struct fsl_mc_io *mc_io,
14925+ uint32_t cmd_flags,
14926+ uint16_t token,
14927+ uint8_t irq_index,
14928+ uint32_t status);
14929+/**
14930+ * struct dpdcei_attr - Structure representing DPDCEI attributes
14931+ * @id: DPDCEI object ID
14932+ * @engine: DCE engine block
14933+ * @version: DPDCEI version
14934+ */
14935+struct dpdcei_attr {
14936+ int id;
14937+ enum dpdcei_engine engine;
14938+ /**
14939+ * struct version - DPDCEI version
14940+ * @major: DPDCEI major version
14941+ * @minor: DPDCEI minor version
14942+ */
14943+ struct {
14944+ uint16_t major;
14945+ uint16_t minor;
14946+ } version;
14947+};
14948+
14949+/**
14950+ * dpdcei_get_attributes() - Retrieve DPDCEI attributes.
14951+ * @mc_io: Pointer to MC portal's I/O object
14952+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
14953+ * @token: Token of DPDCEI object
14954+ * @attr: Returned object's attributes
14955+ *
14956+ * Return: '0' on Success; Error code otherwise.
14957+ */
14958+int dpdcei_get_attributes(struct fsl_mc_io *mc_io,
14959+ uint32_t cmd_flags,
14960+ uint16_t token,
14961+ struct dpdcei_attr *attr);
14962+
14963+/**
14964+ * enum dpdcei_dest - DPDCEI destination types
14965+ * @DPDCEI_DEST_NONE: Unassigned destination; The queue is set in parked mode
14966+ * and does not generate FQDAN notifications;
14967+ * user is expected to dequeue from the queue based on
14968+ * polling or other user-defined method
14969+ * @DPDCEI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN
14970+ * notifications to the specified DPIO; user is expected to
14971+ * dequeue from the queue only after notification is
14972+ * received
14973+ * @DPDCEI_DEST_DPCON: The queue is set in schedule mode and does not generate
14974+ * FQDAN notifications, but is connected to the specified
14975+ * DPCON object;
14976+ * user is expected to dequeue from the DPCON channel
14977+ */
14978+enum dpdcei_dest {
14979+ DPDCEI_DEST_NONE = 0,
14980+ DPDCEI_DEST_DPIO = 1,
14981+ DPDCEI_DEST_DPCON = 2
14982+};
14983+
14984+/**
14985+ * struct dpdcei_dest_cfg - Structure representing DPDCEI destination parameters
14986+ * @dest_type: Destination type
14987+ * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type
14988+ * @priority: Priority selection within the DPIO or DPCON channel; valid values
14989+ * are 0-1 or 0-7, depending on the number of priorities in that
14990+ * channel; not relevant for 'DPDCEI_DEST_NONE' option
14991+ */
14992+struct dpdcei_dest_cfg {
14993+ enum dpdcei_dest dest_type;
14994+ int dest_id;
14995+ uint8_t priority;
14996+};
14997+
14998+/** DPDCEI queue modification options */
14999+
15000+/**
15001+ * Select to modify the user's context associated with the queue
15002+ */
15003+#define DPDCEI_QUEUE_OPT_USER_CTX 0x00000001
15004+
15005+/**
15006+ * Select to modify the queue's destination
15007+ */
15008+#define DPDCEI_QUEUE_OPT_DEST 0x00000002
15009+
15010+/**
15011+ * struct dpdcei_rx_queue_cfg - RX queue configuration
15012+ * @options: Flags representing the suggested modifications to the queue;
15013+ * Use any combination of 'DPDCEI_QUEUE_OPT_<X>' flags
15014+ * @user_ctx: User context value provided in the frame descriptor of each
15015+ * dequeued frame;
15016+ * valid only if 'DPDCEI_QUEUE_OPT_USER_CTX' is contained in 'options'
15017+ * @dest_cfg: Queue destination parameters;
15018+ * valid only if 'DPDCEI_QUEUE_OPT_DEST' is contained in 'options'
15019+ */
15020+struct dpdcei_rx_queue_cfg {
15021+ uint32_t options;
15022+ uint64_t user_ctx;
15023+ struct dpdcei_dest_cfg dest_cfg;
15024+};
15025+
15026+/**
15027+ * dpdcei_set_rx_queue() - Set Rx queue configuration
15028+ * @mc_io: Pointer to MC portal's I/O object
15029+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15030+ * @token: Token of DPDCEI object
15031+ * @cfg: Rx queue configuration
15032+ *
15033+ * Return: '0' on Success; Error code otherwise.
15034+ */
15035+int dpdcei_set_rx_queue(struct fsl_mc_io *mc_io,
15036+ uint32_t cmd_flags,
15037+ uint16_t token,
15038+ const struct dpdcei_rx_queue_cfg *cfg);
15039+
15040+/**
15041+ * struct dpdcei_rx_queue_attr - Structure representing attributes of Rx queues
15042+ * @user_ctx: User context value provided in the frame descriptor of each
15043+ * dequeued frame
15044+ * @dest_cfg: Queue destination configuration
15045+ * @fqid: Virtual FQID value to be used for dequeue operations
15046+ */
15047+struct dpdcei_rx_queue_attr {
15048+ uint64_t user_ctx;
15049+ struct dpdcei_dest_cfg dest_cfg;
15050+ uint32_t fqid;
15051+};
15052+
15053+/**
15054+ * dpdcei_get_rx_queue() - Retrieve Rx queue attributes.
15055+ * @mc_io: Pointer to MC portal's I/O object
15056+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15057+ * @token: Token of DPDCEI object
15058+ * @attr: Returned Rx queue attributes
15059+ *
15060+ * Return: '0' on Success; Error code otherwise.
15061+ */
15062+int dpdcei_get_rx_queue(struct fsl_mc_io *mc_io,
15063+ uint32_t cmd_flags,
15064+ uint16_t token,
15065+ struct dpdcei_rx_queue_attr *attr);
15066+
15067+/**
15068+ * struct dpdcei_tx_queue_attr - Structure representing attributes of Tx queues
15069+ * @fqid: Virtual FQID to be used for sending frames to DCE hardware
15070+ */
15071+struct dpdcei_tx_queue_attr {
15072+ uint32_t fqid;
15073+};
15074+
15075+/**
15076+ * dpdcei_get_tx_queue() - Retrieve Tx queue attributes.
15077+ * @mc_io: Pointer to MC portal's I/O object
15078+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15079+ * @token: Token of DPDCEI object
15080+ * @attr: Returned Tx queue attributes
15081+ *
15082+ * Return: '0' on Success; Error code otherwise.
15083+ */
15084+int dpdcei_get_tx_queue(struct fsl_mc_io *mc_io,
15085+ uint32_t cmd_flags,
15086+ uint16_t token,
15087+ struct dpdcei_tx_queue_attr *attr);
15088+
15089+#endif /* __FSL_DPDCEI_H */
15090diff --git a/drivers/net/dpaa2/mc/fsl_dpdcei_cmd.h b/drivers/net/dpaa2/mc/fsl_dpdcei_cmd.h
15091new file mode 100644
15092index 0000000..8452d88
15093--- /dev/null
15094+++ b/drivers/net/dpaa2/mc/fsl_dpdcei_cmd.h
15095@@ -0,0 +1,182 @@
15096+/* Copyright 2013-2015 Freescale Semiconductor Inc.
15097+ *
15098+ * Redistribution and use in source and binary forms, with or without
15099+ * modification, are permitted provided that the following conditions are met:
15100+ * * Redistributions of source code must retain the above copyright
15101+ * notice, this list of conditions and the following disclaimer.
15102+ * * Redistributions in binary form must reproduce the above copyright
15103+ * notice, this list of conditions and the following disclaimer in the
15104+ * documentation and/or other materials provided with the distribution.
15105+ * * Neither the name of the above-listed copyright holders nor the
15106+ * names of any contributors may be used to endorse or promote products
15107+ * derived from this software without specific prior written permission.
15108+ *
15109+ *
15110+ * ALTERNATIVELY, this software may be distributed under the terms of the
15111+ * GNU General Public License ("GPL") as published by the Free Software
15112+ * Foundation, either version 2 of that License or (at your option) any
15113+ * later version.
15114+ *
15115+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15116+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15117+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
15118+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
15119+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
15120+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
15121+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
15122+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
15123+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
15124+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
15125+ * POSSIBILITY OF SUCH DAMAGE.
15126+ */
15127+#ifndef _FSL_DPDCEI_CMD_H
15128+#define _FSL_DPDCEI_CMD_H
15129+
15130+/* DPDCEI Version */
15131+#define DPDCEI_VER_MAJOR 1
15132+#define DPDCEI_VER_MINOR 2
15133+
15134+/* Command IDs */
15135+#define DPDCEI_CMDID_CLOSE 0x800
15136+#define DPDCEI_CMDID_OPEN 0x80D
15137+#define DPDCEI_CMDID_CREATE 0x90D
15138+#define DPDCEI_CMDID_DESTROY 0x900
15139+
15140+#define DPDCEI_CMDID_ENABLE 0x002
15141+#define DPDCEI_CMDID_DISABLE 0x003
15142+#define DPDCEI_CMDID_GET_ATTR 0x004
15143+#define DPDCEI_CMDID_RESET 0x005
15144+#define DPDCEI_CMDID_IS_ENABLED 0x006
15145+
15146+#define DPDCEI_CMDID_SET_IRQ 0x010
15147+#define DPDCEI_CMDID_GET_IRQ 0x011
15148+#define DPDCEI_CMDID_SET_IRQ_ENABLE 0x012
15149+#define DPDCEI_CMDID_GET_IRQ_ENABLE 0x013
15150+#define DPDCEI_CMDID_SET_IRQ_MASK 0x014
15151+#define DPDCEI_CMDID_GET_IRQ_MASK 0x015
15152+#define DPDCEI_CMDID_GET_IRQ_STATUS 0x016
15153+#define DPDCEI_CMDID_CLEAR_IRQ_STATUS 0x017
15154+
15155+#define DPDCEI_CMDID_SET_RX_QUEUE 0x1B0
15156+#define DPDCEI_CMDID_GET_RX_QUEUE 0x1B1
15157+#define DPDCEI_CMDID_GET_TX_QUEUE 0x1B2
15158+
15159+/* cmd, param, offset, width, type, arg_name */
15160+#define DPDCEI_CMD_OPEN(cmd, dpdcei_id) \
15161+ MC_CMD_OP(cmd, 0, 0, 32, int, dpdcei_id)
15162+
15163+/* cmd, param, offset, width, type, arg_name */
15164+#define DPDCEI_CMD_CREATE(cmd, cfg) \
15165+do { \
15166+ MC_CMD_OP(cmd, 0, 8, 8, enum dpdcei_engine, cfg->engine);\
15167+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->priority);\
15168+} while (0)
15169+
15170+/* cmd, param, offset, width, type, arg_name */
15171+#define DPDCEI_RSP_IS_ENABLED(cmd, en) \
15172+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
15173+
15174+/* cmd, param, offset, width, type, arg_name */
15175+#define DPDCEI_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
15176+do { \
15177+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
15178+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
15179+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
15180+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
15181+} while (0)
15182+
15183+/* cmd, param, offset, width, type, arg_name */
15184+#define DPDCEI_CMD_GET_IRQ(cmd, irq_index) \
15185+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
15186+
15187+/* cmd, param, offset, width, type, arg_name */
15188+#define DPDCEI_RSP_GET_IRQ(cmd, type, irq_cfg) \
15189+do { \
15190+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
15191+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
15192+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
15193+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
15194+} while (0)
15195+
15196+/* cmd, param, offset, width, type, arg_name */
15197+#define DPDCEI_CMD_SET_IRQ_ENABLE(cmd, irq_index, enable_state) \
15198+do { \
15199+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, enable_state); \
15200+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
15201+} while (0)
15202+
15203+/* cmd, param, offset, width, type, arg_name */
15204+#define DPDCEI_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
15205+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
15206+
15207+/* cmd, param, offset, width, type, arg_name */
15208+#define DPDCEI_RSP_GET_IRQ_ENABLE(cmd, enable_state) \
15209+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, enable_state)
15210+
15211+/* cmd, param, offset, width, type, arg_name */
15212+#define DPDCEI_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
15213+do { \
15214+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
15215+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
15216+} while (0)
15217+
15218+/* cmd, param, offset, width, type, arg_name */
15219+#define DPDCEI_CMD_GET_IRQ_MASK(cmd, irq_index) \
15220+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
15221+
15222+/* cmd, param, offset, width, type, arg_name */
15223+#define DPDCEI_RSP_GET_IRQ_MASK(cmd, mask) \
15224+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
15225+
15226+/* cmd, param, offset, width, type, arg_name */
15227+#define DPDCEI_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
15228+do { \
15229+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
15230+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
15231+} while (0)
15232+
15233+/* cmd, param, offset, width, type, arg_name */
15234+#define DPDCEI_RSP_GET_IRQ_STATUS(cmd, status) \
15235+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
15236+
15237+/* cmd, param, offset, width, type, arg_name */
15238+#define DPDCEI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
15239+do { \
15240+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
15241+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
15242+} while (0)
15243+
15244+/* cmd, param, offset, width, type, arg_name */
15245+#define DPDCEI_RSP_GET_ATTR(cmd, attr) \
15246+do { \
15247+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id); \
15248+ MC_RSP_OP(cmd, 0, 32, 8, enum dpdcei_engine, attr->engine); \
15249+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
15250+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
15251+} while (0)
15252+
15253+/* cmd, param, offset, width, type, arg_name */
15254+#define DPDCEI_CMD_SET_RX_QUEUE(cmd, cfg) \
15255+do { \
15256+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \
15257+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority); \
15258+ MC_CMD_OP(cmd, 0, 48, 4, enum dpdcei_dest, cfg->dest_cfg.dest_type); \
15259+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \
15260+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
15261+} while (0)
15262+
15263+/* cmd, param, offset, width, type, arg_name */
15264+#define DPDCEI_RSP_GET_RX_QUEUE(cmd, attr) \
15265+do { \
15266+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id);\
15267+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
15268+ MC_RSP_OP(cmd, 0, 48, 4, enum dpdcei_dest, attr->dest_cfg.dest_type);\
15269+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx);\
15270+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->fqid);\
15271+} while (0)
15272+
15273+/* cmd, param, offset, width, type, arg_name */
15274+#define DPDCEI_RSP_GET_TX_QUEUE(cmd, attr) \
15275+ MC_RSP_OP(cmd, 0, 32, 32, uint32_t, attr->fqid)
15276+
15277+#endif /* _FSL_DPDCEI_CMD_H */
15278diff --git a/drivers/net/dpaa2/mc/fsl_dpdmai.h b/drivers/net/dpaa2/mc/fsl_dpdmai.h
15279new file mode 100644
15280index 0000000..e931ce1
15281--- /dev/null
15282+++ b/drivers/net/dpaa2/mc/fsl_dpdmai.h
15283@@ -0,0 +1,521 @@
15284+/* Copyright 2013-2015 Freescale Semiconductor Inc.
15285+ *
15286+ * Redistribution and use in source and binary forms, with or without
15287+ * modification, are permitted provided that the following conditions are met:
15288+ * * Redistributions of source code must retain the above copyright
15289+ * notice, this list of conditions and the following disclaimer.
15290+ * * Redistributions in binary form must reproduce the above copyright
15291+ * notice, this list of conditions and the following disclaimer in the
15292+ * documentation and/or other materials provided with the distribution.
15293+ * * Neither the name of the above-listed copyright holders nor the
15294+ * names of any contributors may be used to endorse or promote products
15295+ * derived from this software without specific prior written permission.
15296+ *
15297+ *
15298+ * ALTERNATIVELY, this software may be distributed under the terms of the
15299+ * GNU General Public License ("GPL") as published by the Free Software
15300+ * Foundation, either version 2 of that License or (at your option) any
15301+ * later version.
15302+ *
15303+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15304+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15305+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
15306+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
15307+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
15308+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
15309+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
15310+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
15311+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
15312+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
15313+ * POSSIBILITY OF SUCH DAMAGE.
15314+ */
15315+#ifndef __FSL_DPDMAI_H
15316+#define __FSL_DPDMAI_H
15317+
15318+struct fsl_mc_io;
15319+
15320+/* Data Path DMA Interface API
15321+ * Contains initialization APIs and runtime control APIs for DPDMAI
15322+ */
15323+
15324+/* General DPDMAI macros */
15325+
15326+/**
15327+ * Maximum number of Tx/Rx priorities per DPDMAI object
15328+ */
15329+#define DPDMAI_PRIO_NUM 2
15330+
15331+/**
15332+ * All queues considered; see dpdmai_set_rx_queue()
15333+ */
15334+#define DPDMAI_ALL_QUEUES (uint8_t)(-1)
15335+
15336+/**
15337+ * dpdmai_open() - Open a control session for the specified object
15338+ * @mc_io: Pointer to MC portal's I/O object
15339+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15340+ * @dpdmai_id: DPDMAI unique ID
15341+ * @token: Returned token; use in subsequent API calls
15342+ *
15343+ * This function can be used to open a control session for an
15344+ * already created object; an object may have been declared in
15345+ * the DPL or by calling the dpdmai_create() function.
15346+ * This function returns a unique authentication token,
15347+ * associated with the specific object ID and the specific MC
15348+ * portal; this token must be used in all subsequent commands for
15349+ * this specific object.
15350+ *
15351+ * Return: '0' on Success; Error code otherwise.
15352+ */
15353+int dpdmai_open(struct fsl_mc_io *mc_io,
15354+ uint32_t cmd_flags,
15355+ int dpdmai_id,
15356+ uint16_t *token);
15357+
15358+/**
15359+ * dpdmai_close() - Close the control session of the object
15360+ * @mc_io: Pointer to MC portal's I/O object
15361+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15362+ * @token: Token of DPDMAI object
15363+ *
15364+ * After this function is called, no further operations are
15365+ * allowed on the object without opening a new control session.
15366+ *
15367+ * Return: '0' on Success; Error code otherwise.
15368+ */
15369+int dpdmai_close(struct fsl_mc_io *mc_io,
15370+ uint32_t cmd_flags,
15371+ uint16_t token);
15372+
15373+/**
15374+ * struct dpdmai_cfg - Structure representing DPDMAI configuration
15375+ * @priorities: Priorities for the DMA hardware processing; valid priorities are
15376+ * configured with values 1-8; the entry following last valid entry
15377+ * should be configured with 0
15378+ */
15379+struct dpdmai_cfg {
15380+ uint8_t priorities[DPDMAI_PRIO_NUM];
15381+};
15382+
15383+/**
15384+ * dpdmai_create() - Create the DPDMAI object
15385+ * @mc_io: Pointer to MC portal's I/O object
15386+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15387+ * @cfg: Configuration structure
15388+ * @token: Returned token; use in subsequent API calls
15389+ *
15390+ * Create the DPDMAI object, allocate required resources and
15391+ * perform required initialization.
15392+ *
15393+ * The object can be created either by declaring it in the
15394+ * DPL file, or by calling this function.
15395+ *
15396+ * This function returns a unique authentication token,
15397+ * associated with the specific object ID and the specific MC
15398+ * portal; this token must be used in all subsequent calls to
15399+ * this specific object. For objects that are created using the
15400+ * DPL file, call dpdmai_open() function to get an authentication
15401+ * token first.
15402+ *
15403+ * Return: '0' on Success; Error code otherwise.
15404+ */
15405+int dpdmai_create(struct fsl_mc_io *mc_io,
15406+ uint32_t cmd_flags,
15407+ const struct dpdmai_cfg *cfg,
15408+ uint16_t *token);
15409+
15410+/**
15411+ * dpdmai_destroy() - Destroy the DPDMAI object and release all its resources.
15412+ * @mc_io: Pointer to MC portal's I/O object
15413+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15414+ * @token: Token of DPDMAI object
15415+ *
15416+ * Return: '0' on Success; error code otherwise.
15417+ */
15418+int dpdmai_destroy(struct fsl_mc_io *mc_io,
15419+ uint32_t cmd_flags,
15420+ uint16_t token);
15421+
15422+/**
15423+ * dpdmai_enable() - Enable the DPDMAI, allow sending and receiving frames.
15424+ * @mc_io: Pointer to MC portal's I/O object
15425+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15426+ * @token: Token of DPDMAI object
15427+ *
15428+ * Return: '0' on Success; Error code otherwise.
15429+ */
15430+int dpdmai_enable(struct fsl_mc_io *mc_io,
15431+ uint32_t cmd_flags,
15432+ uint16_t token);
15433+
15434+/**
15435+ * dpdmai_disable() - Disable the DPDMAI, stop sending and receiving frames.
15436+ * @mc_io: Pointer to MC portal's I/O object
15437+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15438+ * @token: Token of DPDMAI object
15439+ *
15440+ * Return: '0' on Success; Error code otherwise.
15441+ */
15442+int dpdmai_disable(struct fsl_mc_io *mc_io,
15443+ uint32_t cmd_flags,
15444+ uint16_t token);
15445+
15446+/**
15447+ * dpdmai_is_enabled() - Check if the DPDMAI is enabled.
15448+ * @mc_io: Pointer to MC portal's I/O object
15449+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15450+ * @token: Token of DPDMAI object
15451+ * @en: Returns '1' if object is enabled; '0' otherwise
15452+ *
15453+ * Return: '0' on Success; Error code otherwise.
15454+ */
15455+int dpdmai_is_enabled(struct fsl_mc_io *mc_io,
15456+ uint32_t cmd_flags,
15457+ uint16_t token,
15458+ int *en);
15459+
15460+/**
15461+ * dpdmai_reset() - Reset the DPDMAI, returns the object to initial state.
15462+ * @mc_io: Pointer to MC portal's I/O object
15463+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15464+ * @token: Token of DPDMAI object
15465+ *
15466+ * Return: '0' on Success; Error code otherwise.
15467+ */
15468+int dpdmai_reset(struct fsl_mc_io *mc_io,
15469+ uint32_t cmd_flags,
15470+ uint16_t token);
15471+
15472+/**
15473+ * struct dpdmai_irq_cfg - IRQ configuration
15474+ * @addr: Address that must be written to signal a message-based interrupt
15475+ * @val: Value to write into irq_addr address
15476+ * @irq_num: A user defined number associated with this IRQ
15477+ */
15478+struct dpdmai_irq_cfg {
15479+ uint64_t addr;
15480+ uint32_t val;
15481+ int irq_num;
15482+};
15483+
15484+/**
15485+ * dpdmai_set_irq() - Set IRQ information for the DPDMAI to trigger an interrupt.
15486+ * @mc_io: Pointer to MC portal's I/O object
15487+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15488+ * @token: Token of DPDMAI object
15489+ * @irq_index: Identifies the interrupt index to configure
15490+ * @irq_cfg: IRQ configuration
15491+ *
15492+ * Return: '0' on Success; Error code otherwise.
15493+ */
15494+int dpdmai_set_irq(struct fsl_mc_io *mc_io,
15495+ uint32_t cmd_flags,
15496+ uint16_t token,
15497+ uint8_t irq_index,
15498+ struct dpdmai_irq_cfg *irq_cfg);
15499+
15500+/**
15501+ * dpdmai_get_irq() - Get IRQ information from the DPDMAI
15502+ *
15503+ * @mc_io: Pointer to MC portal's I/O object
15504+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15505+ * @token: Token of DPDMAI object
15506+ * @irq_index: The interrupt index to configure
15507+ * @type: Interrupt type: 0 represents message interrupt
15508+ * type (both irq_addr and irq_val are valid)
15509+ * @irq_cfg: IRQ attributes
15510+ *
15511+ * Return: '0' on Success; Error code otherwise.
15512+ */
15513+int dpdmai_get_irq(struct fsl_mc_io *mc_io,
15514+ uint32_t cmd_flags,
15515+ uint16_t token,
15516+ uint8_t irq_index,
15517+ int *type,
15518+ struct dpdmai_irq_cfg *irq_cfg);
15519+
15520+/**
15521+ * dpdmai_set_irq_enable() - Set overall interrupt state.
15522+ * @mc_io: Pointer to MC portal's I/O object
15523+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15524+ * @token: Token of DPDMAI object
15525+ * @irq_index: The interrupt index to configure
15526+ * @en: Interrupt state - enable = 1, disable = 0
15527+ *
15528+ * Allows GPP software to control when interrupts are generated.
15529+ * Each interrupt can have up to 32 causes. The enable/disable control's the
15530+ * overall interrupt state. if the interrupt is disabled no causes will cause
15531+ * an interrupt
15532+ *
15533+ * Return: '0' on Success; Error code otherwise.
15534+ */
15535+int dpdmai_set_irq_enable(struct fsl_mc_io *mc_io,
15536+ uint32_t cmd_flags,
15537+ uint16_t token,
15538+ uint8_t irq_index,
15539+ uint8_t en);
15540+
15541+/**
15542+ * dpdmai_get_irq_enable() - Get overall interrupt state
15543+ * @mc_io: Pointer to MC portal's I/O object
15544+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15545+ * @token: Token of DPDMAI object
15546+ * @irq_index: The interrupt index to configure
15547+ * @en: Returned Interrupt state - enable = 1, disable = 0
15548+ *
15549+ * Return: '0' on Success; Error code otherwise.
15550+ */
15551+int dpdmai_get_irq_enable(struct fsl_mc_io *mc_io,
15552+ uint32_t cmd_flags,
15553+ uint16_t token,
15554+ uint8_t irq_index,
15555+ uint8_t *en);
15556+
15557+/**
15558+ * dpdmai_set_irq_mask() - Set interrupt mask.
15559+ * @mc_io: Pointer to MC portal's I/O object
15560+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15561+ * @token: Token of DPDMAI object
15562+ * @irq_index: The interrupt index to configure
15563+ * @mask: event mask to trigger interrupt;
15564+ * each bit:
15565+ * 0 = ignore event
15566+ * 1 = consider event for asserting IRQ
15567+ *
15568+ * Every interrupt can have up to 32 causes and the interrupt model supports
15569+ * masking/unmasking each cause independently
15570+ *
15571+ * Return: '0' on Success; Error code otherwise.
15572+ */
15573+int dpdmai_set_irq_mask(struct fsl_mc_io *mc_io,
15574+ uint32_t cmd_flags,
15575+ uint16_t token,
15576+ uint8_t irq_index,
15577+ uint32_t mask);
15578+
15579+/**
15580+ * dpdmai_get_irq_mask() - Get interrupt mask.
15581+ * @mc_io: Pointer to MC portal's I/O object
15582+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15583+ * @token: Token of DPDMAI object
15584+ * @irq_index: The interrupt index to configure
15585+ * @mask: Returned event mask to trigger interrupt
15586+ *
15587+ * Every interrupt can have up to 32 causes and the interrupt model supports
15588+ * masking/unmasking each cause independently
15589+ *
15590+ * Return: '0' on Success; Error code otherwise.
15591+ */
15592+int dpdmai_get_irq_mask(struct fsl_mc_io *mc_io,
15593+ uint32_t cmd_flags,
15594+ uint16_t token,
15595+ uint8_t irq_index,
15596+ uint32_t *mask);
15597+
15598+/**
15599+ * dpdmai_get_irq_status() - Get the current status of any pending interrupts
15600+ * @mc_io: Pointer to MC portal's I/O object
15601+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15602+ * @token: Token of DPDMAI object
15603+ * @irq_index: The interrupt index to configure
15604+ * @status: Returned interrupts status - one bit per cause:
15605+ * 0 = no interrupt pending
15606+ * 1 = interrupt pending
15607+ *
15608+ * Return: '0' on Success; Error code otherwise.
15609+ */
15610+int dpdmai_get_irq_status(struct fsl_mc_io *mc_io,
15611+ uint32_t cmd_flags,
15612+ uint16_t token,
15613+ uint8_t irq_index,
15614+ uint32_t *status);
15615+
15616+/**
15617+ * dpdmai_clear_irq_status() - Clear a pending interrupt's status
15618+ * @mc_io: Pointer to MC portal's I/O object
15619+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15620+ * @token: Token of DPDMAI object
15621+ * @irq_index: The interrupt index to configure
15622+ * @status: bits to clear (W1C) - one bit per cause:
15623+ * 0 = don't change
15624+ * 1 = clear status bit
15625+ *
15626+ * Return: '0' on Success; Error code otherwise.
15627+ */
15628+int dpdmai_clear_irq_status(struct fsl_mc_io *mc_io,
15629+ uint32_t cmd_flags,
15630+ uint16_t token,
15631+ uint8_t irq_index,
15632+ uint32_t status);
15633+
15634+/**
15635+ * struct dpdmai_attr - Structure representing DPDMAI attributes
15636+ * @id: DPDMAI object ID
15637+ * @version: DPDMAI version
15638+ * @num_of_priorities: number of priorities
15639+ */
15640+struct dpdmai_attr {
15641+ int id;
15642+ /**
15643+ * struct version - DPDMAI version
15644+ * @major: DPDMAI major version
15645+ * @minor: DPDMAI minor version
15646+ */
15647+ struct {
15648+ uint16_t major;
15649+ uint16_t minor;
15650+ } version;
15651+ uint8_t num_of_priorities;
15652+};
15653+
15654+/**
15655+ * dpdmai_get_attributes() - Retrieve DPDMAI attributes.
15656+ * @mc_io: Pointer to MC portal's I/O object
15657+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15658+ * @token: Token of DPDMAI object
15659+ * @attr: Returned object's attributes
15660+ *
15661+ * Return: '0' on Success; Error code otherwise.
15662+ */
15663+int dpdmai_get_attributes(struct fsl_mc_io *mc_io,
15664+ uint32_t cmd_flags,
15665+ uint16_t token,
15666+ struct dpdmai_attr *attr);
15667+
15668+/**
15669+ * enum dpdmai_dest - DPDMAI destination types
15670+ * @DPDMAI_DEST_NONE: Unassigned destination; The queue is set in parked mode
15671+ * and does not generate FQDAN notifications; user is expected to dequeue
15672+ * from the queue based on polling or other user-defined method
15673+ * @DPDMAI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN
15674+ * notifications to the specified DPIO; user is expected to dequeue
15675+ * from the queue only after notification is received
15676+ * @DPDMAI_DEST_DPCON: The queue is set in schedule mode and does not generate
15677+ * FQDAN notifications, but is connected to the specified DPCON object;
15678+ * user is expected to dequeue from the DPCON channel
15679+ */
15680+enum dpdmai_dest {
15681+ DPDMAI_DEST_NONE = 0,
15682+ DPDMAI_DEST_DPIO = 1,
15683+ DPDMAI_DEST_DPCON = 2
15684+};
15685+
15686+/**
15687+ * struct dpdmai_dest_cfg - Structure representing DPDMAI destination parameters
15688+ * @dest_type: Destination type
15689+ * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type
15690+ * @priority: Priority selection within the DPIO or DPCON channel; valid values
15691+ * are 0-1 or 0-7, depending on the number of priorities in that
15692+ * channel; not relevant for 'DPDMAI_DEST_NONE' option
15693+ */
15694+struct dpdmai_dest_cfg {
15695+ enum dpdmai_dest dest_type;
15696+ int dest_id;
15697+ uint8_t priority;
15698+};
15699+
15700+/* DPDMAI queue modification options */
15701+
15702+/**
15703+ * Select to modify the user's context associated with the queue
15704+ */
15705+#define DPDMAI_QUEUE_OPT_USER_CTX 0x00000001
15706+
15707+/**
15708+ * Select to modify the queue's destination
15709+ */
15710+#define DPDMAI_QUEUE_OPT_DEST 0x00000002
15711+
15712+/**
15713+ * struct dpdmai_rx_queue_cfg - DPDMAI RX queue configuration
15714+ * @options: Flags representing the suggested modifications to the queue;
15715+ * Use any combination of 'DPDMAI_QUEUE_OPT_<X>' flags
15716+ * @user_ctx: User context value provided in the frame descriptor of each
15717+ * dequeued frame;
15718+ * valid only if 'DPDMAI_QUEUE_OPT_USER_CTX' is contained in 'options'
15719+ * @dest_cfg: Queue destination parameters;
15720+ * valid only if 'DPDMAI_QUEUE_OPT_DEST' is contained in 'options'
15721+ */
15722+struct dpdmai_rx_queue_cfg {
15723+ uint32_t options;
15724+ uint64_t user_ctx;
15725+ struct dpdmai_dest_cfg dest_cfg;
15726+
15727+};
15728+
15729+/**
15730+ * dpdmai_set_rx_queue() - Set Rx queue configuration
15731+ * @mc_io: Pointer to MC portal's I/O object
15732+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15733+ * @token: Token of DPDMAI object
15734+ * @priority: Select the queue relative to number of
15735+ * priorities configured at DPDMAI creation; use
15736+ * DPDMAI_ALL_QUEUES to configure all Rx queues
15737+ * identically.
15738+ * @cfg: Rx queue configuration
15739+ *
15740+ * Return: '0' on Success; Error code otherwise.
15741+ */
15742+int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io,
15743+ uint32_t cmd_flags,
15744+ uint16_t token,
15745+ uint8_t priority,
15746+ const struct dpdmai_rx_queue_cfg *cfg);
15747+
15748+/**
15749+ * struct dpdmai_rx_queue_attr - Structure representing attributes of Rx queues
15750+ * @user_ctx: User context value provided in the frame descriptor of each
15751+ * dequeued frame
15752+ * @dest_cfg: Queue destination configuration
15753+ * @fqid: Virtual FQID value to be used for dequeue operations
15754+ */
15755+struct dpdmai_rx_queue_attr {
15756+ uint64_t user_ctx;
15757+ struct dpdmai_dest_cfg dest_cfg;
15758+ uint32_t fqid;
15759+};
15760+
15761+/**
15762+ * dpdmai_get_rx_queue() - Retrieve Rx queue attributes.
15763+ * @mc_io: Pointer to MC portal's I/O object
15764+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15765+ * @token: Token of DPDMAI object
15766+ * @priority: Select the queue relative to number of
15767+ * priorities configured at DPDMAI creation
15768+ * @attr: Returned Rx queue attributes
15769+ *
15770+ * Return: '0' on Success; Error code otherwise.
15771+ */
15772+int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io,
15773+ uint32_t cmd_flags,
15774+ uint16_t token,
15775+ uint8_t priority,
15776+ struct dpdmai_rx_queue_attr *attr);
15777+
15778+/**
15779+ * struct dpdmai_tx_queue_attr - Structure representing attributes of Tx queues
15780+ * @fqid: Virtual FQID to be used for sending frames to DMA hardware
15781+ */
15782+
15783+struct dpdmai_tx_queue_attr {
15784+ uint32_t fqid;
15785+};
15786+
15787+/**
15788+ * dpdmai_get_tx_queue() - Retrieve Tx queue attributes.
15789+ * @mc_io: Pointer to MC portal's I/O object
15790+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
15791+ * @token: Token of DPDMAI object
15792+ * @priority: Select the queue relative to number of
15793+ * priorities configured at DPDMAI creation
15794+ * @attr: Returned Tx queue attributes
15795+ *
15796+ * Return: '0' on Success; Error code otherwise.
15797+ */
15798+int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io,
15799+ uint32_t cmd_flags,
15800+ uint16_t token,
15801+ uint8_t priority,
15802+ struct dpdmai_tx_queue_attr *attr);
15803+
15804+#endif /* __FSL_DPDMAI_H */
15805diff --git a/drivers/net/dpaa2/mc/fsl_dpdmai_cmd.h b/drivers/net/dpaa2/mc/fsl_dpdmai_cmd.h
15806new file mode 100644
15807index 0000000..7c4a31a
15808--- /dev/null
15809+++ b/drivers/net/dpaa2/mc/fsl_dpdmai_cmd.h
15810@@ -0,0 +1,191 @@
15811+/* Copyright 2013-2015 Freescale Semiconductor Inc.
15812+ *
15813+ * Redistribution and use in source and binary forms, with or without
15814+ * modification, are permitted provided that the following conditions are met:
15815+ * * Redistributions of source code must retain the above copyright
15816+ * notice, this list of conditions and the following disclaimer.
15817+ * * Redistributions in binary form must reproduce the above copyright
15818+ * notice, this list of conditions and the following disclaimer in the
15819+ * documentation and/or other materials provided with the distribution.
15820+ * * Neither the name of the above-listed copyright holders nor the
15821+ * names of any contributors may be used to endorse or promote products
15822+ * derived from this software without specific prior written permission.
15823+ *
15824+ *
15825+ * ALTERNATIVELY, this software may be distributed under the terms of the
15826+ * GNU General Public License ("GPL") as published by the Free Software
15827+ * Foundation, either version 2 of that License or (at your option) any
15828+ * later version.
15829+ *
15830+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15831+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15832+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
15833+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
15834+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
15835+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
15836+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
15837+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
15838+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
15839+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
15840+ * POSSIBILITY OF SUCH DAMAGE.
15841+ */
15842+#ifndef _FSL_DPDMAI_CMD_H
15843+#define _FSL_DPDMAI_CMD_H
15844+
15845+/* DPDMAI Version */
15846+#define DPDMAI_VER_MAJOR 2
15847+#define DPDMAI_VER_MINOR 2
15848+
15849+/* Command IDs */
15850+#define DPDMAI_CMDID_CLOSE 0x800
15851+#define DPDMAI_CMDID_OPEN 0x80E
15852+#define DPDMAI_CMDID_CREATE 0x90E
15853+#define DPDMAI_CMDID_DESTROY 0x900
15854+
15855+#define DPDMAI_CMDID_ENABLE 0x002
15856+#define DPDMAI_CMDID_DISABLE 0x003
15857+#define DPDMAI_CMDID_GET_ATTR 0x004
15858+#define DPDMAI_CMDID_RESET 0x005
15859+#define DPDMAI_CMDID_IS_ENABLED 0x006
15860+
15861+#define DPDMAI_CMDID_SET_IRQ 0x010
15862+#define DPDMAI_CMDID_GET_IRQ 0x011
15863+#define DPDMAI_CMDID_SET_IRQ_ENABLE 0x012
15864+#define DPDMAI_CMDID_GET_IRQ_ENABLE 0x013
15865+#define DPDMAI_CMDID_SET_IRQ_MASK 0x014
15866+#define DPDMAI_CMDID_GET_IRQ_MASK 0x015
15867+#define DPDMAI_CMDID_GET_IRQ_STATUS 0x016
15868+#define DPDMAI_CMDID_CLEAR_IRQ_STATUS 0x017
15869+
15870+#define DPDMAI_CMDID_SET_RX_QUEUE 0x1A0
15871+#define DPDMAI_CMDID_GET_RX_QUEUE 0x1A1
15872+#define DPDMAI_CMDID_GET_TX_QUEUE 0x1A2
15873+
15874+/* cmd, param, offset, width, type, arg_name */
15875+#define DPDMAI_CMD_OPEN(cmd, dpdmai_id) \
15876+ MC_CMD_OP(cmd, 0, 0, 32, int, dpdmai_id)
15877+
15878+/* cmd, param, offset, width, type, arg_name */
15879+#define DPDMAI_CMD_CREATE(cmd, cfg) \
15880+do { \
15881+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->priorities[0]);\
15882+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->priorities[1]);\
15883+} while (0)
15884+
15885+/* cmd, param, offset, width, type, arg_name */
15886+#define DPDMAI_RSP_IS_ENABLED(cmd, en) \
15887+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
15888+
15889+/* cmd, param, offset, width, type, arg_name */
15890+#define DPDMAI_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
15891+do { \
15892+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
15893+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
15894+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
15895+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
15896+} while (0)
15897+
15898+/* cmd, param, offset, width, type, arg_name */
15899+#define DPDMAI_CMD_GET_IRQ(cmd, irq_index) \
15900+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
15901+
15902+/* cmd, param, offset, width, type, arg_name */
15903+#define DPDMAI_RSP_GET_IRQ(cmd, type, irq_cfg) \
15904+do { \
15905+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
15906+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
15907+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
15908+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
15909+} while (0)
15910+
15911+/* cmd, param, offset, width, type, arg_name */
15912+#define DPDMAI_CMD_SET_IRQ_ENABLE(cmd, irq_index, enable_state) \
15913+do { \
15914+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, enable_state); \
15915+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
15916+} while (0)
15917+
15918+/* cmd, param, offset, width, type, arg_name */
15919+#define DPDMAI_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
15920+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
15921+
15922+/* cmd, param, offset, width, type, arg_name */
15923+#define DPDMAI_RSP_GET_IRQ_ENABLE(cmd, enable_state) \
15924+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, enable_state)
15925+
15926+/* cmd, param, offset, width, type, arg_name */
15927+#define DPDMAI_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
15928+do { \
15929+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
15930+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
15931+} while (0)
15932+
15933+/* cmd, param, offset, width, type, arg_name */
15934+#define DPDMAI_CMD_GET_IRQ_MASK(cmd, irq_index) \
15935+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
15936+
15937+/* cmd, param, offset, width, type, arg_name */
15938+#define DPDMAI_RSP_GET_IRQ_MASK(cmd, mask) \
15939+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
15940+
15941+/* cmd, param, offset, width, type, arg_name */
15942+#define DPDMAI_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
15943+do { \
15944+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
15945+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
15946+} while (0)
15947+
15948+/* cmd, param, offset, width, type, arg_name */
15949+#define DPDMAI_RSP_GET_IRQ_STATUS(cmd, status) \
15950+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
15951+
15952+/* cmd, param, offset, width, type, arg_name */
15953+#define DPDMAI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
15954+do { \
15955+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
15956+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
15957+} while (0)
15958+
15959+/* cmd, param, offset, width, type, arg_name */
15960+#define DPDMAI_RSP_GET_ATTR(cmd, attr) \
15961+do { \
15962+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id); \
15963+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->num_of_priorities); \
15964+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
15965+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
15966+} while (0)
15967+
15968+/* cmd, param, offset, width, type, arg_name */
15969+#define DPDMAI_CMD_SET_RX_QUEUE(cmd, priority, cfg) \
15970+do { \
15971+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \
15972+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority); \
15973+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, priority); \
15974+ MC_CMD_OP(cmd, 0, 48, 4, enum dpdmai_dest, cfg->dest_cfg.dest_type); \
15975+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \
15976+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
15977+} while (0)
15978+
15979+/* cmd, param, offset, width, type, arg_name */
15980+#define DPDMAI_CMD_GET_RX_QUEUE(cmd, priority) \
15981+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, priority)
15982+
15983+/* cmd, param, offset, width, type, arg_name */
15984+#define DPDMAI_RSP_GET_RX_QUEUE(cmd, attr) \
15985+do { \
15986+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id);\
15987+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
15988+ MC_RSP_OP(cmd, 0, 48, 4, enum dpdmai_dest, attr->dest_cfg.dest_type);\
15989+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx);\
15990+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->fqid);\
15991+} while (0)
15992+
15993+/* cmd, param, offset, width, type, arg_name */
15994+#define DPDMAI_CMD_GET_TX_QUEUE(cmd, priority) \
15995+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, priority)
15996+
15997+/* cmd, param, offset, width, type, arg_name */
15998+#define DPDMAI_RSP_GET_TX_QUEUE(cmd, attr) \
15999+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->fqid)
16000+
16001+#endif /* _FSL_DPDMAI_CMD_H */
16002diff --git a/drivers/net/dpaa2/mc/fsl_dpdmux.h b/drivers/net/dpaa2/mc/fsl_dpdmux.h
16003new file mode 100644
16004index 0000000..455a042
16005--- /dev/null
16006+++ b/drivers/net/dpaa2/mc/fsl_dpdmux.h
16007@@ -0,0 +1,724 @@
16008+/* Copyright 2013-2015 Freescale Semiconductor Inc.
16009+ *
16010+ * Redistribution and use in source and binary forms, with or without
16011+ * modification, are permitted provided that the following conditions are met:
16012+ * * Redistributions of source code must retain the above copyright
16013+ * notice, this list of conditions and the following disclaimer.
16014+ * * Redistributions in binary form must reproduce the above copyright
16015+ * notice, this list of conditions and the following disclaimer in the
16016+ * documentation and/or other materials provided with the distribution.
16017+ * * Neither the name of the above-listed copyright holders nor the
16018+ * names of any contributors may be used to endorse or promote products
16019+ * derived from this software without specific prior written permission.
16020+ *
16021+ *
16022+ * ALTERNATIVELY, this software may be distributed under the terms of the
16023+ * GNU General Public License ("GPL") as published by the Free Software
16024+ * Foundation, either version 2 of that License or (at your option) any
16025+ * later version.
16026+ *
16027+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16028+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16029+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16030+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
16031+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
16032+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
16033+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
16034+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
16035+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
16036+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
16037+ * POSSIBILITY OF SUCH DAMAGE.
16038+ */
16039+#ifndef __FSL_DPDMUX_H
16040+#define __FSL_DPDMUX_H
16041+
16042+#include <fsl_net.h>
16043+
16044+struct fsl_mc_io;
16045+
16046+/* Data Path Demux API
16047+ * Contains API for handling DPDMUX topology and functionality
16048+ */
16049+
16050+/**
16051+ * dpdmux_open() - Open a control session for the specified object
16052+ * @mc_io: Pointer to MC portal's I/O object
16053+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16054+ * @dpdmux_id: DPDMUX unique ID
16055+ * @token: Returned token; use in subsequent API calls
16056+ *
16057+ * This function can be used to open a control session for an
16058+ * already created object; an object may have been declared in
16059+ * the DPL or by calling the dpdmux_create() function.
16060+ * This function returns a unique authentication token,
16061+ * associated with the specific object ID and the specific MC
16062+ * portal; this token must be used in all subsequent commands for
16063+ * this specific object.
16064+ *
16065+ * Return: '0' on Success; Error code otherwise.
16066+ */
16067+int dpdmux_open(struct fsl_mc_io *mc_io,
16068+ uint32_t cmd_flags,
16069+ int dpdmux_id,
16070+ uint16_t *token);
16071+
16072+/**
16073+ * dpdmux_close() - Close the control session of the object
16074+ * @mc_io: Pointer to MC portal's I/O object
16075+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16076+ * @token: Token of DPDMUX object
16077+ *
16078+ * After this function is called, no further operations are
16079+ * allowed on the object without opening a new control session.
16080+ *
16081+ * Return: '0' on Success; Error code otherwise.
16082+ */
16083+int dpdmux_close(struct fsl_mc_io *mc_io,
16084+ uint32_t cmd_flags,
16085+ uint16_t token);
16086+
16087+/**
16088+ * DPDMUX general options
16089+ */
16090+
16091+/**
16092+ * Enable bridging between internal interfaces
16093+ */
16094+#define DPDMUX_OPT_BRIDGE_EN 0x0000000000000002ULL
16095+
16096+#define DPDMUX_IRQ_INDEX_IF 0x0000
16097+#define DPDMUX_IRQ_INDEX 0x0001
16098+
16099+/**
16100+ * IRQ event - Indicates that the link state changed
16101+ */
16102+#define DPDMUX_IRQ_EVENT_LINK_CHANGED 0x0001
16103+
16104+/**
16105+ * enum dpdmux_manip - DPDMUX manipulation operations
16106+ * @DPDMUX_MANIP_NONE: No manipulation on frames
16107+ * @DPDMUX_MANIP_ADD_REMOVE_S_VLAN: Add S-VLAN on egress, remove it on ingress
16108+ */
16109+enum dpdmux_manip {
16110+ DPDMUX_MANIP_NONE = 0x0,
16111+ DPDMUX_MANIP_ADD_REMOVE_S_VLAN = 0x1
16112+};
16113+
16114+/**
16115+ * enum dpdmux_method - DPDMUX method options
16116+ * @DPDMUX_METHOD_NONE: no DPDMUX method
16117+ * @DPDMUX_METHOD_C_VLAN_MAC: DPDMUX based on C-VLAN and MAC address
16118+ * @DPDMUX_METHOD_MAC: DPDMUX based on MAC address
16119+ * @DPDMUX_METHOD_C_VLAN: DPDMUX based on C-VLAN
16120+ * @DPDMUX_METHOD_S_VLAN: DPDMUX based on S-VLAN
16121+ */
16122+enum dpdmux_method {
16123+ DPDMUX_METHOD_NONE = 0x0,
16124+ DPDMUX_METHOD_C_VLAN_MAC = 0x1,
16125+ DPDMUX_METHOD_MAC = 0x2,
16126+ DPDMUX_METHOD_C_VLAN = 0x3,
16127+ DPDMUX_METHOD_S_VLAN = 0x4
16128+};
16129+
16130+/**
16131+ * struct dpdmux_cfg - DPDMUX configuration parameters
16132+ * @method: Defines the operation method for the DPDMUX address table
16133+ * @manip: Required manipulation operation
16134+ * @num_ifs: Number of interfaces (excluding the uplink interface)
16135+ * @adv: Advanced parameters; default is all zeros;
16136+ * use this structure to change default settings
16137+ */
16138+struct dpdmux_cfg {
16139+ enum dpdmux_method method;
16140+ enum dpdmux_manip manip;
16141+ uint16_t num_ifs;
16142+ /**
16143+ * struct adv - Advanced parameters
16144+ * @options: DPDMUX options - combination of 'DPDMUX_OPT_<X>' flags
16145+ * @max_dmat_entries: Maximum entries in DPDMUX address table
16146+ * 0 - indicates default: 64 entries per interface.
16147+ * @max_mc_groups: Number of multicast groups in DPDMUX table
16148+ * 0 - indicates default: 32 multicast groups
16149+ * @max_vlan_ids: max vlan ids allowed in the system -
16150+ * relevant only case of working in mac+vlan method.
16151+ * 0 - indicates default 16 vlan ids.
16152+ */
16153+ struct {
16154+ uint64_t options;
16155+ uint16_t max_dmat_entries;
16156+ uint16_t max_mc_groups;
16157+ uint16_t max_vlan_ids;
16158+ } adv;
16159+};
16160+
16161+/**
16162+ * dpdmux_create() - Create the DPDMUX object
16163+ * @mc_io: Pointer to MC portal's I/O object
16164+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16165+ * @cfg: Configuration structure
16166+ * @token: Returned token; use in subsequent API calls
16167+ *
16168+ * Create the DPDMUX object, allocate required resources and
16169+ * perform required initialization.
16170+ *
16171+ * The object can be created either by declaring it in the
16172+ * DPL file, or by calling this function.
16173+ *
16174+ * This function returns a unique authentication token,
16175+ * associated with the specific object ID and the specific MC
16176+ * portal; this token must be used in all subsequent calls to
16177+ * this specific object. For objects that are created using the
16178+ * DPL file, call dpdmux_open() function to get an authentication
16179+ * token first.
16180+ *
16181+ * Return: '0' on Success; Error code otherwise.
16182+ */
16183+int dpdmux_create(struct fsl_mc_io *mc_io,
16184+ uint32_t cmd_flags,
16185+ const struct dpdmux_cfg *cfg,
16186+ uint16_t *token);
16187+
16188+/**
16189+ * dpdmux_destroy() - Destroy the DPDMUX object and release all its resources.
16190+ * @mc_io: Pointer to MC portal's I/O object
16191+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16192+ * @token: Token of DPDMUX object
16193+ *
16194+ * Return: '0' on Success; error code otherwise.
16195+ */
16196+int dpdmux_destroy(struct fsl_mc_io *mc_io,
16197+ uint32_t cmd_flags,
16198+ uint16_t token);
16199+
16200+/**
16201+ * dpdmux_enable() - Enable DPDMUX functionality
16202+ * @mc_io: Pointer to MC portal's I/O object
16203+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16204+ * @token: Token of DPDMUX object
16205+ *
16206+ * Return: '0' on Success; Error code otherwise.
16207+ */
16208+int dpdmux_enable(struct fsl_mc_io *mc_io,
16209+ uint32_t cmd_flags,
16210+ uint16_t token);
16211+
16212+/**
16213+ * dpdmux_disable() - Disable DPDMUX functionality
16214+ * @mc_io: Pointer to MC portal's I/O object
16215+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16216+ * @token: Token of DPDMUX object
16217+ *
16218+ * Return: '0' on Success; Error code otherwise.
16219+ */
16220+int dpdmux_disable(struct fsl_mc_io *mc_io,
16221+ uint32_t cmd_flags,
16222+ uint16_t token);
16223+
16224+/**
16225+ * dpdmux_is_enabled() - Check if the DPDMUX is enabled.
16226+ * @mc_io: Pointer to MC portal's I/O object
16227+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16228+ * @token: Token of DPDMUX object
16229+ * @en: Returns '1' if object is enabled; '0' otherwise
16230+ *
16231+ * Return: '0' on Success; Error code otherwise.
16232+ */
16233+int dpdmux_is_enabled(struct fsl_mc_io *mc_io,
16234+ uint32_t cmd_flags,
16235+ uint16_t token,
16236+ int *en);
16237+
16238+/**
16239+ * dpdmux_reset() - Reset the DPDMUX, returns the object to initial state.
16240+ * @mc_io: Pointer to MC portal's I/O object
16241+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16242+ * @token: Token of DPDMUX object
16243+ *
16244+ * Return: '0' on Success; Error code otherwise.
16245+ */
16246+int dpdmux_reset(struct fsl_mc_io *mc_io,
16247+ uint32_t cmd_flags,
16248+ uint16_t token);
16249+
16250+/**
16251+ * struct dpdmux_irq_cfg - IRQ configuration
16252+ * @addr: Address that must be written to signal a message-based interrupt
16253+ * @val: Value to write into irq_addr address
16254+ * @irq_num: A user defined number associated with this IRQ
16255+ */
16256+struct dpdmux_irq_cfg {
16257+ uint64_t addr;
16258+ uint32_t val;
16259+ int irq_num;
16260+};
16261+
16262+/**
16263+ * dpdmux_set_irq() - Set IRQ information for the DPDMUX to trigger an interrupt.
16264+ * @mc_io: Pointer to MC portal's I/O object
16265+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16266+ * @token: Token of DPDMUX object
16267+ * @irq_index: Identifies the interrupt index to configure
16268+ * @irq_cfg: IRQ configuration
16269+ *
16270+ * Return: '0' on Success; Error code otherwise.
16271+ */
16272+int dpdmux_set_irq(struct fsl_mc_io *mc_io,
16273+ uint32_t cmd_flags,
16274+ uint16_t token,
16275+ uint8_t irq_index,
16276+ struct dpdmux_irq_cfg *irq_cfg);
16277+
16278+/**
16279+ * dpdmux_get_irq() - Get IRQ information from the DPDMUX.
16280+ * @mc_io: Pointer to MC portal's I/O object
16281+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16282+ * @token: Token of DPDMUX object
16283+ * @irq_index: The interrupt index to configure
16284+ * @type: Interrupt type: 0 represents message interrupt
16285+ * type (both irq_addr and irq_val are valid)
16286+ * @irq_cfg: IRQ attributes
16287+ *
16288+ * Return: '0' on Success; Error code otherwise.
16289+ */
16290+int dpdmux_get_irq(struct fsl_mc_io *mc_io,
16291+ uint32_t cmd_flags,
16292+ uint16_t token,
16293+ uint8_t irq_index,
16294+ int *type,
16295+ struct dpdmux_irq_cfg *irq_cfg);
16296+
16297+/**
16298+ * dpdmux_set_irq_enable() - Set overall interrupt state.
16299+ * @mc_io: Pointer to MC portal's I/O object
16300+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16301+ * @token: Token of DPDMUX object
16302+ * @irq_index: The interrupt index to configure
16303+ * @en: Interrupt state - enable = 1, disable = 0
16304+ *
16305+ * Allows GPP software to control when interrupts are generated.
16306+ * Each interrupt can have up to 32 causes. The enable/disable control's the
16307+ * overall interrupt state. if the interrupt is disabled no causes will cause
16308+ * an interrupt.
16309+ *
16310+ * Return: '0' on Success; Error code otherwise.
16311+ */
16312+int dpdmux_set_irq_enable(struct fsl_mc_io *mc_io,
16313+ uint32_t cmd_flags,
16314+ uint16_t token,
16315+ uint8_t irq_index,
16316+ uint8_t en);
16317+
16318+/**
16319+ * dpdmux_get_irq_enable() - Get overall interrupt state.
16320+ * @mc_io: Pointer to MC portal's I/O object
16321+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16322+ * @token: Token of DPDMUX object
16323+ * @irq_index: The interrupt index to configure
16324+ * @en: Returned interrupt state - enable = 1, disable = 0
16325+ *
16326+ * Return: '0' on Success; Error code otherwise.
16327+ */
16328+int dpdmux_get_irq_enable(struct fsl_mc_io *mc_io,
16329+ uint32_t cmd_flags,
16330+ uint16_t token,
16331+ uint8_t irq_index,
16332+ uint8_t *en);
16333+
16334+/**
16335+ * dpdmux_set_irq_mask() - Set interrupt mask.
16336+ * @mc_io: Pointer to MC portal's I/O object
16337+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16338+ * @token: Token of DPDMUX object
16339+ * @irq_index: The interrupt index to configure
16340+ * @mask: event mask to trigger interrupt;
16341+ * each bit:
16342+ * 0 = ignore event
16343+ * 1 = consider event for asserting IRQ
16344+ *
16345+ * Every interrupt can have up to 32 causes and the interrupt model supports
16346+ * masking/unmasking each cause independently
16347+ *
16348+ * Return: '0' on Success; Error code otherwise.
16349+ */
16350+int dpdmux_set_irq_mask(struct fsl_mc_io *mc_io,
16351+ uint32_t cmd_flags,
16352+ uint16_t token,
16353+ uint8_t irq_index,
16354+ uint32_t mask);
16355+
16356+/**
16357+ * dpdmux_get_irq_mask() - Get interrupt mask.
16358+ * @mc_io: Pointer to MC portal's I/O object
16359+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16360+ * @token: Token of DPDMUX object
16361+ * @irq_index: The interrupt index to configure
16362+ * @mask: Returned event mask to trigger interrupt
16363+ *
16364+ * Every interrupt can have up to 32 causes and the interrupt model supports
16365+ * masking/unmasking each cause independently
16366+ *
16367+ * Return: '0' on Success; Error code otherwise.
16368+ */
16369+int dpdmux_get_irq_mask(struct fsl_mc_io *mc_io,
16370+ uint32_t cmd_flags,
16371+ uint16_t token,
16372+ uint8_t irq_index,
16373+ uint32_t *mask);
16374+
16375+/**
16376+ * dpdmux_get_irq_status() - Get the current status of any pending interrupts.
16377+ * @mc_io: Pointer to MC portal's I/O object
16378+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16379+ * @token: Token of DPDMUX object
16380+ * @irq_index: The interrupt index to configure
16381+ * @status: Returned interrupts status - one bit per cause:
16382+ * 0 = no interrupt pending
16383+ * 1 = interrupt pending
16384+ *
16385+ * Return: '0' on Success; Error code otherwise.
16386+ */
16387+int dpdmux_get_irq_status(struct fsl_mc_io *mc_io,
16388+ uint32_t cmd_flags,
16389+ uint16_t token,
16390+ uint8_t irq_index,
16391+ uint32_t *status);
16392+
16393+/**
16394+ * dpdmux_clear_irq_status() - Clear a pending interrupt's status
16395+ * @mc_io: Pointer to MC portal's I/O object
16396+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16397+ * @token: Token of DPDMUX object
16398+ * @irq_index: The interrupt index to configure
16399+ * @status: bits to clear (W1C) - one bit per cause:
16400+ * 0 = don't change
16401+ * 1 = clear status bit
16402+ *
16403+ * Return: '0' on Success; Error code otherwise.
16404+ */
16405+int dpdmux_clear_irq_status(struct fsl_mc_io *mc_io,
16406+ uint32_t cmd_flags,
16407+ uint16_t token,
16408+ uint8_t irq_index,
16409+ uint32_t status);
16410+
16411+/**
16412+ * struct dpdmux_attr - Structure representing DPDMUX attributes
16413+ * @id: DPDMUX object ID
16414+ * @version: DPDMUX version
16415+ * @options: Configuration options (bitmap)
16416+ * @method: DPDMUX address table method
16417+ * @manip: DPDMUX manipulation type
16418+ * @num_ifs: Number of interfaces (excluding the uplink interface)
16419+ * @mem_size: DPDMUX frame storage memory size
16420+ */
16421+struct dpdmux_attr {
16422+ int id;
16423+ /**
16424+ * struct version - DPDMUX version
16425+ * @major: DPDMUX major version
16426+ * @minor: DPDMUX minor version
16427+ */
16428+ struct {
16429+ uint16_t major;
16430+ uint16_t minor;
16431+ } version;
16432+ uint64_t options;
16433+ enum dpdmux_method method;
16434+ enum dpdmux_manip manip;
16435+ uint16_t num_ifs;
16436+ uint16_t mem_size;
16437+};
16438+
16439+/**
16440+ * dpdmux_get_attributes() - Retrieve DPDMUX attributes
16441+ * @mc_io: Pointer to MC portal's I/O object
16442+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16443+ * @token: Token of DPDMUX object
16444+ * @attr: Returned object's attributes
16445+ *
16446+ * Return: '0' on Success; Error code otherwise.
16447+ */
16448+int dpdmux_get_attributes(struct fsl_mc_io *mc_io,
16449+ uint32_t cmd_flags,
16450+ uint16_t token,
16451+ struct dpdmux_attr *attr);
16452+
16453+/**
16454+ * dpdmux_ul_set_max_frame_length() - Set the maximum frame length in DPDMUX
16455+ * @mc_io: Pointer to MC portal's I/O object
16456+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16457+ * @token: Token of DPDMUX object
16458+ * @max_frame_length: The required maximum frame length
16459+ *
16460+ * Return: '0' on Success; Error code otherwise.
16461+ */
16462+int dpdmux_ul_set_max_frame_length(struct fsl_mc_io *mc_io,
16463+ uint32_t cmd_flags,
16464+ uint16_t token,
16465+ uint16_t max_frame_length);
16466+
16467+/**
16468+ * enum dpdmux_counter_type - Counter types
16469+ * @DPDMUX_CNT_ING_FRAME: Counts ingress frames
16470+ * @DPDMUX_CNT_ING_BYTE: Counts ingress bytes
16471+ * @DPDMUX_CNT_ING_FLTR_FRAME: Counts filtered ingress frames
16472+ * @DPDMUX_CNT_ING_FRAME_DISCARD: Counts discarded ingress frames
16473+ * @DPDMUX_CNT_ING_MCAST_FRAME: Counts ingress multicast frames
16474+ * @DPDMUX_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes
16475+ * @DPDMUX_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames
16476+ * @DPDMUX_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes
16477+ * @DPDMUX_CNT_EGR_FRAME: Counts egress frames
16478+ * @DPDMUX_CNT_EGR_BYTE: Counts egress bytes
16479+ * @DPDMUX_CNT_EGR_FRAME_DISCARD: Counts discarded egress frames
16480+ */
16481+enum dpdmux_counter_type {
16482+ DPDMUX_CNT_ING_FRAME = 0x0,
16483+ DPDMUX_CNT_ING_BYTE = 0x1,
16484+ DPDMUX_CNT_ING_FLTR_FRAME = 0x2,
16485+ DPDMUX_CNT_ING_FRAME_DISCARD = 0x3,
16486+ DPDMUX_CNT_ING_MCAST_FRAME = 0x4,
16487+ DPDMUX_CNT_ING_MCAST_BYTE = 0x5,
16488+ DPDMUX_CNT_ING_BCAST_FRAME = 0x6,
16489+ DPDMUX_CNT_ING_BCAST_BYTES = 0x7,
16490+ DPDMUX_CNT_EGR_FRAME = 0x8,
16491+ DPDMUX_CNT_EGR_BYTE = 0x9,
16492+ DPDMUX_CNT_EGR_FRAME_DISCARD = 0xa
16493+};
16494+
16495+/**
16496+ * enum dpdmux_accepted_frames_type - DPDMUX frame types
16497+ * @DPDMUX_ADMIT_ALL: The device accepts VLAN tagged, untagged and
16498+ * priority-tagged frames
16499+ * @DPDMUX_ADMIT_ONLY_VLAN_TAGGED: The device discards untagged frames or
16500+ * priority-tagged frames that are received on this
16501+ * interface
16502+ * @DPDMUX_ADMIT_ONLY_UNTAGGED: Untagged frames or priority-tagged frames
16503+ * received on this interface are accepted
16504+ */
16505+enum dpdmux_accepted_frames_type {
16506+ DPDMUX_ADMIT_ALL = 0,
16507+ DPDMUX_ADMIT_ONLY_VLAN_TAGGED = 1,
16508+ DPDMUX_ADMIT_ONLY_UNTAGGED = 2
16509+};
16510+
16511+/**
16512+ * enum dpdmux_action - DPDMUX action for un-accepted frames
16513+ * @DPDMUX_ACTION_DROP: Drop un-accepted frames
16514+ * @DPDMUX_ACTION_REDIRECT_TO_CTRL: Redirect un-accepted frames to the
16515+ * control interface
16516+ */
16517+enum dpdmux_action {
16518+ DPDMUX_ACTION_DROP = 0,
16519+ DPDMUX_ACTION_REDIRECT_TO_CTRL = 1
16520+};
16521+
16522+/**
16523+ * struct dpdmux_accepted_frames - Frame types configuration
16524+ * @type: Defines ingress accepted frames
16525+ * @unaccept_act: Defines action on frames not accepted
16526+ */
16527+struct dpdmux_accepted_frames {
16528+ enum dpdmux_accepted_frames_type type;
16529+ enum dpdmux_action unaccept_act;
16530+};
16531+
16532+/**
16533+ * dpdmux_if_set_accepted_frames() - Set the accepted frame types
16534+ * @mc_io: Pointer to MC portal's I/O object
16535+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16536+ * @token: Token of DPDMUX object
16537+ * @if_id: Interface ID (0 for uplink, or 1-num_ifs);
16538+ * @cfg: Frame types configuration
16539+ *
16540+ * if 'DPDMUX_ADMIT_ONLY_VLAN_TAGGED' is set - untagged frames or
16541+ * priority-tagged frames are discarded.
16542+ * if 'DPDMUX_ADMIT_ONLY_UNTAGGED' is set - untagged frames or
16543+ * priority-tagged frames are accepted.
16544+ * if 'DPDMUX_ADMIT_ALL' is set (default mode) - all VLAN tagged,
16545+ * untagged and priority-tagged frame are accepted;
16546+ *
16547+ * Return: '0' on Success; Error code otherwise.
16548+ */
16549+int dpdmux_if_set_accepted_frames(struct fsl_mc_io *mc_io,
16550+ uint32_t cmd_flags,
16551+ uint16_t token,
16552+ uint16_t if_id,
16553+ const struct dpdmux_accepted_frames *cfg);
16554+
16555+/**
16556+ * struct dpdmux_if_attr - Structure representing frame types configuration
16557+ * @rate: Configured interface rate (in bits per second)
16558+ * @enabled: Indicates if interface is enabled
16559+ * @accept_frame_type: Indicates type of accepted frames for the interface
16560+ */
16561+struct dpdmux_if_attr {
16562+ uint32_t rate;
16563+ int enabled;
16564+ enum dpdmux_accepted_frames_type accept_frame_type;
16565+};
16566+
16567+/**
16568+ * dpdmux_if_get_attributes() - Obtain DPDMUX interface attributes
16569+ * @mc_io: Pointer to MC portal's I/O object
16570+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16571+ * @token: Token of DPDMUX object
16572+ * @if_id: Interface ID (0 for uplink, or 1-num_ifs);
16573+ * @attr: Interface attributes
16574+ *
16575+ * Return: '0' on Success; Error code otherwise.
16576+ */
16577+int dpdmux_if_get_attributes(struct fsl_mc_io *mc_io,
16578+ uint32_t cmd_flags,
16579+ uint16_t token,
16580+ uint16_t if_id,
16581+ struct dpdmux_if_attr *attr);
16582+
16583+/**
16584+ * struct dpdmux_l2_rule - Structure representing L2 rule
16585+ * @mac_addr: MAC address
16586+ * @vlan_id: VLAN ID
16587+ */
16588+struct dpdmux_l2_rule {
16589+ uint8_t mac_addr[6];
16590+ uint16_t vlan_id;
16591+};
16592+
16593+/**
16594+ * dpdmux_if_remove_l2_rule() - Remove L2 rule from DPDMUX table
16595+ * @mc_io: Pointer to MC portal's I/O object
16596+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16597+ * @token: Token of DPDMUX object
16598+ * @if_id: Destination interface ID
16599+ * @rule: L2 rule
16600+ *
16601+ * Function removes a L2 rule from DPDMUX table
16602+ * or adds an interface to an existing multicast address
16603+ *
16604+ * Return: '0' on Success; Error code otherwise.
16605+ */
16606+int dpdmux_if_remove_l2_rule(struct fsl_mc_io *mc_io,
16607+ uint32_t cmd_flags,
16608+ uint16_t token,
16609+ uint16_t if_id,
16610+ const struct dpdmux_l2_rule *rule);
16611+
16612+/**
16613+ * dpdmux_if_add_l2_rule() - Add L2 rule into DPDMUX table
16614+ * @mc_io: Pointer to MC portal's I/O object
16615+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16616+ * @token: Token of DPDMUX object
16617+ * @if_id: Destination interface ID
16618+ * @rule: L2 rule
16619+ *
16620+ * Function adds a L2 rule into DPDMUX table
16621+ * or adds an interface to an existing multicast address
16622+ *
16623+ * Return: '0' on Success; Error code otherwise.
16624+ */
16625+int dpdmux_if_add_l2_rule(struct fsl_mc_io *mc_io,
16626+ uint32_t cmd_flags,
16627+ uint16_t token,
16628+ uint16_t if_id,
16629+ const struct dpdmux_l2_rule *rule);
16630+
16631+/**
16632+* dpdmux_if_get_counter() - Functions obtains specific counter of an interface
16633+* @mc_io: Pointer to MC portal's I/O object
16634+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16635+* @token: Token of DPDMUX object
16636+* @if_id: Interface Id
16637+* @counter_type: counter type
16638+* @counter: Returned specific counter information
16639+*
16640+* Return: '0' on Success; Error code otherwise.
16641+*/
16642+int dpdmux_if_get_counter(struct fsl_mc_io *mc_io,
16643+ uint32_t cmd_flags,
16644+ uint16_t token,
16645+ uint16_t if_id,
16646+ enum dpdmux_counter_type counter_type,
16647+ uint64_t *counter);
16648+
16649+/**
16650+* dpdmux_ul_reset_counters() - Function resets the uplink counter
16651+* @mc_io: Pointer to MC portal's I/O object
16652+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16653+* @token: Token of DPDMUX object
16654+*
16655+* Return: '0' on Success; Error code otherwise.
16656+*/
16657+int dpdmux_ul_reset_counters(struct fsl_mc_io *mc_io,
16658+ uint32_t cmd_flags,
16659+ uint16_t token);
16660+
16661+/**
16662+ * Enable auto-negotiation
16663+ */
16664+#define DPDMUX_LINK_OPT_AUTONEG 0x0000000000000001ULL
16665+/**
16666+ * Enable half-duplex mode
16667+ */
16668+#define DPDMUX_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL
16669+/**
16670+ * Enable pause frames
16671+ */
16672+#define DPDMUX_LINK_OPT_PAUSE 0x0000000000000004ULL
16673+/**
16674+ * Enable a-symmetric pause frames
16675+ */
16676+#define DPDMUX_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL
16677+
16678+/**
16679+ * struct dpdmux_link_cfg - Structure representing DPDMUX link configuration
16680+ * @rate: Rate
16681+ * @options: Mask of available options; use 'DPDMUX_LINK_OPT_<X>' values
16682+ */
16683+struct dpdmux_link_cfg {
16684+ uint32_t rate;
16685+ uint64_t options;
16686+};
16687+
16688+/**
16689+ * dpdmux_if_set_link_cfg() - set the link configuration.
16690+ * @mc_io: Pointer to MC portal's I/O object
16691+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16692+ * @token: Token of DPSW object
16693+ * @if_id: interface id
16694+ * @cfg: Link configuration
16695+ *
16696+ * Return: '0' on Success; Error code otherwise.
16697+ */
16698+int dpdmux_if_set_link_cfg(struct fsl_mc_io *mc_io,
16699+ uint32_t cmd_flags,
16700+ uint16_t token,
16701+ uint16_t if_id,
16702+ struct dpdmux_link_cfg *cfg);
16703+/**
16704+ * struct dpdmux_link_state - Structure representing DPDMUX link state
16705+ * @rate: Rate
16706+ * @options: Mask of available options; use 'DPDMUX_LINK_OPT_<X>' values
16707+ * @up: 0 - down, 1 - up
16708+ */
16709+struct dpdmux_link_state {
16710+ uint32_t rate;
16711+ uint64_t options;
16712+ int up;
16713+};
16714+
16715+/**
16716+ * dpdmux_if_get_link_state - Return the link state
16717+ * @mc_io: Pointer to MC portal's I/O object
16718+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
16719+ * @token: Token of DPSW object
16720+ * @if_id: interface id
16721+ * @state: link state
16722+ *
16723+ * @returns '0' on Success; Error code otherwise.
16724+ */
16725+int dpdmux_if_get_link_state(struct fsl_mc_io *mc_io,
16726+ uint32_t cmd_flags,
16727+ uint16_t token,
16728+ uint16_t if_id,
16729+ struct dpdmux_link_state *state);
16730+
16731+#endif /* __FSL_DPDMUX_H */
16732diff --git a/drivers/net/dpaa2/mc/fsl_dpdmux_cmd.h b/drivers/net/dpaa2/mc/fsl_dpdmux_cmd.h
16733new file mode 100644
16734index 0000000..0a5cf17
16735--- /dev/null
16736+++ b/drivers/net/dpaa2/mc/fsl_dpdmux_cmd.h
16737@@ -0,0 +1,256 @@
16738+/* Copyright 2013-2015 Freescale Semiconductor Inc.
16739+ *
16740+ * Redistribution and use in source and binary forms, with or without
16741+ * modification, are permitted provided that the following conditions are met:
16742+ * * Redistributions of source code must retain the above copyright
16743+ * notice, this list of conditions and the following disclaimer.
16744+ * * Redistributions in binary form must reproduce the above copyright
16745+ * notice, this list of conditions and the following disclaimer in the
16746+ * documentation and/or other materials provided with the distribution.
16747+ * * Neither the name of the above-listed copyright holders nor the
16748+ * names of any contributors may be used to endorse or promote products
16749+ * derived from this software without specific prior written permission.
16750+ *
16751+ *
16752+ * ALTERNATIVELY, this software may be distributed under the terms of the
16753+ * GNU General Public License ("GPL") as published by the Free Software
16754+ * Foundation, either version 2 of that License or (at your option) any
16755+ * later version.
16756+ *
16757+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16758+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16759+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16760+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
16761+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
16762+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
16763+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
16764+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
16765+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
16766+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
16767+ * POSSIBILITY OF SUCH DAMAGE.
16768+ */
16769+#ifndef _FSL_DPDMUX_CMD_H
16770+#define _FSL_DPDMUX_CMD_H
16771+
16772+/* DPDMUX Version */
16773+#define DPDMUX_VER_MAJOR 5
16774+#define DPDMUX_VER_MINOR 0
16775+
16776+/* Command IDs */
16777+#define DPDMUX_CMDID_CLOSE 0x800
16778+#define DPDMUX_CMDID_OPEN 0x806
16779+#define DPDMUX_CMDID_CREATE 0x906
16780+#define DPDMUX_CMDID_DESTROY 0x900
16781+
16782+#define DPDMUX_CMDID_ENABLE 0x002
16783+#define DPDMUX_CMDID_DISABLE 0x003
16784+#define DPDMUX_CMDID_GET_ATTR 0x004
16785+#define DPDMUX_CMDID_RESET 0x005
16786+#define DPDMUX_CMDID_IS_ENABLED 0x006
16787+
16788+#define DPDMUX_CMDID_SET_IRQ 0x010
16789+#define DPDMUX_CMDID_GET_IRQ 0x011
16790+#define DPDMUX_CMDID_SET_IRQ_ENABLE 0x012
16791+#define DPDMUX_CMDID_GET_IRQ_ENABLE 0x013
16792+#define DPDMUX_CMDID_SET_IRQ_MASK 0x014
16793+#define DPDMUX_CMDID_GET_IRQ_MASK 0x015
16794+#define DPDMUX_CMDID_GET_IRQ_STATUS 0x016
16795+#define DPDMUX_CMDID_CLEAR_IRQ_STATUS 0x017
16796+
16797+#define DPDMUX_CMDID_UL_SET_MAX_FRAME_LENGTH 0x0a1
16798+
16799+#define DPDMUX_CMDID_UL_RESET_COUNTERS 0x0a3
16800+
16801+#define DPDMUX_CMDID_IF_SET_ACCEPTED_FRAMES 0x0a7
16802+#define DPDMUX_CMDID_IF_GET_ATTR 0x0a8
16803+
16804+#define DPDMUX_CMDID_IF_ADD_L2_RULE 0x0b0
16805+#define DPDMUX_CMDID_IF_REMOVE_L2_RULE 0x0b1
16806+#define DPDMUX_CMDID_IF_GET_COUNTER 0x0b2
16807+#define DPDMUX_CMDID_IF_SET_LINK_CFG 0x0b3
16808+#define DPDMUX_CMDID_IF_GET_LINK_STATE 0x0b4
16809+
16810+/* cmd, param, offset, width, type, arg_name */
16811+#define DPDMUX_CMD_OPEN(cmd, dpdmux_id) \
16812+ MC_CMD_OP(cmd, 0, 0, 32, int, dpdmux_id)
16813+
16814+/* cmd, param, offset, width, type, arg_name */
16815+#define DPDMUX_CMD_CREATE(cmd, cfg) \
16816+do { \
16817+ MC_CMD_OP(cmd, 0, 0, 8, enum dpdmux_method, cfg->method);\
16818+ MC_CMD_OP(cmd, 0, 8, 8, enum dpdmux_manip, cfg->manip);\
16819+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs);\
16820+ MC_CMD_OP(cmd, 1, 0, 16, uint16_t, cfg->adv.max_dmat_entries);\
16821+ MC_CMD_OP(cmd, 1, 16, 16, uint16_t, cfg->adv.max_mc_groups);\
16822+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, cfg->adv.max_vlan_ids);\
16823+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->adv.options);\
16824+} while (0)
16825+
16826+/* cmd, param, offset, width, type, arg_name */
16827+#define DPDMUX_RSP_IS_ENABLED(cmd, en) \
16828+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
16829+
16830+/* cmd, param, offset, width, type, arg_name */
16831+#define DPDMUX_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
16832+do { \
16833+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
16834+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
16835+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
16836+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
16837+} while (0)
16838+
16839+/* cmd, param, offset, width, type, arg_name */
16840+#define DPDMUX_CMD_GET_IRQ(cmd, irq_index) \
16841+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
16842+
16843+/* cmd, param, offset, width, type, arg_name */
16844+#define DPDMUX_RSP_GET_IRQ(cmd, type, irq_cfg) \
16845+do { \
16846+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
16847+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
16848+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
16849+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
16850+} while (0)
16851+
16852+/* cmd, param, offset, width, type, arg_name */
16853+#define DPDMUX_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \
16854+do { \
16855+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en);\
16856+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
16857+} while (0)
16858+
16859+/* cmd, param, offset, width, type, arg_name */
16860+#define DPDMUX_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
16861+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
16862+
16863+/* cmd, param, offset, width, type, arg_name */
16864+#define DPDMUX_RSP_GET_IRQ_ENABLE(cmd, en) \
16865+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en)
16866+
16867+/* cmd, param, offset, width, type, arg_name */
16868+#define DPDMUX_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
16869+do { \
16870+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
16871+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
16872+} while (0)
16873+
16874+/* cmd, param, offset, width, type, arg_name */
16875+#define DPDMUX_CMD_GET_IRQ_MASK(cmd, irq_index) \
16876+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
16877+
16878+/* cmd, param, offset, width, type, arg_name */
16879+#define DPDMUX_RSP_GET_IRQ_MASK(cmd, mask) \
16880+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
16881+
16882+/* cmd, param, offset, width, type, arg_name */
16883+#define DPDMUX_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
16884+do { \
16885+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
16886+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
16887+} while (0)
16888+
16889+/* cmd, param, offset, width, type, arg_name */
16890+#define DPDMUX_RSP_GET_IRQ_STATUS(cmd, status) \
16891+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status) \
16892+
16893+/* cmd, param, offset, width, type, arg_name */
16894+#define DPDMUX_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
16895+do { \
16896+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
16897+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
16898+} while (0)
16899+
16900+#define DPDMUX_RSP_GET_ATTR(cmd, attr) \
16901+do { \
16902+ MC_RSP_OP(cmd, 0, 0, 8, enum dpdmux_method, attr->method);\
16903+ MC_RSP_OP(cmd, 0, 8, 8, enum dpdmux_manip, attr->manip);\
16904+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->num_ifs);\
16905+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->mem_size);\
16906+ MC_RSP_OP(cmd, 2, 0, 32, int, attr->id);\
16907+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, attr->options);\
16908+ MC_RSP_OP(cmd, 4, 0, 16, uint16_t, attr->version.major);\
16909+ MC_RSP_OP(cmd, 4, 16, 16, uint16_t, attr->version.minor);\
16910+} while (0)
16911+
16912+/* cmd, param, offset, width, type, arg_name */
16913+#define DPDMUX_CMD_UL_SET_MAX_FRAME_LENGTH(cmd, max_frame_length) \
16914+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, max_frame_length)
16915+
16916+/* cmd, param, offset, width, type, arg_name */
16917+#define DPDMUX_CMD_IF_SET_ACCEPTED_FRAMES(cmd, if_id, cfg) \
16918+do { \
16919+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
16920+ MC_CMD_OP(cmd, 0, 16, 4, enum dpdmux_accepted_frames_type, cfg->type);\
16921+ MC_CMD_OP(cmd, 0, 20, 4, enum dpdmux_unaccepted_frames_action, \
16922+ cfg->unaccept_act);\
16923+} while (0)
16924+
16925+/* cmd, param, offset, width, type, arg_name */
16926+#define DPDMUX_CMD_IF_GET_ATTR(cmd, if_id) \
16927+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id)
16928+
16929+/* cmd, param, offset, width, type, arg_name */
16930+#define DPDMUX_RSP_IF_GET_ATTR(cmd, attr) \
16931+do { \
16932+ MC_RSP_OP(cmd, 0, 56, 4, enum dpdmux_accepted_frames_type, \
16933+ attr->accept_frame_type);\
16934+ MC_RSP_OP(cmd, 0, 24, 1, int, attr->enabled);\
16935+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->rate);\
16936+} while (0)
16937+
16938+#define DPDMUX_CMD_IF_REMOVE_L2_RULE(cmd, if_id, l2_rule) \
16939+do { \
16940+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
16941+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, l2_rule->mac_addr[5]);\
16942+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, l2_rule->mac_addr[4]);\
16943+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, l2_rule->mac_addr[3]);\
16944+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, l2_rule->mac_addr[2]);\
16945+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, l2_rule->mac_addr[1]);\
16946+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, l2_rule->mac_addr[0]);\
16947+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, l2_rule->vlan_id);\
16948+} while (0)
16949+
16950+#define DPDMUX_CMD_IF_ADD_L2_RULE(cmd, if_id, l2_rule) \
16951+do { \
16952+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
16953+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, l2_rule->mac_addr[5]);\
16954+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, l2_rule->mac_addr[4]);\
16955+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, l2_rule->mac_addr[3]);\
16956+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, l2_rule->mac_addr[2]);\
16957+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, l2_rule->mac_addr[1]);\
16958+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, l2_rule->mac_addr[0]);\
16959+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, l2_rule->vlan_id);\
16960+} while (0)
16961+
16962+/* cmd, param, offset, width, type, arg_name */
16963+#define DPDMUX_CMD_IF_GET_COUNTER(cmd, if_id, counter_type) \
16964+do { \
16965+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
16966+ MC_CMD_OP(cmd, 0, 16, 8, enum dpdmux_counter_type, counter_type);\
16967+} while (0)
16968+
16969+/* cmd, param, offset, width, type, arg_name */
16970+#define DPDMUX_RSP_IF_GET_COUNTER(cmd, counter) \
16971+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter)
16972+
16973+/* cmd, param, offset, width, type, arg_name */
16974+#define DPDMUX_CMD_IF_SET_LINK_CFG(cmd, if_id, cfg) \
16975+do { \
16976+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
16977+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate);\
16978+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options);\
16979+} while (0)
16980+
16981+/* cmd, param, offset, width, type, arg_name */
16982+#define DPDMUX_CMD_IF_GET_LINK_STATE(cmd, if_id) \
16983+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id)
16984+
16985+/* cmd, param, offset, width, type, arg_name */
16986+#define DPDMUX_RSP_IF_GET_LINK_STATE(cmd, state) \
16987+do { \
16988+ MC_RSP_OP(cmd, 0, 32, 1, int, state->up);\
16989+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, state->rate);\
16990+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\
16991+} while (0)
16992+
16993+#endif /* _FSL_DPDMUX_CMD_H */
16994diff --git a/drivers/net/dpaa2/mc/fsl_dpio.h b/drivers/net/dpaa2/mc/fsl_dpio.h
16995new file mode 100644
16996index 0000000..88a492f
16997--- /dev/null
16998+++ b/drivers/net/dpaa2/mc/fsl_dpio.h
16999@@ -0,0 +1,460 @@
17000+/* Copyright 2013-2015 Freescale Semiconductor Inc.
17001+ *
17002+ * Redistribution and use in source and binary forms, with or without
17003+ * modification, are permitted provided that the following conditions are met:
17004+ * * Redistributions of source code must retain the above copyright
17005+ * notice, this list of conditions and the following disclaimer.
17006+ * * Redistributions in binary form must reproduce the above copyright
17007+ * notice, this list of conditions and the following disclaimer in the
17008+ * documentation and/or other materials provided with the distribution.
17009+ * * Neither the name of the above-listed copyright holders nor the
17010+ * names of any contributors may be used to endorse or promote products
17011+ * derived from this software without specific prior written permission.
17012+ *
17013+ *
17014+ * ALTERNATIVELY, this software may be distributed under the terms of the
17015+ * GNU General Public License ("GPL") as published by the Free Software
17016+ * Foundation, either version 2 of that License or (at your option) any
17017+ * later version.
17018+ *
17019+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17020+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17021+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17022+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
17023+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
17024+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
17025+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
17026+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
17027+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
17028+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
17029+ * POSSIBILITY OF SUCH DAMAGE.
17030+ */
17031+#ifndef __FSL_DPIO_H
17032+#define __FSL_DPIO_H
17033+
17034+/* Data Path I/O Portal API
17035+ * Contains initialization APIs and runtime control APIs for DPIO
17036+ */
17037+
17038+struct fsl_mc_io;
17039+
17040+/**
17041+ * dpio_open() - Open a control session for the specified object
17042+ * @mc_io: Pointer to MC portal's I/O object
17043+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17044+ * @dpio_id: DPIO unique ID
17045+ * @token: Returned token; use in subsequent API calls
17046+ *
17047+ * This function can be used to open a control session for an
17048+ * already created object; an object may have been declared in
17049+ * the DPL or by calling the dpio_create() function.
17050+ * This function returns a unique authentication token,
17051+ * associated with the specific object ID and the specific MC
17052+ * portal; this token must be used in all subsequent commands for
17053+ * this specific object.
17054+ *
17055+ * Return: '0' on Success; Error code otherwise.
17056+ */
17057+int dpio_open(struct fsl_mc_io *mc_io,
17058+ uint32_t cmd_flags,
17059+ int dpio_id,
17060+ uint16_t *token);
17061+
17062+/**
17063+ * dpio_close() - Close the control session of the object
17064+ * @mc_io: Pointer to MC portal's I/O object
17065+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17066+ * @token: Token of DPIO object
17067+ *
17068+ * Return: '0' on Success; Error code otherwise.
17069+ */
17070+int dpio_close(struct fsl_mc_io *mc_io,
17071+ uint32_t cmd_flags,
17072+ uint16_t token);
17073+
17074+/**
17075+ * enum dpio_channel_mode - DPIO notification channel mode
17076+ * @DPIO_NO_CHANNEL: No support for notification channel
17077+ * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a
17078+ * dedicated channel in the DPIO; user should point the queue's
17079+ * destination in the relevant interface to this DPIO
17080+ */
17081+enum dpio_channel_mode {
17082+ DPIO_NO_CHANNEL = 0,
17083+ DPIO_LOCAL_CHANNEL = 1,
17084+};
17085+
17086+/**
17087+ * struct dpio_cfg - Structure representing DPIO configuration
17088+ * @channel_mode: Notification channel mode
17089+ * @num_priorities: Number of priorities for the notification channel (1-8);
17090+ * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
17091+ */
17092+struct dpio_cfg {
17093+ enum dpio_channel_mode channel_mode;
17094+ uint8_t num_priorities;
17095+};
17096+
17097+/**
17098+ * dpio_create() - Create the DPIO object.
17099+ * @mc_io: Pointer to MC portal's I/O object
17100+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17101+ * @cfg: Configuration structure
17102+ * @token: Returned token; use in subsequent API calls
17103+ *
17104+ * Create the DPIO object, allocate required resources and
17105+ * perform required initialization.
17106+ *
17107+ * The object can be created either by declaring it in the
17108+ * DPL file, or by calling this function.
17109+ *
17110+ * This function returns a unique authentication token,
17111+ * associated with the specific object ID and the specific MC
17112+ * portal; this token must be used in all subsequent calls to
17113+ * this specific object. For objects that are created using the
17114+ * DPL file, call dpio_open() function to get an authentication
17115+ * token first.
17116+ *
17117+ * Return: '0' on Success; Error code otherwise.
17118+ */
17119+int dpio_create(struct fsl_mc_io *mc_io,
17120+ uint32_t cmd_flags,
17121+ const struct dpio_cfg *cfg,
17122+ uint16_t *token);
17123+
17124+/**
17125+ * dpio_destroy() - Destroy the DPIO object and release all its resources.
17126+ * @mc_io: Pointer to MC portal's I/O object
17127+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17128+ * @token: Token of DPIO object
17129+ *
17130+ * Return: '0' on Success; Error code otherwise
17131+ */
17132+int dpio_destroy(struct fsl_mc_io *mc_io,
17133+ uint32_t cmd_flags,
17134+ uint16_t token);
17135+
17136+/**
17137+ * dpio_enable() - Enable the DPIO, allow I/O portal operations.
17138+ * @mc_io: Pointer to MC portal's I/O object
17139+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17140+ * @token: Token of DPIO object
17141+ *
17142+ * Return: '0' on Success; Error code otherwise
17143+ */
17144+int dpio_enable(struct fsl_mc_io *mc_io,
17145+ uint32_t cmd_flags,
17146+ uint16_t token);
17147+
17148+/**
17149+ * dpio_disable() - Disable the DPIO, stop any I/O portal operation.
17150+ * @mc_io: Pointer to MC portal's I/O object
17151+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17152+ * @token: Token of DPIO object
17153+ *
17154+ * Return: '0' on Success; Error code otherwise
17155+ */
17156+int dpio_disable(struct fsl_mc_io *mc_io,
17157+ uint32_t cmd_flags,
17158+ uint16_t token);
17159+
17160+/**
17161+ * dpio_is_enabled() - Check if the DPIO is enabled.
17162+ * @mc_io: Pointer to MC portal's I/O object
17163+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17164+ * @token: Token of DPIO object
17165+ * @en: Returns '1' if object is enabled; '0' otherwise
17166+ *
17167+ * Return: '0' on Success; Error code otherwise.
17168+ */
17169+int dpio_is_enabled(struct fsl_mc_io *mc_io,
17170+ uint32_t cmd_flags,
17171+ uint16_t token,
17172+ int *en);
17173+
17174+/**
17175+ * dpio_reset() - Reset the DPIO, returns the object to initial state.
17176+ * @mc_io: Pointer to MC portal's I/O object
17177+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17178+ * @token: Token of DPIO object
17179+ *
17180+ * Return: '0' on Success; Error code otherwise.
17181+ */
17182+int dpio_reset(struct fsl_mc_io *mc_io,
17183+ uint32_t cmd_flags,
17184+ uint16_t token);
17185+
17186+/**
17187+ * dpio_set_stashing_destination() - Set the stashing destination.
17188+ * @mc_io: Pointer to MC portal's I/O object
17189+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17190+ * @token: Token of DPIO object
17191+ * @sdest: stashing destination value
17192+ *
17193+ * Return: '0' on Success; Error code otherwise.
17194+ */
17195+int dpio_set_stashing_destination(struct fsl_mc_io *mc_io,
17196+ uint32_t cmd_flags,
17197+ uint16_t token,
17198+ uint8_t sdest);
17199+
17200+/**
17201+ * dpio_get_stashing_destination() - Get the stashing destination..
17202+ * @mc_io: Pointer to MC portal's I/O object
17203+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17204+ * @token: Token of DPIO object
17205+ * @sdest: Returns the stashing destination value
17206+ *
17207+ * Return: '0' on Success; Error code otherwise.
17208+ */
17209+int dpio_get_stashing_destination(struct fsl_mc_io *mc_io,
17210+ uint32_t cmd_flags,
17211+ uint16_t token,
17212+ uint8_t *sdest);
17213+
17214+/**
17215+ * dpio_add_static_dequeue_channel() - Add a static dequeue channel.
17216+ * @mc_io: Pointer to MC portal's I/O object
17217+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17218+ * @token: Token of DPIO object
17219+ * @dpcon_id: DPCON object ID
17220+ * @channel_index: Returned channel index to be used in qbman API
17221+ *
17222+ * Return: '0' on Success; Error code otherwise.
17223+ */
17224+int dpio_add_static_dequeue_channel(struct fsl_mc_io *mc_io,
17225+ uint32_t cmd_flags,
17226+ uint16_t token,
17227+ int dpcon_id,
17228+ uint8_t *channel_index);
17229+
17230+/**
17231+ * dpio_remove_static_dequeue_channel() - Remove a static dequeue channel.
17232+ * @mc_io: Pointer to MC portal's I/O object
17233+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17234+ * @token: Token of DPIO object
17235+ * @dpcon_id: DPCON object ID
17236+ *
17237+ * Return: '0' on Success; Error code otherwise.
17238+ */
17239+int dpio_remove_static_dequeue_channel(struct fsl_mc_io *mc_io,
17240+ uint32_t cmd_flags,
17241+ uint16_t token,
17242+ int dpcon_id);
17243+
17244+/**
17245+ * DPIO IRQ Index and Events
17246+ */
17247+
17248+/**
17249+ * Irq software-portal index
17250+ */
17251+#define DPIO_IRQ_SWP_INDEX 0
17252+
17253+/**
17254+ * struct dpio_irq_cfg - IRQ configuration
17255+ * @addr: Address that must be written to signal a message-based interrupt
17256+ * @val: Value to write into irq_addr address
17257+ * @irq_num: A user defined number associated with this IRQ
17258+ */
17259+struct dpio_irq_cfg {
17260+ uint64_t addr;
17261+ uint32_t val;
17262+ int irq_num;
17263+};
17264+
17265+/**
17266+ * dpio_set_irq() - Set IRQ information for the DPIO to trigger an interrupt.
17267+ * @mc_io: Pointer to MC portal's I/O object
17268+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17269+ * @token: Token of DPIO object
17270+ * @irq_index: Identifies the interrupt index to configure
17271+ * @irq_cfg: IRQ configuration
17272+ *
17273+ * Return: '0' on Success; Error code otherwise.
17274+ */
17275+int dpio_set_irq(struct fsl_mc_io *mc_io,
17276+ uint32_t cmd_flags,
17277+ uint16_t token,
17278+ uint8_t irq_index,
17279+ struct dpio_irq_cfg *irq_cfg);
17280+
17281+/**
17282+ * dpio_get_irq() - Get IRQ information from the DPIO.
17283+ *
17284+ * @mc_io: Pointer to MC portal's I/O object
17285+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17286+ * @token: Token of DPIO object
17287+ * @irq_index: The interrupt index to configure
17288+ * @type: Interrupt type: 0 represents message interrupt
17289+ * type (both irq_addr and irq_val are valid)
17290+ * @irq_cfg: IRQ attributes
17291+ *
17292+ * Return: '0' on Success; Error code otherwise.
17293+ */
17294+int dpio_get_irq(struct fsl_mc_io *mc_io,
17295+ uint32_t cmd_flags,
17296+ uint16_t token,
17297+ uint8_t irq_index,
17298+ int *type,
17299+ struct dpio_irq_cfg *irq_cfg);
17300+
17301+/**
17302+ * dpio_set_irq_enable() - Set overall interrupt state.
17303+ * @mc_io: Pointer to MC portal's I/O object
17304+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17305+ * @token: Token of DPIO object
17306+ * @irq_index: The interrupt index to configure
17307+ * @en: Interrupt state - enable = 1, disable = 0
17308+ *
17309+ * Allows GPP software to control when interrupts are generated.
17310+ * Each interrupt can have up to 32 causes. The enable/disable control's the
17311+ * overall interrupt state. if the interrupt is disabled no causes will cause
17312+ * an interrupt.
17313+ *
17314+ * Return: '0' on Success; Error code otherwise.
17315+ */
17316+int dpio_set_irq_enable(struct fsl_mc_io *mc_io,
17317+ uint32_t cmd_flags,
17318+ uint16_t token,
17319+ uint8_t irq_index,
17320+ uint8_t en);
17321+
17322+/**
17323+ * dpio_get_irq_enable() - Get overall interrupt state
17324+ * @mc_io: Pointer to MC portal's I/O object
17325+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17326+ * @token: Token of DPIO object
17327+ * @irq_index: The interrupt index to configure
17328+ * @en: Returned interrupt state - enable = 1, disable = 0
17329+ *
17330+ * Return: '0' on Success; Error code otherwise.
17331+ */
17332+int dpio_get_irq_enable(struct fsl_mc_io *mc_io,
17333+ uint32_t cmd_flags,
17334+ uint16_t token,
17335+ uint8_t irq_index,
17336+ uint8_t *en);
17337+
17338+/**
17339+ * dpio_set_irq_mask() - Set interrupt mask.
17340+ * @mc_io: Pointer to MC portal's I/O object
17341+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17342+ * @token: Token of DPIO object
17343+ * @irq_index: The interrupt index to configure
17344+ * @mask: event mask to trigger interrupt;
17345+ * each bit:
17346+ * 0 = ignore event
17347+ * 1 = consider event for asserting IRQ
17348+ *
17349+ * Every interrupt can have up to 32 causes and the interrupt model supports
17350+ * masking/unmasking each cause independently
17351+ *
17352+ * Return: '0' on Success; Error code otherwise.
17353+ */
17354+int dpio_set_irq_mask(struct fsl_mc_io *mc_io,
17355+ uint32_t cmd_flags,
17356+ uint16_t token,
17357+ uint8_t irq_index,
17358+ uint32_t mask);
17359+
17360+/**
17361+ * dpio_get_irq_mask() - Get interrupt mask.
17362+ * @mc_io: Pointer to MC portal's I/O object
17363+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17364+ * @token: Token of DPIO object
17365+ * @irq_index: The interrupt index to configure
17366+ * @mask: Returned event mask to trigger interrupt
17367+ *
17368+ * Every interrupt can have up to 32 causes and the interrupt model supports
17369+ * masking/unmasking each cause independently
17370+ *
17371+ * Return: '0' on Success; Error code otherwise.
17372+ */
17373+int dpio_get_irq_mask(struct fsl_mc_io *mc_io,
17374+ uint32_t cmd_flags,
17375+ uint16_t token,
17376+ uint8_t irq_index,
17377+ uint32_t *mask);
17378+
17379+/**
17380+ * dpio_get_irq_status() - Get the current status of any pending interrupts.
17381+ * @mc_io: Pointer to MC portal's I/O object
17382+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17383+ * @token: Token of DPIO object
17384+ * @irq_index: The interrupt index to configure
17385+ * @status: Returned interrupts status - one bit per cause:
17386+ * 0 = no interrupt pending
17387+ * 1 = interrupt pending
17388+ *
17389+ * Return: '0' on Success; Error code otherwise.
17390+ */
17391+int dpio_get_irq_status(struct fsl_mc_io *mc_io,
17392+ uint32_t cmd_flags,
17393+ uint16_t token,
17394+ uint8_t irq_index,
17395+ uint32_t *status);
17396+
17397+/**
17398+ * dpio_clear_irq_status() - Clear a pending interrupt's status
17399+ * @mc_io: Pointer to MC portal's I/O object
17400+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17401+ * @token: Token of DPIO object
17402+ * @irq_index: The interrupt index to configure
17403+ * @status: bits to clear (W1C) - one bit per cause:
17404+ * 0 = don't change
17405+ * 1 = clear status bit
17406+ *
17407+ * Return: '0' on Success; Error code otherwise.
17408+ */
17409+int dpio_clear_irq_status(struct fsl_mc_io *mc_io,
17410+ uint32_t cmd_flags,
17411+ uint16_t token,
17412+ uint8_t irq_index,
17413+ uint32_t status);
17414+
17415+/**
17416+ * struct dpio_attr - Structure representing DPIO attributes
17417+ * @id: DPIO object ID
17418+ * @version: DPIO version
17419+ * @qbman_portal_ce_offset: offset of the software portal cache-enabled area
17420+ * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area
17421+ * @qbman_portal_id: Software portal ID
17422+ * @channel_mode: Notification channel mode
17423+ * @num_priorities: Number of priorities for the notification channel (1-8);
17424+ * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
17425+ * @qbman_version: QBMAN version
17426+ */
17427+struct dpio_attr {
17428+ int id;
17429+ /**
17430+ * struct version - DPIO version
17431+ * @major: DPIO major version
17432+ * @minor: DPIO minor version
17433+ */
17434+ struct {
17435+ uint16_t major;
17436+ uint16_t minor;
17437+ } version;
17438+ uint64_t qbman_portal_ce_offset;
17439+ uint64_t qbman_portal_ci_offset;
17440+ uint16_t qbman_portal_id;
17441+ enum dpio_channel_mode channel_mode;
17442+ uint8_t num_priorities;
17443+ uint32_t qbman_version;
17444+};
17445+
17446+/**
17447+ * dpio_get_attributes() - Retrieve DPIO attributes
17448+ * @mc_io: Pointer to MC portal's I/O object
17449+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17450+ * @token: Token of DPIO object
17451+ * @attr: Returned object's attributes
17452+ *
17453+ * Return: '0' on Success; Error code otherwise
17454+ */
17455+int dpio_get_attributes(struct fsl_mc_io *mc_io,
17456+ uint32_t cmd_flags,
17457+ uint16_t token,
17458+ struct dpio_attr *attr);
17459+#endif /* __FSL_DPIO_H */
17460diff --git a/drivers/net/dpaa2/mc/fsl_dpio_cmd.h b/drivers/net/dpaa2/mc/fsl_dpio_cmd.h
17461new file mode 100644
17462index 0000000..f339cd6
17463--- /dev/null
17464+++ b/drivers/net/dpaa2/mc/fsl_dpio_cmd.h
17465@@ -0,0 +1,184 @@
17466+/* Copyright 2013-2015 Freescale Semiconductor Inc.
17467+ *
17468+ * Redistribution and use in source and binary forms, with or without
17469+ * modification, are permitted provided that the following conditions are met:
17470+ * * Redistributions of source code must retain the above copyright
17471+ * notice, this list of conditions and the following disclaimer.
17472+ * * Redistributions in binary form must reproduce the above copyright
17473+ * notice, this list of conditions and the following disclaimer in the
17474+ * documentation and/or other materials provided with the distribution.
17475+ * * Neither the name of the above-listed copyright holders nor the
17476+ * names of any contributors may be used to endorse or promote products
17477+ * derived from this software without specific prior written permission.
17478+ *
17479+ *
17480+ * ALTERNATIVELY, this software may be distributed under the terms of the
17481+ * GNU General Public License ("GPL") as published by the Free Software
17482+ * Foundation, either version 2 of that License or (at your option) any
17483+ * later version.
17484+ *
17485+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17486+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17487+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17488+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
17489+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
17490+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
17491+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
17492+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
17493+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
17494+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
17495+ * POSSIBILITY OF SUCH DAMAGE.
17496+ */
17497+#ifndef _FSL_DPIO_CMD_H
17498+#define _FSL_DPIO_CMD_H
17499+
17500+/* DPIO Version */
17501+#define DPIO_VER_MAJOR 3
17502+#define DPIO_VER_MINOR 2
17503+
17504+/* Command IDs */
17505+#define DPIO_CMDID_CLOSE 0x800
17506+#define DPIO_CMDID_OPEN 0x803
17507+#define DPIO_CMDID_CREATE 0x903
17508+#define DPIO_CMDID_DESTROY 0x900
17509+
17510+#define DPIO_CMDID_ENABLE 0x002
17511+#define DPIO_CMDID_DISABLE 0x003
17512+#define DPIO_CMDID_GET_ATTR 0x004
17513+#define DPIO_CMDID_RESET 0x005
17514+#define DPIO_CMDID_IS_ENABLED 0x006
17515+
17516+#define DPIO_CMDID_SET_IRQ 0x010
17517+#define DPIO_CMDID_GET_IRQ 0x011
17518+#define DPIO_CMDID_SET_IRQ_ENABLE 0x012
17519+#define DPIO_CMDID_GET_IRQ_ENABLE 0x013
17520+#define DPIO_CMDID_SET_IRQ_MASK 0x014
17521+#define DPIO_CMDID_GET_IRQ_MASK 0x015
17522+#define DPIO_CMDID_GET_IRQ_STATUS 0x016
17523+#define DPIO_CMDID_CLEAR_IRQ_STATUS 0x017
17524+
17525+#define DPIO_CMDID_SET_STASHING_DEST 0x120
17526+#define DPIO_CMDID_GET_STASHING_DEST 0x121
17527+#define DPIO_CMDID_ADD_STATIC_DEQUEUE_CHANNEL 0x122
17528+#define DPIO_CMDID_REMOVE_STATIC_DEQUEUE_CHANNEL 0x123
17529+
17530+/* cmd, param, offset, width, type, arg_name */
17531+#define DPIO_CMD_OPEN(cmd, dpio_id) \
17532+ MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id)
17533+
17534+/* cmd, param, offset, width, type, arg_name */
17535+#define DPIO_CMD_CREATE(cmd, cfg) \
17536+do { \
17537+ MC_CMD_OP(cmd, 0, 16, 2, enum dpio_channel_mode, \
17538+ cfg->channel_mode);\
17539+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->num_priorities);\
17540+} while (0)
17541+
17542+/* cmd, param, offset, width, type, arg_name */
17543+#define DPIO_RSP_IS_ENABLED(cmd, en) \
17544+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
17545+
17546+/* cmd, param, offset, width, type, arg_name */
17547+#define DPIO_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
17548+do { \
17549+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
17550+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
17551+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
17552+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
17553+} while (0)
17554+
17555+/* cmd, param, offset, width, type, arg_name */
17556+#define DPIO_CMD_GET_IRQ(cmd, irq_index) \
17557+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
17558+
17559+/* cmd, param, offset, width, type, arg_name */
17560+#define DPIO_RSP_GET_IRQ(cmd, type, irq_cfg) \
17561+do { \
17562+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
17563+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
17564+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
17565+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
17566+} while (0)
17567+
17568+/* cmd, param, offset, width, type, arg_name */
17569+#define DPIO_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \
17570+do { \
17571+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \
17572+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
17573+} while (0)
17574+
17575+/* cmd, param, offset, width, type, arg_name */
17576+#define DPIO_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
17577+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
17578+
17579+/* cmd, param, offset, width, type, arg_name */
17580+#define DPIO_RSP_GET_IRQ_ENABLE(cmd, en) \
17581+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en)
17582+
17583+/* cmd, param, offset, width, type, arg_name */
17584+#define DPIO_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
17585+do { \
17586+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
17587+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
17588+} while (0)
17589+
17590+/* cmd, param, offset, width, type, arg_name */
17591+#define DPIO_CMD_GET_IRQ_MASK(cmd, irq_index) \
17592+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
17593+
17594+/* cmd, param, offset, width, type, arg_name */
17595+#define DPIO_RSP_GET_IRQ_MASK(cmd, mask) \
17596+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
17597+
17598+/* cmd, param, offset, width, type, arg_name */
17599+#define DPIO_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
17600+do { \
17601+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
17602+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
17603+} while (0)
17604+
17605+/* cmd, param, offset, width, type, arg_name */
17606+#define DPIO_RSP_GET_IRQ_STATUS(cmd, status) \
17607+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
17608+
17609+/* cmd, param, offset, width, type, arg_name */
17610+#define DPIO_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
17611+do { \
17612+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
17613+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
17614+} while (0)
17615+
17616+/* cmd, param, offset, width, type, arg_name */
17617+#define DPIO_RSP_GET_ATTR(cmd, attr) \
17618+do { \
17619+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\
17620+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qbman_portal_id);\
17621+ MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->num_priorities);\
17622+ MC_RSP_OP(cmd, 0, 56, 4, enum dpio_channel_mode, attr->channel_mode);\
17623+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->qbman_portal_ce_offset);\
17624+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_offset);\
17625+ MC_RSP_OP(cmd, 3, 0, 16, uint16_t, attr->version.major);\
17626+ MC_RSP_OP(cmd, 3, 16, 16, uint16_t, attr->version.minor);\
17627+ MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\
17628+} while (0)
17629+
17630+/* cmd, param, offset, width, type, arg_name */
17631+#define DPIO_CMD_SET_STASHING_DEST(cmd, sdest) \
17632+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, sdest)
17633+
17634+/* cmd, param, offset, width, type, arg_name */
17635+#define DPIO_RSP_GET_STASHING_DEST(cmd, sdest) \
17636+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, sdest)
17637+
17638+/* cmd, param, offset, width, type, arg_name */
17639+#define DPIO_CMD_ADD_STATIC_DEQUEUE_CHANNEL(cmd, dpcon_id) \
17640+ MC_CMD_OP(cmd, 0, 0, 32, int, dpcon_id)
17641+
17642+/* cmd, param, offset, width, type, arg_name */
17643+#define DPIO_RSP_ADD_STATIC_DEQUEUE_CHANNEL(cmd, channel_index) \
17644+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, channel_index)
17645+
17646+/* cmd, param, offset, width, type, arg_name */
17647+#define DPIO_CMD_REMOVE_STATIC_DEQUEUE_CHANNEL(cmd, dpcon_id) \
17648+ MC_CMD_OP(cmd, 0, 0, 32, int, dpcon_id)
17649+#endif /* _FSL_DPIO_CMD_H */
17650diff --git a/drivers/net/dpaa2/mc/fsl_dpkg.h b/drivers/net/dpaa2/mc/fsl_dpkg.h
17651new file mode 100644
17652index 0000000..b2bceaf
17653--- /dev/null
17654+++ b/drivers/net/dpaa2/mc/fsl_dpkg.h
17655@@ -0,0 +1,174 @@
17656+/* Copyright 2013-2015 Freescale Semiconductor Inc.
17657+ *
17658+ * Redistribution and use in source and binary forms, with or without
17659+ * modification, are permitted provided that the following conditions are met:
17660+ * * Redistributions of source code must retain the above copyright
17661+ * notice, this list of conditions and the following disclaimer.
17662+ * * Redistributions in binary form must reproduce the above copyright
17663+ * notice, this list of conditions and the following disclaimer in the
17664+ * documentation and/or other materials provided with the distribution.
17665+ * * Neither the name of the above-listed copyright holders nor the
17666+ * names of any contributors may be used to endorse or promote products
17667+ * derived from this software without specific prior written permission.
17668+ *
17669+ *
17670+ * ALTERNATIVELY, this software may be distributed under the terms of the
17671+ * GNU General Public License ("GPL") as published by the Free Software
17672+ * Foundation, either version 2 of that License or (at your option) any
17673+ * later version.
17674+ *
17675+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17676+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17677+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17678+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
17679+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
17680+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
17681+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
17682+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
17683+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
17684+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
17685+ * POSSIBILITY OF SUCH DAMAGE.
17686+ */
17687+#ifndef __FSL_DPKG_H_
17688+#define __FSL_DPKG_H_
17689+
17690+#include <fsl_net.h>
17691+
17692+/* Data Path Key Generator API
17693+ * Contains initialization APIs and runtime APIs for the Key Generator
17694+ */
17695+
17696+/** Key Generator properties */
17697+
17698+/**
17699+ * Number of masks per key extraction
17700+ */
17701+#define DPKG_NUM_OF_MASKS 4
17702+/**
17703+ * Number of extractions per key profile
17704+ */
17705+#define DPKG_MAX_NUM_OF_EXTRACTS 10
17706+
17707+/**
17708+ * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
17709+ * @DPKG_FROM_HDR: Extract selected bytes from header, by offset
17710+ * @DPKG_FROM_FIELD: Extract selected bytes from header, by offset from field
17711+ * @DPKG_FULL_FIELD: Extract a full field
17712+ */
17713+enum dpkg_extract_from_hdr_type {
17714+ DPKG_FROM_HDR = 0,
17715+ DPKG_FROM_FIELD = 1,
17716+ DPKG_FULL_FIELD = 2
17717+};
17718+
17719+/**
17720+ * enum dpkg_extract_type - Enumeration for selecting extraction type
17721+ * @DPKG_EXTRACT_FROM_HDR: Extract from the header
17722+ * @DPKG_EXTRACT_FROM_DATA: Extract from data not in specific header
17723+ * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
17724+ * e.g. can be used to extract header existence;
17725+ * please refer to 'Parse Result definition' section in the parser BG
17726+ */
17727+enum dpkg_extract_type {
17728+ DPKG_EXTRACT_FROM_HDR = 0,
17729+ DPKG_EXTRACT_FROM_DATA = 1,
17730+ DPKG_EXTRACT_FROM_PARSE = 3
17731+};
17732+
17733+/**
17734+ * struct dpkg_mask - A structure for defining a single extraction mask
17735+ * @mask: Byte mask for the extracted content
17736+ * @offset: Offset within the extracted content
17737+ */
17738+struct dpkg_mask {
17739+ uint8_t mask;
17740+ uint8_t offset;
17741+};
17742+
17743+/**
17744+ * struct dpkg_extract - A structure for defining a single extraction
17745+ * @type: Determines how the union below is interpreted:
17746+ * DPKG_EXTRACT_FROM_HDR: selects 'from_hdr';
17747+ * DPKG_EXTRACT_FROM_DATA: selects 'from_data';
17748+ * DPKG_EXTRACT_FROM_PARSE: selects 'from_parse'
17749+ * @extract: Selects extraction method
17750+ * @num_of_byte_masks: Defines the number of valid entries in the array below;
17751+ * This is also the number of bytes to be used as masks
17752+ * @masks: Masks parameters
17753+ */
17754+struct dpkg_extract {
17755+ enum dpkg_extract_type type;
17756+ /**
17757+ * union extract - Selects extraction method
17758+ * @from_hdr - Used when 'type = DPKG_EXTRACT_FROM_HDR'
17759+ * @from_data - Used when 'type = DPKG_EXTRACT_FROM_DATA'
17760+ * @from_parse - Used when 'type = DPKG_EXTRACT_FROM_PARSE'
17761+ */
17762+ union {
17763+ /**
17764+ * struct from_hdr - Used when 'type = DPKG_EXTRACT_FROM_HDR'
17765+ * @prot: Any of the supported headers
17766+ * @type: Defines the type of header extraction:
17767+ * DPKG_FROM_HDR: use size & offset below;
17768+ * DPKG_FROM_FIELD: use field, size and offset below;
17769+ * DPKG_FULL_FIELD: use field below
17770+ * @field: One of the supported fields (NH_FLD_)
17771+ *
17772+ * @size: Size in bytes
17773+ * @offset: Byte offset
17774+ * @hdr_index: Clear for cases not listed below;
17775+ * Used for protocols that may have more than a single
17776+ * header, 0 indicates an outer header;
17777+ * Supported protocols (possible values):
17778+ * NET_PROT_VLAN (0, HDR_INDEX_LAST);
17779+ * NET_PROT_MPLS (0, 1, HDR_INDEX_LAST);
17780+ * NET_PROT_IP(0, HDR_INDEX_LAST);
17781+ * NET_PROT_IPv4(0, HDR_INDEX_LAST);
17782+ * NET_PROT_IPv6(0, HDR_INDEX_LAST);
17783+ */
17784+
17785+ struct {
17786+ enum net_prot prot;
17787+ enum dpkg_extract_from_hdr_type type;
17788+ uint32_t field;
17789+ uint8_t size;
17790+ uint8_t offset;
17791+ uint8_t hdr_index;
17792+ } from_hdr;
17793+ /**
17794+ * struct from_data - Used when 'type = DPKG_EXTRACT_FROM_DATA'
17795+ * @size: Size in bytes
17796+ * @offset: Byte offset
17797+ */
17798+ struct {
17799+ uint8_t size;
17800+ uint8_t offset;
17801+ } from_data;
17802+
17803+ /**
17804+ * struct from_parse - Used when 'type = DPKG_EXTRACT_FROM_PARSE'
17805+ * @size: Size in bytes
17806+ * @offset: Byte offset
17807+ */
17808+ struct {
17809+ uint8_t size;
17810+ uint8_t offset;
17811+ } from_parse;
17812+ } extract;
17813+
17814+ uint8_t num_of_byte_masks;
17815+ struct dpkg_mask masks[DPKG_NUM_OF_MASKS];
17816+};
17817+
17818+/**
17819+ * struct dpkg_profile_cfg - A structure for defining a full Key Generation
17820+ * profile (rule)
17821+ * @num_extracts: Defines the number of valid entries in the array below
17822+ * @extracts: Array of required extractions
17823+ */
17824+struct dpkg_profile_cfg {
17825+ uint8_t num_extracts;
17826+ struct dpkg_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS];
17827+};
17828+
17829+#endif /* __FSL_DPKG_H_ */
17830diff --git a/drivers/net/dpaa2/mc/fsl_dpmac.h b/drivers/net/dpaa2/mc/fsl_dpmac.h
17831new file mode 100644
17832index 0000000..ad27772
17833--- /dev/null
17834+++ b/drivers/net/dpaa2/mc/fsl_dpmac.h
17835@@ -0,0 +1,593 @@
17836+/* Copyright 2013-2015 Freescale Semiconductor Inc.
17837+ *
17838+ * Redistribution and use in source and binary forms, with or without
17839+ * modification, are permitted provided that the following conditions are met:
17840+ * * Redistributions of source code must retain the above copyright
17841+ * notice, this list of conditions and the following disclaimer.
17842+ * * Redistributions in binary form must reproduce the above copyright
17843+ * notice, this list of conditions and the following disclaimer in the
17844+ * documentation and/or other materials provided with the distribution.
17845+ * * Neither the name of the above-listed copyright holders nor the
17846+ * names of any contributors may be used to endorse or promote products
17847+ * derived from this software without specific prior written permission.
17848+ *
17849+ *
17850+ * ALTERNATIVELY, this software may be distributed under the terms of the
17851+ * GNU General Public License ("GPL") as published by the Free Software
17852+ * Foundation, either version 2 of that License or (at your option) any
17853+ * later version.
17854+ *
17855+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17856+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17857+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17858+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
17859+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
17860+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
17861+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
17862+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
17863+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
17864+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
17865+ * POSSIBILITY OF SUCH DAMAGE.
17866+ */
17867+#ifndef __FSL_DPMAC_H
17868+#define __FSL_DPMAC_H
17869+
17870+/* Data Path MAC API
17871+ * Contains initialization APIs and runtime control APIs for DPMAC
17872+ */
17873+
17874+struct fsl_mc_io;
17875+
17876+/**
17877+ * dpmac_open() - Open a control session for the specified object.
17878+ * @mc_io: Pointer to MC portal's I/O object
17879+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17880+ * @dpmac_id: DPMAC unique ID
17881+ * @token: Returned token; use in subsequent API calls
17882+ *
17883+ * This function can be used to open a control session for an
17884+ * already created object; an object may have been declared in
17885+ * the DPL or by calling the dpmac_create function.
17886+ * This function returns a unique authentication token,
17887+ * associated with the specific object ID and the specific MC
17888+ * portal; this token must be used in all subsequent commands for
17889+ * this specific object
17890+ *
17891+ * Return: '0' on Success; Error code otherwise.
17892+ */
17893+int dpmac_open(struct fsl_mc_io *mc_io,
17894+ uint32_t cmd_flags,
17895+ int dpmac_id,
17896+ uint16_t *token);
17897+
17898+/**
17899+ * dpmac_close() - Close the control session of the object
17900+ * @mc_io: Pointer to MC portal's I/O object
17901+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17902+ * @token: Token of DPMAC object
17903+ *
17904+ * After this function is called, no further operations are
17905+ * allowed on the object without opening a new control session.
17906+ *
17907+ * Return: '0' on Success; Error code otherwise.
17908+ */
17909+int dpmac_close(struct fsl_mc_io *mc_io,
17910+ uint32_t cmd_flags,
17911+ uint16_t token);
17912+
17913+/**
17914+ * enum dpmac_link_type - DPMAC link type
17915+ * @DPMAC_LINK_TYPE_NONE: No link
17916+ * @DPMAC_LINK_TYPE_FIXED: Link is fixed type
17917+ * @DPMAC_LINK_TYPE_PHY: Link by PHY ID
17918+ * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type
17919+ */
17920+enum dpmac_link_type {
17921+ DPMAC_LINK_TYPE_NONE,
17922+ DPMAC_LINK_TYPE_FIXED,
17923+ DPMAC_LINK_TYPE_PHY,
17924+ DPMAC_LINK_TYPE_BACKPLANE
17925+};
17926+
17927+/**
17928+ * enum dpmac_eth_if - DPMAC Ethrnet interface
17929+ * @DPMAC_ETH_IF_MII: MII interface
17930+ * @DPMAC_ETH_IF_RMII: RMII interface
17931+ * @DPMAC_ETH_IF_SMII: SMII interface
17932+ * @DPMAC_ETH_IF_GMII: GMII interface
17933+ * @DPMAC_ETH_IF_RGMII: RGMII interface
17934+ * @DPMAC_ETH_IF_SGMII: SGMII interface
17935+ * @DPMAC_ETH_IF_QSGMII: QSGMII interface
17936+ * @DPMAC_ETH_IF_XAUI: XAUI interface
17937+ * @DPMAC_ETH_IF_XFI: XFI interface
17938+ */
17939+enum dpmac_eth_if {
17940+ DPMAC_ETH_IF_MII,
17941+ DPMAC_ETH_IF_RMII,
17942+ DPMAC_ETH_IF_SMII,
17943+ DPMAC_ETH_IF_GMII,
17944+ DPMAC_ETH_IF_RGMII,
17945+ DPMAC_ETH_IF_SGMII,
17946+ DPMAC_ETH_IF_QSGMII,
17947+ DPMAC_ETH_IF_XAUI,
17948+ DPMAC_ETH_IF_XFI
17949+};
17950+
17951+/**
17952+ * struct dpmac_cfg - Structure representing DPMAC configuration
17953+ * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP,
17954+ * the MAC IDs are continuous.
17955+ * For example: 2 WRIOPs, 16 MACs in each:
17956+ * MAC IDs for the 1st WRIOP: 1-16,
17957+ * MAC IDs for the 2nd WRIOP: 17-32.
17958+ */
17959+struct dpmac_cfg {
17960+ int mac_id;
17961+};
17962+
17963+/**
17964+ * dpmac_create() - Create the DPMAC object.
17965+ * @mc_io: Pointer to MC portal's I/O object
17966+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17967+ * @cfg: Configuration structure
17968+ * @token: Returned token; use in subsequent API calls
17969+ *
17970+ * Create the DPMAC object, allocate required resources and
17971+ * perform required initialization.
17972+ *
17973+ * The object can be created either by declaring it in the
17974+ * DPL file, or by calling this function.
17975+ * This function returns a unique authentication token,
17976+ * associated with the specific object ID and the specific MC
17977+ * portal; this token must be used in all subsequent calls to
17978+ * this specific object. For objects that are created using the
17979+ * DPL file, call dpmac_open function to get an authentication
17980+ * token first.
17981+ *
17982+ * Return: '0' on Success; Error code otherwise.
17983+ */
17984+int dpmac_create(struct fsl_mc_io *mc_io,
17985+ uint32_t cmd_flags,
17986+ const struct dpmac_cfg *cfg,
17987+ uint16_t *token);
17988+
17989+/**
17990+ * dpmac_destroy() - Destroy the DPMAC object and release all its resources.
17991+ * @mc_io: Pointer to MC portal's I/O object
17992+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
17993+ * @token: Token of DPMAC object
17994+ *
17995+ * Return: '0' on Success; error code otherwise.
17996+ */
17997+int dpmac_destroy(struct fsl_mc_io *mc_io,
17998+ uint32_t cmd_flags,
17999+ uint16_t token);
18000+
18001+/**
18002+ * DPMAC IRQ Index and Events
18003+ */
18004+
18005+/**
18006+ * IRQ index
18007+ */
18008+#define DPMAC_IRQ_INDEX 0
18009+/**
18010+ * IRQ event - indicates a change in link state
18011+ */
18012+#define DPMAC_IRQ_EVENT_LINK_CFG_REQ 0x00000001
18013+/**
18014+ * IRQ event - Indicates that the link state changed
18015+ */
18016+#define DPMAC_IRQ_EVENT_LINK_CHANGED 0x00000002
18017+
18018+/**
18019+ * struct dpmac_irq_cfg - IRQ configuration
18020+ * @addr: Address that must be written to signal a message-based interrupt
18021+ * @val: Value to write into irq_addr address
18022+ * @irq_num: A user defined number associated with this IRQ
18023+ */
18024+struct dpmac_irq_cfg {
18025+ uint64_t addr;
18026+ uint32_t val;
18027+ int irq_num;
18028+};
18029+
18030+/**
18031+ * dpmac_set_irq() - Set IRQ information for the DPMAC to trigger an interrupt.
18032+ * @mc_io: Pointer to MC portal's I/O object
18033+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18034+ * @token: Token of DPMAC object
18035+ * @irq_index: Identifies the interrupt index to configure
18036+ * @irq_cfg: IRQ configuration
18037+ *
18038+ * Return: '0' on Success; Error code otherwise.
18039+ */
18040+int dpmac_set_irq(struct fsl_mc_io *mc_io,
18041+ uint32_t cmd_flags,
18042+ uint16_t token,
18043+ uint8_t irq_index,
18044+ struct dpmac_irq_cfg *irq_cfg);
18045+
18046+/**
18047+ * dpmac_get_irq() - Get IRQ information from the DPMAC.
18048+ * @mc_io: Pointer to MC portal's I/O object
18049+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18050+ * @token: Token of DPMAC object
18051+ * @irq_index: The interrupt index to configure
18052+ * @type: Interrupt type: 0 represents message interrupt
18053+ * type (both irq_addr and irq_val are valid)
18054+ * @irq_cfg: IRQ attributes
18055+ *
18056+ * Return: '0' on Success; Error code otherwise.
18057+ */
18058+int dpmac_get_irq(struct fsl_mc_io *mc_io,
18059+ uint32_t cmd_flags,
18060+ uint16_t token,
18061+ uint8_t irq_index,
18062+ int *type,
18063+ struct dpmac_irq_cfg *irq_cfg);
18064+
18065+/**
18066+ * dpmac_set_irq_enable() - Set overall interrupt state.
18067+ * @mc_io: Pointer to MC portal's I/O object
18068+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18069+ * @token: Token of DPMAC object
18070+ * @irq_index: The interrupt index to configure
18071+ * @en: Interrupt state - enable = 1, disable = 0
18072+ *
18073+ * Allows GPP software to control when interrupts are generated.
18074+ * Each interrupt can have up to 32 causes. The enable/disable control's the
18075+ * overall interrupt state. if the interrupt is disabled no causes will cause
18076+ * an interrupt.
18077+ *
18078+ * Return: '0' on Success; Error code otherwise.
18079+ */
18080+int dpmac_set_irq_enable(struct fsl_mc_io *mc_io,
18081+ uint32_t cmd_flags,
18082+ uint16_t token,
18083+ uint8_t irq_index,
18084+ uint8_t en);
18085+
18086+/**
18087+ * dpmac_get_irq_enable() - Get overall interrupt state
18088+ * @mc_io: Pointer to MC portal's I/O object
18089+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18090+ * @token: Token of DPMAC object
18091+ * @irq_index: The interrupt index to configure
18092+ * @en: Returned interrupt state - enable = 1, disable = 0
18093+ *
18094+ * Return: '0' on Success; Error code otherwise.
18095+ */
18096+int dpmac_get_irq_enable(struct fsl_mc_io *mc_io,
18097+ uint32_t cmd_flags,
18098+ uint16_t token,
18099+ uint8_t irq_index,
18100+ uint8_t *en);
18101+
18102+/**
18103+ * dpmac_set_irq_mask() - Set interrupt mask.
18104+ * @mc_io: Pointer to MC portal's I/O object
18105+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18106+ * @token: Token of DPMAC object
18107+ * @irq_index: The interrupt index to configure
18108+ * @mask: Event mask to trigger interrupt;
18109+ * each bit:
18110+ * 0 = ignore event
18111+ * 1 = consider event for asserting IRQ
18112+ *
18113+ * Every interrupt can have up to 32 causes and the interrupt model supports
18114+ * masking/unmasking each cause independently
18115+ *
18116+ * Return: '0' on Success; Error code otherwise.
18117+ */
18118+int dpmac_set_irq_mask(struct fsl_mc_io *mc_io,
18119+ uint32_t cmd_flags,
18120+ uint16_t token,
18121+ uint8_t irq_index,
18122+ uint32_t mask);
18123+
18124+/**
18125+ * dpmac_get_irq_mask() - Get interrupt mask.
18126+ * @mc_io: Pointer to MC portal's I/O object
18127+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18128+ * @token: Token of DPMAC object
18129+ * @irq_index: The interrupt index to configure
18130+ * @mask: Returned event mask to trigger interrupt
18131+ *
18132+ * Every interrupt can have up to 32 causes and the interrupt model supports
18133+ * masking/unmasking each cause independently
18134+ *
18135+ * Return: '0' on Success; Error code otherwise.
18136+ */
18137+int dpmac_get_irq_mask(struct fsl_mc_io *mc_io,
18138+ uint32_t cmd_flags,
18139+ uint16_t token,
18140+ uint8_t irq_index,
18141+ uint32_t *mask);
18142+
18143+/**
18144+ * dpmac_get_irq_status() - Get the current status of any pending interrupts.
18145+ *
18146+ * @mc_io: Pointer to MC portal's I/O object
18147+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18148+ * @token: Token of DPMAC object
18149+ * @irq_index: The interrupt index to configure
18150+ * @status: Returned interrupts status - one bit per cause:
18151+ * 0 = no interrupt pending
18152+ * 1 = interrupt pending
18153+ *
18154+ * Return: '0' on Success; Error code otherwise.
18155+ */
18156+int dpmac_get_irq_status(struct fsl_mc_io *mc_io,
18157+ uint32_t cmd_flags,
18158+ uint16_t token,
18159+ uint8_t irq_index,
18160+ uint32_t *status);
18161+
18162+/**
18163+ * dpmac_clear_irq_status() - Clear a pending interrupt's status
18164+ *
18165+ * @mc_io: Pointer to MC portal's I/O object
18166+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18167+ * @token: Token of DPMAC object
18168+ * @irq_index: The interrupt index to configure
18169+ * @status: Bits to clear (W1C) - one bit per cause:
18170+ * 0 = don't change
18171+ * 1 = clear status bit
18172+ *
18173+ * Return: '0' on Success; Error code otherwise.
18174+ */
18175+int dpmac_clear_irq_status(struct fsl_mc_io *mc_io,
18176+ uint32_t cmd_flags,
18177+ uint16_t token,
18178+ uint8_t irq_index,
18179+ uint32_t status);
18180+
18181+/**
18182+ * struct dpmac_attr - Structure representing DPMAC attributes
18183+ * @id: DPMAC object ID
18184+ * @phy_id: PHY ID
18185+ * @link_type: link type
18186+ * @eth_if: Ethernet interface
18187+ * @max_rate: Maximum supported rate - in Mbps
18188+ * @version: DPMAC version
18189+ */
18190+struct dpmac_attr {
18191+ int id;
18192+ int phy_id;
18193+ enum dpmac_link_type link_type;
18194+ enum dpmac_eth_if eth_if;
18195+ uint32_t max_rate;
18196+ /**
18197+ * struct version - Structure representing DPMAC version
18198+ * @major: DPMAC major version
18199+ * @minor: DPMAC minor version
18200+ */
18201+ struct {
18202+ uint16_t major;
18203+ uint16_t minor;
18204+ } version;
18205+};
18206+
18207+/**
18208+ * dpmac_get_attributes - Retrieve DPMAC attributes.
18209+ *
18210+ * @mc_io: Pointer to MC portal's I/O object
18211+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18212+ * @token: Token of DPMAC object
18213+ * @attr: Returned object's attributes
18214+ *
18215+ * Return: '0' on Success; Error code otherwise.
18216+ */
18217+int dpmac_get_attributes(struct fsl_mc_io *mc_io,
18218+ uint32_t cmd_flags,
18219+ uint16_t token,
18220+ struct dpmac_attr *attr);
18221+
18222+/**
18223+ * struct dpmac_mdio_cfg - DPMAC MDIO read/write parameters
18224+ * @phy_addr: MDIO device address
18225+ * @reg: Address of the register within the Clause 45 PHY device from which data
18226+ * is to be read
18227+ * @data: Data read/write from/to MDIO
18228+ */
18229+struct dpmac_mdio_cfg {
18230+ uint8_t phy_addr;
18231+ uint8_t reg;
18232+ uint16_t data;
18233+};
18234+
18235+/**
18236+ * dpmac_mdio_read() - Perform MDIO read transaction
18237+ * @mc_io: Pointer to opaque I/O object
18238+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18239+ * @token: Token of DPMAC object
18240+ * @cfg: Structure with MDIO transaction parameters
18241+ *
18242+ * Return: '0' on Success; Error code otherwise.
18243+ */
18244+int dpmac_mdio_read(struct fsl_mc_io *mc_io,
18245+ uint32_t cmd_flags,
18246+ uint16_t token,
18247+ struct dpmac_mdio_cfg *cfg);
18248+
18249+/**
18250+ * dpmac_mdio_write() - Perform MDIO write transaction
18251+ * @mc_io: Pointer to opaque I/O object
18252+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18253+ * @token: Token of DPMAC object
18254+ * @cfg: Structure with MDIO transaction parameters
18255+ *
18256+ * Return: '0' on Success; Error code otherwise.
18257+ */
18258+int dpmac_mdio_write(struct fsl_mc_io *mc_io,
18259+ uint32_t cmd_flags,
18260+ uint16_t token,
18261+ struct dpmac_mdio_cfg *cfg);
18262+
18263+/**
18264+ * DPMAC link configuration/state options
18265+ */
18266+
18267+/**
18268+ * Enable auto-negotiation
18269+ */
18270+#define DPMAC_LINK_OPT_AUTONEG 0x0000000000000001ULL
18271+/**
18272+ * Enable half-duplex mode
18273+ */
18274+#define DPMAC_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL
18275+/**
18276+ * Enable pause frames
18277+ */
18278+#define DPMAC_LINK_OPT_PAUSE 0x0000000000000004ULL
18279+/**
18280+ * Enable a-symmetric pause frames
18281+ */
18282+#define DPMAC_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL
18283+
18284+/**
18285+ * struct dpmac_link_cfg - Structure representing DPMAC link configuration
18286+ * @rate: Link's rate - in Mbps
18287+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
18288+ */
18289+struct dpmac_link_cfg {
18290+ uint32_t rate;
18291+ uint64_t options;
18292+};
18293+
18294+/**
18295+ * dpmac_get_link_cfg() - Get Ethernet link configuration
18296+ * @mc_io: Pointer to opaque I/O object
18297+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18298+ * @token: Token of DPMAC object
18299+ * @cfg: Returned structure with the link configuration
18300+ *
18301+ * Return: '0' on Success; Error code otherwise.
18302+ */
18303+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
18304+ uint32_t cmd_flags,
18305+ uint16_t token,
18306+ struct dpmac_link_cfg *cfg);
18307+
18308+/**
18309+ * struct dpmac_link_state - DPMAC link configuration request
18310+ * @rate: Rate in Mbps
18311+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
18312+ * @up: Link state
18313+ */
18314+struct dpmac_link_state {
18315+ uint32_t rate;
18316+ uint64_t options;
18317+ int up;
18318+};
18319+
18320+/**
18321+ * dpmac_set_link_state() - Set the Ethernet link status
18322+ * @mc_io: Pointer to opaque I/O object
18323+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18324+ * @token: Token of DPMAC object
18325+ * @link_state: Link state configuration
18326+ *
18327+ * Return: '0' on Success; Error code otherwise.
18328+ */
18329+int dpmac_set_link_state(struct fsl_mc_io *mc_io,
18330+ uint32_t cmd_flags,
18331+ uint16_t token,
18332+ struct dpmac_link_state *link_state);
18333+
18334+/**
18335+ * enum dpmac_counter - DPMAC counter types
18336+ * @DPMAC_CNT_ING_FRAME_64: counts 64-bytes frames, good or bad.
18337+ * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-bytes frames, good or bad.
18338+ * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-bytes frames, good or bad.
18339+ * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-bytes frames, good or bad.
18340+ * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-bytes frames, good or bad.
18341+ * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-bytes frames, good or bad.
18342+ * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-bytes frames and larger
18343+ * (up to max frame length specified),
18344+ * good or bad.
18345+ * @DPMAC_CNT_ING_FRAG: counts frames which are shorter than 64 bytes received
18346+ * with a wrong CRC
18347+ * @DPMAC_CNT_ING_JABBER: counts frames longer than the maximum frame length
18348+ * specified, with a bad frame check sequence.
18349+ * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped frames due to internal errors.
18350+ * Occurs when a receive FIFO overflows.
18351+ * Includes also frames truncated as a result of
18352+ * the receive FIFO overflow.
18353+ * @DPMAC_CNT_ING_ALIGN_ERR: counts frames with an alignment error
18354+ * (optional used for wrong SFD).
18355+ * @DPMAC_CNT_EGR_UNDERSIZED: counts frames transmitted that was less than 64
18356+ * bytes long with a good CRC.
18357+ * @DPMAC_CNT_ING_OVERSIZED: counts frames longer than the maximum frame length
18358+ * specified, with a good frame check sequence.
18359+ * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frames (regular and PFC)
18360+ * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frames transmitted
18361+ * (regular and PFC).
18362+ * @DPMAC_CNT_ING_BYTE: counts bytes received except preamble for all valid
18363+ * frames and valid pause frames.
18364+ * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frames.
18365+ * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frames.
18366+ * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad frames received.
18367+ * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frames.
18368+ * @DPMAC_CNT_ING_ERR_FRAME: counts frames received with an error
18369+ * (except for undersized/fragment frame).
18370+ * @DPMAC_CNT_EGR_BYTE: counts bytes transmitted except preamble for all valid
18371+ * frames and valid pause frames transmitted.
18372+ * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frames.
18373+ * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frames.
18374+ * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frames.
18375+ * @DPMAC_CNT_EGR_ERR_FRAME: counts frames transmitted with an error.
18376+ * @DPMAC_CNT_ING_GOOD_FRAME: counts frames received without error, including
18377+ * pause frames.
18378+ * @DPMAC_CNT_ENG_GOOD_FRAME: counts frames transmitted without error, including
18379+ * pause frames.
18380+ */
18381+enum dpmac_counter {
18382+ DPMAC_CNT_ING_FRAME_64,
18383+ DPMAC_CNT_ING_FRAME_127,
18384+ DPMAC_CNT_ING_FRAME_255,
18385+ DPMAC_CNT_ING_FRAME_511,
18386+ DPMAC_CNT_ING_FRAME_1023,
18387+ DPMAC_CNT_ING_FRAME_1518,
18388+ DPMAC_CNT_ING_FRAME_1519_MAX,
18389+ DPMAC_CNT_ING_FRAG,
18390+ DPMAC_CNT_ING_JABBER,
18391+ DPMAC_CNT_ING_FRAME_DISCARD,
18392+ DPMAC_CNT_ING_ALIGN_ERR,
18393+ DPMAC_CNT_EGR_UNDERSIZED,
18394+ DPMAC_CNT_ING_OVERSIZED,
18395+ DPMAC_CNT_ING_VALID_PAUSE_FRAME,
18396+ DPMAC_CNT_EGR_VALID_PAUSE_FRAME,
18397+ DPMAC_CNT_ING_BYTE,
18398+ DPMAC_CNT_ING_MCAST_FRAME,
18399+ DPMAC_CNT_ING_BCAST_FRAME,
18400+ DPMAC_CNT_ING_ALL_FRAME,
18401+ DPMAC_CNT_ING_UCAST_FRAME,
18402+ DPMAC_CNT_ING_ERR_FRAME,
18403+ DPMAC_CNT_EGR_BYTE,
18404+ DPMAC_CNT_EGR_MCAST_FRAME,
18405+ DPMAC_CNT_EGR_BCAST_FRAME,
18406+ DPMAC_CNT_EGR_UCAST_FRAME,
18407+ DPMAC_CNT_EGR_ERR_FRAME,
18408+ DPMAC_CNT_ING_GOOD_FRAME,
18409+ DPMAC_CNT_ENG_GOOD_FRAME
18410+};
18411+
18412+/**
18413+ * dpmac_get_counter() - Read a specific DPMAC counter
18414+ * @mc_io: Pointer to opaque I/O object
18415+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18416+ * @token: Token of DPMAC object
18417+ * @type: The requested counter
18418+ * @counter: Returned counter value
18419+ *
18420+ * Return: The requested counter; '0' otherwise.
18421+ */
18422+int dpmac_get_counter(struct fsl_mc_io *mc_io,
18423+ uint32_t cmd_flags,
18424+ uint16_t token,
18425+ enum dpmac_counter type,
18426+ uint64_t *counter);
18427+
18428+#endif /* __FSL_DPMAC_H */
18429diff --git a/drivers/net/dpaa2/mc/fsl_dpmac_cmd.h b/drivers/net/dpaa2/mc/fsl_dpmac_cmd.h
18430new file mode 100644
18431index 0000000..dc00590
18432--- /dev/null
18433+++ b/drivers/net/dpaa2/mc/fsl_dpmac_cmd.h
18434@@ -0,0 +1,195 @@
18435+/* Copyright 2013-2015 Freescale Semiconductor Inc.
18436+ *
18437+ * Redistribution and use in source and binary forms, with or without
18438+ * modification, are permitted provided that the following conditions are met:
18439+ * * Redistributions of source code must retain the above copyright
18440+ * notice, this list of conditions and the following disclaimer.
18441+ * * Redistributions in binary form must reproduce the above copyright
18442+ * notice, this list of conditions and the following disclaimer in the
18443+ * documentation and/or other materials provided with the distribution.
18444+ * * Neither the name of the above-listed copyright holders nor the
18445+ * names of any contributors may be used to endorse or promote products
18446+ * derived from this software without specific prior written permission.
18447+ *
18448+ *
18449+ * ALTERNATIVELY, this software may be distributed under the terms of the
18450+ * GNU General Public License ("GPL") as published by the Free Software
18451+ * Foundation, either version 2 of that License or (at your option) any
18452+ * later version.
18453+ *
18454+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18455+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18456+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18457+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
18458+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18459+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
18460+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
18461+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
18462+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
18463+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
18464+ * POSSIBILITY OF SUCH DAMAGE.
18465+ */
18466+#ifndef _FSL_DPMAC_CMD_H
18467+#define _FSL_DPMAC_CMD_H
18468+
18469+/* DPMAC Version */
18470+#define DPMAC_VER_MAJOR 3
18471+#define DPMAC_VER_MINOR 2
18472+
18473+/* Command IDs */
18474+#define DPMAC_CMDID_CLOSE 0x800
18475+#define DPMAC_CMDID_OPEN 0x80c
18476+#define DPMAC_CMDID_CREATE 0x90c
18477+#define DPMAC_CMDID_DESTROY 0x900
18478+
18479+#define DPMAC_CMDID_GET_ATTR 0x004
18480+#define DPMAC_CMDID_RESET 0x005
18481+
18482+#define DPMAC_CMDID_SET_IRQ 0x010
18483+#define DPMAC_CMDID_GET_IRQ 0x011
18484+#define DPMAC_CMDID_SET_IRQ_ENABLE 0x012
18485+#define DPMAC_CMDID_GET_IRQ_ENABLE 0x013
18486+#define DPMAC_CMDID_SET_IRQ_MASK 0x014
18487+#define DPMAC_CMDID_GET_IRQ_MASK 0x015
18488+#define DPMAC_CMDID_GET_IRQ_STATUS 0x016
18489+#define DPMAC_CMDID_CLEAR_IRQ_STATUS 0x017
18490+
18491+#define DPMAC_CMDID_MDIO_READ 0x0c0
18492+#define DPMAC_CMDID_MDIO_WRITE 0x0c1
18493+#define DPMAC_CMDID_GET_LINK_CFG 0x0c2
18494+#define DPMAC_CMDID_SET_LINK_STATE 0x0c3
18495+#define DPMAC_CMDID_GET_COUNTER 0x0c4
18496+
18497+/* cmd, param, offset, width, type, arg_name */
18498+#define DPMAC_CMD_CREATE(cmd, cfg) \
18499+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->mac_id)
18500+
18501+/* cmd, param, offset, width, type, arg_name */
18502+#define DPMAC_CMD_OPEN(cmd, dpmac_id) \
18503+ MC_CMD_OP(cmd, 0, 0, 32, int, dpmac_id)
18504+
18505+/* cmd, param, offset, width, type, arg_name */
18506+#define DPMAC_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
18507+do { \
18508+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
18509+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
18510+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
18511+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
18512+} while (0)
18513+
18514+/* cmd, param, offset, width, type, arg_name */
18515+#define DPMAC_CMD_GET_IRQ(cmd, irq_index) \
18516+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
18517+
18518+/* cmd, param, offset, width, type, arg_name */
18519+#define DPMAC_RSP_GET_IRQ(cmd, type, irq_cfg) \
18520+do { \
18521+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
18522+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
18523+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
18524+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
18525+} while (0)
18526+
18527+/* cmd, param, offset, width, type, arg_name */
18528+#define DPMAC_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \
18529+do { \
18530+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \
18531+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
18532+} while (0)
18533+
18534+/* cmd, param, offset, width, type, arg_name */
18535+#define DPMAC_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
18536+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
18537+
18538+/* cmd, param, offset, width, type, arg_name */
18539+#define DPMAC_RSP_GET_IRQ_ENABLE(cmd, en) \
18540+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en)
18541+
18542+/* cmd, param, offset, width, type, arg_name */
18543+#define DPMAC_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
18544+do { \
18545+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask);\
18546+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
18547+} while (0)
18548+
18549+/* cmd, param, offset, width, type, arg_name */
18550+#define DPMAC_CMD_GET_IRQ_MASK(cmd, irq_index) \
18551+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
18552+
18553+/* cmd, param, offset, width, type, arg_name */
18554+#define DPMAC_RSP_GET_IRQ_MASK(cmd, mask) \
18555+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
18556+
18557+/* cmd, param, offset, width, type, arg_name */
18558+#define DPMAC_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
18559+do { \
18560+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
18561+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
18562+} while (0)
18563+
18564+/* cmd, param, offset, width, type, arg_name */
18565+#define DPMAC_RSP_GET_IRQ_STATUS(cmd, status) \
18566+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
18567+
18568+/* cmd, param, offset, width, type, arg_name */
18569+#define DPMAC_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
18570+do { \
18571+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
18572+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
18573+} while (0)
18574+
18575+/* cmd, param, offset, width, type, arg_name */
18576+#define DPMAC_RSP_GET_ATTRIBUTES(cmd, attr) \
18577+do { \
18578+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\
18579+ MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\
18580+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
18581+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
18582+ MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\
18583+ MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\
18584+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\
18585+} while (0)
18586+
18587+/* cmd, param, offset, width, type, arg_name */
18588+#define DPMAC_CMD_MDIO_READ(cmd, cfg) \
18589+do { \
18590+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \
18591+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \
18592+} while (0)
18593+
18594+/* cmd, param, offset, width, type, arg_name */
18595+#define DPMAC_RSP_MDIO_READ(cmd, data) \
18596+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, data)
18597+
18598+/* cmd, param, offset, width, type, arg_name */
18599+#define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \
18600+do { \
18601+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \
18602+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \
18603+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \
18604+} while (0)
18605+
18606+/* cmd, param, offset, width, type, arg_name */
18607+#define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \
18608+do { \
18609+ MC_RSP_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \
18610+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \
18611+} while (0)
18612+
18613+/* cmd, param, offset, width, type, arg_name */
18614+#define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \
18615+do { \
18616+ MC_CMD_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \
18617+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \
18618+ MC_CMD_OP(cmd, 2, 0, 1, int, cfg->up); \
18619+} while (0)
18620+
18621+/* cmd, param, offset, width, type, arg_name */
18622+#define DPMAC_CMD_GET_COUNTER(cmd, type) \
18623+ MC_CMD_OP(cmd, 0, 0, 8, enum dpmac_counter, type)
18624+
18625+/* cmd, param, offset, width, type, arg_name */
18626+#define DPMAC_RSP_GET_COUNTER(cmd, counter) \
18627+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter)
18628+
18629+#endif /* _FSL_DPMAC_CMD_H */
18630diff --git a/drivers/net/dpaa2/mc/fsl_dpmcp.h b/drivers/net/dpaa2/mc/fsl_dpmcp.h
18631new file mode 100644
18632index 0000000..80f238e
18633--- /dev/null
18634+++ b/drivers/net/dpaa2/mc/fsl_dpmcp.h
18635@@ -0,0 +1,332 @@
18636+/* Copyright 2013-2015 Freescale Semiconductor Inc.
18637+ *
18638+ * Redistribution and use in source and binary forms, with or without
18639+ * modification, are permitted provided that the following conditions are met:
18640+ * * Redistributions of source code must retain the above copyright
18641+ * notice, this list of conditions and the following disclaimer.
18642+ * * Redistributions in binary form must reproduce the above copyright
18643+ * notice, this list of conditions and the following disclaimer in the
18644+ * documentation and/or other materials provided with the distribution.
18645+ * * Neither the name of the above-listed copyright holders nor the
18646+ * names of any contributors may be used to endorse or promote products
18647+ * derived from this software without specific prior written permission.
18648+ *
18649+ *
18650+ * ALTERNATIVELY, this software may be distributed under the terms of the
18651+ * GNU General Public License ("GPL") as published by the Free Software
18652+ * Foundation, either version 2 of that License or (at your option) any
18653+ * later version.
18654+ *
18655+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18656+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18657+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18658+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
18659+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18660+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
18661+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
18662+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
18663+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
18664+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
18665+ * POSSIBILITY OF SUCH DAMAGE.
18666+ */
18667+#ifndef __FSL_DPMCP_H
18668+#define __FSL_DPMCP_H
18669+
18670+/* Data Path Management Command Portal API
18671+ * Contains initialization APIs and runtime control APIs for DPMCP
18672+ */
18673+
18674+struct fsl_mc_io;
18675+
18676+/**
18677+ * dpmcp_open() - Open a control session for the specified object.
18678+ * @mc_io: Pointer to MC portal's I/O object
18679+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18680+ * @dpmcp_id: DPMCP unique ID
18681+ * @token: Returned token; use in subsequent API calls
18682+ *
18683+ * This function can be used to open a control session for an
18684+ * already created object; an object may have been declared in
18685+ * the DPL or by calling the dpmcp_create function.
18686+ * This function returns a unique authentication token,
18687+ * associated with the specific object ID and the specific MC
18688+ * portal; this token must be used in all subsequent commands for
18689+ * this specific object
18690+ *
18691+ * Return: '0' on Success; Error code otherwise.
18692+ */
18693+int dpmcp_open(struct fsl_mc_io *mc_io,
18694+ uint32_t cmd_flags,
18695+ int dpmcp_id,
18696+ uint16_t *token);
18697+
18698+/**
18699+ * Get portal ID from pool
18700+ */
18701+#define DPMCP_GET_PORTAL_ID_FROM_POOL (-1)
18702+
18703+/**
18704+ * dpmcp_close() - Close the control session of the object
18705+ * @mc_io: Pointer to MC portal's I/O object
18706+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18707+ * @token: Token of DPMCP object
18708+ *
18709+ * After this function is called, no further operations are
18710+ * allowed on the object without opening a new control session.
18711+ *
18712+ * Return: '0' on Success; Error code otherwise.
18713+ */
18714+int dpmcp_close(struct fsl_mc_io *mc_io,
18715+ uint32_t cmd_flags,
18716+ uint16_t token);
18717+
18718+/**
18719+ * struct dpmcp_cfg - Structure representing DPMCP configuration
18720+ * @portal_id: Portal ID; 'DPMCP_GET_PORTAL_ID_FROM_POOL' to get the portal ID
18721+ * from pool
18722+ */
18723+struct dpmcp_cfg {
18724+ int portal_id;
18725+};
18726+
18727+/**
18728+ * dpmcp_create() - Create the DPMCP object.
18729+ * @mc_io: Pointer to MC portal's I/O object
18730+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18731+ * @cfg: Configuration structure
18732+ * @token: Returned token; use in subsequent API calls
18733+ *
18734+ * Create the DPMCP object, allocate required resources and
18735+ * perform required initialization.
18736+ *
18737+ * The object can be created either by declaring it in the
18738+ * DPL file, or by calling this function.
18739+ * This function returns a unique authentication token,
18740+ * associated with the specific object ID and the specific MC
18741+ * portal; this token must be used in all subsequent calls to
18742+ * this specific object. For objects that are created using the
18743+ * DPL file, call dpmcp_open function to get an authentication
18744+ * token first.
18745+ *
18746+ * Return: '0' on Success; Error code otherwise.
18747+ */
18748+int dpmcp_create(struct fsl_mc_io *mc_io,
18749+ uint32_t cmd_flags,
18750+ const struct dpmcp_cfg *cfg,
18751+ uint16_t *token);
18752+
18753+/**
18754+ * dpmcp_destroy() - Destroy the DPMCP object and release all its resources.
18755+ * @mc_io: Pointer to MC portal's I/O object
18756+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18757+ * @token: Token of DPMCP object
18758+ *
18759+ * Return: '0' on Success; error code otherwise.
18760+ */
18761+int dpmcp_destroy(struct fsl_mc_io *mc_io,
18762+ uint32_t cmd_flags,
18763+ uint16_t token);
18764+
18765+/**
18766+ * dpmcp_reset() - Reset the DPMCP, returns the object to initial state.
18767+ * @mc_io: Pointer to MC portal's I/O object
18768+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18769+ * @token: Token of DPMCP object
18770+ *
18771+ * Return: '0' on Success; Error code otherwise.
18772+ */
18773+int dpmcp_reset(struct fsl_mc_io *mc_io,
18774+ uint32_t cmd_flags,
18775+ uint16_t token);
18776+
18777+/**
18778+ * IRQ
18779+ */
18780+
18781+/**
18782+ * IRQ Index
18783+ */
18784+#define DPMCP_IRQ_INDEX 0
18785+/**
18786+ * irq event - Indicates that the link state changed
18787+ */
18788+#define DPMCP_IRQ_EVENT_CMD_DONE 0x00000001
18789+
18790+/**
18791+ * struct dpmcp_irq_cfg - IRQ configuration
18792+ * @addr: Address that must be written to signal a message-based interrupt
18793+ * @val: Value to write into irq_addr address
18794+ * @irq_num: A user defined number associated with this IRQ
18795+ */
18796+struct dpmcp_irq_cfg {
18797+ uint64_t addr;
18798+ uint32_t val;
18799+ int irq_num;
18800+};
18801+
18802+/**
18803+ * dpmcp_set_irq() - Set IRQ information for the DPMCP to trigger an interrupt.
18804+ * @mc_io: Pointer to MC portal's I/O object
18805+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18806+ * @token: Token of DPMCP object
18807+ * @irq_index: Identifies the interrupt index to configure
18808+ * @irq_cfg: IRQ configuration
18809+ *
18810+ * Return: '0' on Success; Error code otherwise.
18811+ */
18812+int dpmcp_set_irq(struct fsl_mc_io *mc_io,
18813+ uint32_t cmd_flags,
18814+ uint16_t token,
18815+ uint8_t irq_index,
18816+ struct dpmcp_irq_cfg *irq_cfg);
18817+
18818+/**
18819+ * dpmcp_get_irq() - Get IRQ information from the DPMCP.
18820+ * @mc_io: Pointer to MC portal's I/O object
18821+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18822+ * @token: Token of DPMCP object
18823+ * @irq_index: The interrupt index to configure
18824+ * @type: Interrupt type: 0 represents message interrupt
18825+ * type (both irq_addr and irq_val are valid)
18826+ * @irq_cfg: IRQ attributes
18827+ *
18828+ * Return: '0' on Success; Error code otherwise.
18829+ */
18830+int dpmcp_get_irq(struct fsl_mc_io *mc_io,
18831+ uint32_t cmd_flags,
18832+ uint16_t token,
18833+ uint8_t irq_index,
18834+ int *type,
18835+ struct dpmcp_irq_cfg *irq_cfg);
18836+
18837+/**
18838+ * dpmcp_set_irq_enable() - Set overall interrupt state.
18839+ * @mc_io: Pointer to MC portal's I/O object
18840+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18841+ * @token: Token of DPMCP object
18842+ * @irq_index: The interrupt index to configure
18843+ * @en: Interrupt state - enable = 1, disable = 0
18844+ *
18845+ * Allows GPP software to control when interrupts are generated.
18846+ * Each interrupt can have up to 32 causes. The enable/disable control's the
18847+ * overall interrupt state. if the interrupt is disabled no causes will cause
18848+ * an interrupt.
18849+ *
18850+ * Return: '0' on Success; Error code otherwise.
18851+ */
18852+int dpmcp_set_irq_enable(struct fsl_mc_io *mc_io,
18853+ uint32_t cmd_flags,
18854+ uint16_t token,
18855+ uint8_t irq_index,
18856+ uint8_t en);
18857+
18858+/**
18859+ * dpmcp_get_irq_enable() - Get overall interrupt state
18860+ * @mc_io: Pointer to MC portal's I/O object
18861+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18862+ * @token: Token of DPMCP object
18863+ * @irq_index: The interrupt index to configure
18864+ * @en: Returned interrupt state - enable = 1, disable = 0
18865+ *
18866+ * Return: '0' on Success; Error code otherwise.
18867+ */
18868+int dpmcp_get_irq_enable(struct fsl_mc_io *mc_io,
18869+ uint32_t cmd_flags,
18870+ uint16_t token,
18871+ uint8_t irq_index,
18872+ uint8_t *en);
18873+
18874+/**
18875+ * dpmcp_set_irq_mask() - Set interrupt mask.
18876+ * @mc_io: Pointer to MC portal's I/O object
18877+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18878+ * @token: Token of DPMCP object
18879+ * @irq_index: The interrupt index to configure
18880+ * @mask: Event mask to trigger interrupt;
18881+ * each bit:
18882+ * 0 = ignore event
18883+ * 1 = consider event for asserting IRQ
18884+ *
18885+ * Every interrupt can have up to 32 causes and the interrupt model supports
18886+ * masking/unmasking each cause independently
18887+ *
18888+ * Return: '0' on Success; Error code otherwise.
18889+ */
18890+int dpmcp_set_irq_mask(struct fsl_mc_io *mc_io,
18891+ uint32_t cmd_flags,
18892+ uint16_t token,
18893+ uint8_t irq_index,
18894+ uint32_t mask);
18895+
18896+/**
18897+ * dpmcp_get_irq_mask() - Get interrupt mask.
18898+ * @mc_io: Pointer to MC portal's I/O object
18899+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18900+ * @token: Token of DPMCP object
18901+ * @irq_index: The interrupt index to configure
18902+ * @mask: Returned event mask to trigger interrupt
18903+ *
18904+ * Every interrupt can have up to 32 causes and the interrupt model supports
18905+ * masking/unmasking each cause independently
18906+ *
18907+ * Return: '0' on Success; Error code otherwise.
18908+ */
18909+int dpmcp_get_irq_mask(struct fsl_mc_io *mc_io,
18910+ uint32_t cmd_flags,
18911+ uint16_t token,
18912+ uint8_t irq_index,
18913+ uint32_t *mask);
18914+
18915+/**
18916+ * dpmcp_get_irq_status() - Get the current status of any pending interrupts.
18917+ *
18918+ * @mc_io: Pointer to MC portal's I/O object
18919+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18920+ * @token: Token of DPMCP object
18921+ * @irq_index: The interrupt index to configure
18922+ * @status: Returned interrupts status - one bit per cause:
18923+ * 0 = no interrupt pending
18924+ * 1 = interrupt pending
18925+ *
18926+ * Return: '0' on Success; Error code otherwise.
18927+ */
18928+int dpmcp_get_irq_status(struct fsl_mc_io *mc_io,
18929+ uint32_t cmd_flags,
18930+ uint16_t token,
18931+ uint8_t irq_index,
18932+ uint32_t *status);
18933+
18934+/**
18935+ * struct dpmcp_attr - Structure representing DPMCP attributes
18936+ * @id: DPMCP object ID
18937+ * @version: DPMCP version
18938+ */
18939+struct dpmcp_attr {
18940+ int id;
18941+ /**
18942+ * struct version - Structure representing DPMCP version
18943+ * @major: DPMCP major version
18944+ * @minor: DPMCP minor version
18945+ */
18946+ struct {
18947+ uint16_t major;
18948+ uint16_t minor;
18949+ } version;
18950+};
18951+
18952+/**
18953+ * dpmcp_get_attributes - Retrieve DPMCP attributes.
18954+ *
18955+ * @mc_io: Pointer to MC portal's I/O object
18956+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
18957+ * @token: Token of DPMCP object
18958+ * @attr: Returned object's attributes
18959+ *
18960+ * Return: '0' on Success; Error code otherwise.
18961+ */
18962+int dpmcp_get_attributes(struct fsl_mc_io *mc_io,
18963+ uint32_t cmd_flags,
18964+ uint16_t token,
18965+ struct dpmcp_attr *attr);
18966+
18967+#endif /* __FSL_DPMCP_H */
18968diff --git a/drivers/net/dpaa2/mc/fsl_dpmcp_cmd.h b/drivers/net/dpaa2/mc/fsl_dpmcp_cmd.h
18969new file mode 100644
18970index 0000000..8f710bd
18971--- /dev/null
18972+++ b/drivers/net/dpaa2/mc/fsl_dpmcp_cmd.h
18973@@ -0,0 +1,135 @@
18974+/* Copyright 2013-2015 Freescale Semiconductor Inc.
18975+ *
18976+ * Redistribution and use in source and binary forms, with or without
18977+ * modification, are permitted provided that the following conditions are met:
18978+ * * Redistributions of source code must retain the above copyright
18979+ * notice, this list of conditions and the following disclaimer.
18980+ * * Redistributions in binary form must reproduce the above copyright
18981+ * notice, this list of conditions and the following disclaimer in the
18982+ * documentation and/or other materials provided with the distribution.
18983+ * * Neither the name of the above-listed copyright holders nor the
18984+ * names of any contributors may be used to endorse or promote products
18985+ * derived from this software without specific prior written permission.
18986+ *
18987+ *
18988+ * ALTERNATIVELY, this software may be distributed under the terms of the
18989+ * GNU General Public License ("GPL") as published by the Free Software
18990+ * Foundation, either version 2 of that License or (at your option) any
18991+ * later version.
18992+ *
18993+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18994+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18995+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18996+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
18997+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18998+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
18999+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
19000+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
19001+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19002+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
19003+ * POSSIBILITY OF SUCH DAMAGE.
19004+ */
19005+#ifndef _FSL_DPMCP_CMD_H
19006+#define _FSL_DPMCP_CMD_H
19007+
19008+/* DPMCP Version */
19009+#define DPMCP_VER_MAJOR 3
19010+#define DPMCP_VER_MINOR 0
19011+
19012+/* Command IDs */
19013+#define DPMCP_CMDID_CLOSE 0x800
19014+#define DPMCP_CMDID_OPEN 0x80b
19015+#define DPMCP_CMDID_CREATE 0x90b
19016+#define DPMCP_CMDID_DESTROY 0x900
19017+
19018+#define DPMCP_CMDID_GET_ATTR 0x004
19019+#define DPMCP_CMDID_RESET 0x005
19020+
19021+#define DPMCP_CMDID_SET_IRQ 0x010
19022+#define DPMCP_CMDID_GET_IRQ 0x011
19023+#define DPMCP_CMDID_SET_IRQ_ENABLE 0x012
19024+#define DPMCP_CMDID_GET_IRQ_ENABLE 0x013
19025+#define DPMCP_CMDID_SET_IRQ_MASK 0x014
19026+#define DPMCP_CMDID_GET_IRQ_MASK 0x015
19027+#define DPMCP_CMDID_GET_IRQ_STATUS 0x016
19028+
19029+/* cmd, param, offset, width, type, arg_name */
19030+#define DPMCP_CMD_OPEN(cmd, dpmcp_id) \
19031+ MC_CMD_OP(cmd, 0, 0, 32, int, dpmcp_id)
19032+
19033+/* cmd, param, offset, width, type, arg_name */
19034+#define DPMCP_CMD_CREATE(cmd, cfg) \
19035+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->portal_id)
19036+
19037+/* cmd, param, offset, width, type, arg_name */
19038+#define DPMCP_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
19039+do { \
19040+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
19041+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
19042+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
19043+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
19044+} while (0)
19045+
19046+/* cmd, param, offset, width, type, arg_name */
19047+#define DPMCP_CMD_GET_IRQ(cmd, irq_index) \
19048+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
19049+
19050+/* cmd, param, offset, width, type, arg_name */
19051+#define DPMCP_RSP_GET_IRQ(cmd, type, irq_cfg) \
19052+do { \
19053+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
19054+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
19055+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
19056+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
19057+} while (0)
19058+
19059+/* cmd, param, offset, width, type, arg_name */
19060+#define DPMCP_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \
19061+do { \
19062+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \
19063+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
19064+} while (0)
19065+
19066+/* cmd, param, offset, width, type, arg_name */
19067+#define DPMCP_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
19068+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
19069+
19070+/* cmd, param, offset, width, type, arg_name */
19071+#define DPMCP_RSP_GET_IRQ_ENABLE(cmd, en) \
19072+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en)
19073+
19074+/* cmd, param, offset, width, type, arg_name */
19075+#define DPMCP_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
19076+do { \
19077+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask);\
19078+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
19079+} while (0)
19080+
19081+/* cmd, param, offset, width, type, arg_name */
19082+#define DPMCP_CMD_GET_IRQ_MASK(cmd, irq_index) \
19083+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
19084+
19085+/* cmd, param, offset, width, type, arg_name */
19086+#define DPMCP_RSP_GET_IRQ_MASK(cmd, mask) \
19087+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
19088+
19089+/* cmd, param, offset, width, type, arg_name */
19090+#define DPMCP_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
19091+do { \
19092+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
19093+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
19094+} while (0)
19095+
19096+/* cmd, param, offset, width, type, arg_name */
19097+#define DPMCP_RSP_GET_IRQ_STATUS(cmd, status) \
19098+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
19099+
19100+/* cmd, param, offset, width, type, arg_name */
19101+#define DPMCP_RSP_GET_ATTRIBUTES(cmd, attr) \
19102+do { \
19103+ MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\
19104+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
19105+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
19106+} while (0)
19107+
19108+#endif /* _FSL_DPMCP_CMD_H */
19109diff --git a/drivers/net/dpaa2/mc/fsl_dpmng.h b/drivers/net/dpaa2/mc/fsl_dpmng.h
19110new file mode 100644
19111index 0000000..4468dea
19112--- /dev/null
19113+++ b/drivers/net/dpaa2/mc/fsl_dpmng.h
19114@@ -0,0 +1,74 @@
19115+/* Copyright 2013-2015 Freescale Semiconductor Inc.
19116+ *
19117+ * Redistribution and use in source and binary forms, with or without
19118+ * modification, are permitted provided that the following conditions are met:
19119+ * * Redistributions of source code must retain the above copyright
19120+ * notice, this list of conditions and the following disclaimer.
19121+ * * Redistributions in binary form must reproduce the above copyright
19122+ * notice, this list of conditions and the following disclaimer in the
19123+ * documentation and/or other materials provided with the distribution.
19124+ * * Neither the name of the above-listed copyright holders nor the
19125+ * names of any contributors may be used to endorse or promote products
19126+ * derived from this software without specific prior written permission.
19127+ *
19128+ *
19129+ * ALTERNATIVELY, this software may be distributed under the terms of the
19130+ * GNU General Public License ("GPL") as published by the Free Software
19131+ * Foundation, either version 2 of that License or (at your option) any
19132+ * later version.
19133+ *
19134+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19135+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19136+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19137+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
19138+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19139+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19140+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
19141+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
19142+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19143+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
19144+ * POSSIBILITY OF SUCH DAMAGE.
19145+ */
19146+#ifndef __FSL_DPMNG_H
19147+#define __FSL_DPMNG_H
19148+
19149+/* Management Complex General API
19150+ * Contains general API for the Management Complex firmware
19151+ */
19152+
19153+struct fsl_mc_io;
19154+
19155+/**
19156+ * Management Complex firmware version information
19157+ */
19158+#define MC_VER_MAJOR 9
19159+#define MC_VER_MINOR 0
19160+
19161+/**
19162+ * struct mc_versoin
19163+ * @major: Major version number: incremented on API compatibility changes
19164+ * @minor: Minor version number: incremented on API additions (that are
19165+ * backward compatible); reset when major version is incremented
19166+ * @revision: Internal revision number: incremented on implementation changes
19167+ * and/or bug fixes that have no impact on API
19168+ */
19169+struct mc_version {
19170+ uint32_t major;
19171+ uint32_t minor;
19172+ uint32_t revision;
19173+};
19174+
19175+/**
19176+ * mc_get_version() - Retrieves the Management Complex firmware
19177+ * version information
19178+ * @mc_io: Pointer to opaque I/O object
19179+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19180+ * @mc_ver_info: Returned version information structure
19181+ *
19182+ * Return: '0' on Success; Error code otherwise.
19183+ */
19184+int mc_get_version(struct fsl_mc_io *mc_io,
19185+ uint32_t cmd_flags,
19186+ struct mc_version *mc_ver_info);
19187+
19188+#endif /* __FSL_DPMNG_H */
19189diff --git a/drivers/net/dpaa2/mc/fsl_dpmng_cmd.h b/drivers/net/dpaa2/mc/fsl_dpmng_cmd.h
19190new file mode 100644
19191index 0000000..c34ca3a
19192--- /dev/null
19193+++ b/drivers/net/dpaa2/mc/fsl_dpmng_cmd.h
19194@@ -0,0 +1,46 @@
19195+/* Copyright 2013-2015 Freescale Semiconductor Inc.
19196+ *
19197+ * Redistribution and use in source and binary forms, with or without
19198+ * modification, are permitted provided that the following conditions are met:
19199+ * * Redistributions of source code must retain the above copyright
19200+ * notice, this list of conditions and the following disclaimer.
19201+ * * Redistributions in binary form must reproduce the above copyright
19202+ * notice, this list of conditions and the following disclaimer in the
19203+ * documentation and/or other materials provided with the distribution.
19204+ * * Neither the name of the above-listed copyright holders nor the
19205+ * names of any contributors may be used to endorse or promote products
19206+ * derived from this software without specific prior written permission.
19207+ *
19208+ *
19209+ * ALTERNATIVELY, this software may be distributed under the terms of the
19210+ * GNU General Public License ("GPL") as published by the Free Software
19211+ * Foundation, either version 2 of that License or (at your option) any
19212+ * later version.
19213+ *
19214+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19215+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19216+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19217+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
19218+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19219+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19220+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
19221+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
19222+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19223+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
19224+ * POSSIBILITY OF SUCH DAMAGE.
19225+ */
19226+#ifndef __FSL_DPMNG_CMD_H
19227+#define __FSL_DPMNG_CMD_H
19228+
19229+/* Command IDs */
19230+#define DPMNG_CMDID_GET_VERSION 0x831
19231+
19232+/* cmd, param, offset, width, type, arg_name */
19233+#define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \
19234+do { \
19235+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mc_ver_info->revision); \
19236+ MC_RSP_OP(cmd, 0, 32, 32, uint32_t, mc_ver_info->major); \
19237+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, mc_ver_info->minor); \
19238+} while (0)
19239+
19240+#endif /* __FSL_DPMNG_CMD_H */
19241diff --git a/drivers/net/dpaa2/mc/fsl_dpni.h b/drivers/net/dpaa2/mc/fsl_dpni.h
19242new file mode 100644
19243index 0000000..c820086
19244--- /dev/null
19245+++ b/drivers/net/dpaa2/mc/fsl_dpni.h
19246@@ -0,0 +1,2581 @@
19247+/* Copyright 2013-2015 Freescale Semiconductor Inc.
19248+ *
19249+ * Redistribution and use in source and binary forms, with or without
19250+ * modification, are permitted provided that the following conditions are met:
19251+ * * Redistributions of source code must retain the above copyright
19252+ * notice, this list of conditions and the following disclaimer.
19253+ * * Redistributions in binary form must reproduce the above copyright
19254+ * notice, this list of conditions and the following disclaimer in the
19255+ * documentation and/or other materials provided with the distribution.
19256+ * * Neither the name of the above-listed copyright holders nor the
19257+ * names of any contributors may be used to endorse or promote products
19258+ * derived from this software without specific prior written permission.
19259+ *
19260+ *
19261+ * ALTERNATIVELY, this software may be distributed under the terms of the
19262+ * GNU General Public License ("GPL") as published by the Free Software
19263+ * Foundation, either version 2 of that License or (at your option) any
19264+ * later version.
19265+ *
19266+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19267+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19268+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19269+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
19270+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19271+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19272+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
19273+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
19274+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19275+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
19276+ * POSSIBILITY OF SUCH DAMAGE.
19277+ */
19278+#ifndef __FSL_DPNI_H
19279+#define __FSL_DPNI_H
19280+
19281+#include <fsl_dpkg.h>
19282+
19283+struct fsl_mc_io;
19284+
19285+/**
19286+ * Data Path Network Interface API
19287+ * Contains initialization APIs and runtime control APIs for DPNI
19288+ */
19289+
19290+/** General DPNI macros */
19291+
19292+/**
19293+ * Maximum number of traffic classes
19294+ */
19295+#define DPNI_MAX_TC 8
19296+/**
19297+ * Maximum number of buffer pools per DPNI
19298+ */
19299+#define DPNI_MAX_DPBP 8
19300+/**
19301+ * Maximum number of storage-profiles per DPNI
19302+ */
19303+#define DPNI_MAX_SP 2
19304+
19305+/**
19306+ * All traffic classes considered; see dpni_set_rx_flow()
19307+ */
19308+#define DPNI_ALL_TCS (uint8_t)(-1)
19309+/**
19310+ * All flows within traffic class considered; see dpni_set_rx_flow()
19311+ */
19312+#define DPNI_ALL_TC_FLOWS (uint16_t)(-1)
19313+/**
19314+ * Generate new flow ID; see dpni_set_tx_flow()
19315+ */
19316+#define DPNI_NEW_FLOW_ID (uint16_t)(-1)
19317+/* use for common tx-conf queue; see dpni_set_tx_conf_<x>() */
19318+#define DPNI_COMMON_TX_CONF (uint16_t)(-1)
19319+
19320+/**
19321+ * dpni_open() - Open a control session for the specified object
19322+ * @mc_io: Pointer to MC portal's I/O object
19323+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19324+ * @dpni_id: DPNI unique ID
19325+ * @token: Returned token; use in subsequent API calls
19326+ *
19327+ * This function can be used to open a control session for an
19328+ * already created object; an object may have been declared in
19329+ * the DPL or by calling the dpni_create() function.
19330+ * This function returns a unique authentication token,
19331+ * associated with the specific object ID and the specific MC
19332+ * portal; this token must be used in all subsequent commands for
19333+ * this specific object.
19334+ *
19335+ * Return: '0' on Success; Error code otherwise.
19336+ */
19337+int dpni_open(struct fsl_mc_io *mc_io,
19338+ uint32_t cmd_flags,
19339+ int dpni_id,
19340+ uint16_t *token);
19341+
19342+/**
19343+ * dpni_close() - Close the control session of the object
19344+ * @mc_io: Pointer to MC portal's I/O object
19345+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19346+ * @token: Token of DPNI object
19347+ *
19348+ * After this function is called, no further operations are
19349+ * allowed on the object without opening a new control session.
19350+ *
19351+ * Return: '0' on Success; Error code otherwise.
19352+ */
19353+int dpni_close(struct fsl_mc_io *mc_io,
19354+ uint32_t cmd_flags,
19355+ uint16_t token);
19356+
19357+/* DPNI configuration options */
19358+
19359+/**
19360+ * Allow different distribution key profiles for different traffic classes;
19361+ * if not set, a single key profile is assumed
19362+ */
19363+#define DPNI_OPT_ALLOW_DIST_KEY_PER_TC 0x00000001
19364+
19365+/**
19366+ * Disable all non-error transmit confirmation; error frames are reported
19367+ * back to a common Tx error queue
19368+ */
19369+#define DPNI_OPT_TX_CONF_DISABLED 0x00000002
19370+
19371+/**
19372+ * Disable per-sender private Tx confirmation/error queue
19373+ */
19374+#define DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED 0x00000004
19375+
19376+/**
19377+ * Support distribution based on hashed key;
19378+ * allows statistical distribution over receive queues in a traffic class
19379+ */
19380+#define DPNI_OPT_DIST_HASH 0x00000010
19381+
19382+/**
19383+ * DEPRECATED - if this flag is selected and and all new 'max_fs_entries' are
19384+ * '0' then backward compatibility is preserved;
19385+ * Support distribution based on flow steering;
19386+ * allows explicit control of distribution over receive queues in a traffic
19387+ * class
19388+ */
19389+#define DPNI_OPT_DIST_FS 0x00000020
19390+
19391+/**
19392+ * Unicast filtering support
19393+ */
19394+#define DPNI_OPT_UNICAST_FILTER 0x00000080
19395+/**
19396+ * Multicast filtering support
19397+ */
19398+#define DPNI_OPT_MULTICAST_FILTER 0x00000100
19399+/**
19400+ * VLAN filtering support
19401+ */
19402+#define DPNI_OPT_VLAN_FILTER 0x00000200
19403+/**
19404+ * Support IP reassembly on received packets
19405+ */
19406+#define DPNI_OPT_IPR 0x00000800
19407+/**
19408+ * Support IP fragmentation on transmitted packets
19409+ */
19410+#define DPNI_OPT_IPF 0x00001000
19411+/**
19412+ * VLAN manipulation support
19413+ */
19414+#define DPNI_OPT_VLAN_MANIPULATION 0x00010000
19415+/**
19416+ * Support masking of QoS lookup keys
19417+ */
19418+#define DPNI_OPT_QOS_MASK_SUPPORT 0x00020000
19419+/**
19420+ * Support masking of Flow Steering lookup keys
19421+ */
19422+#define DPNI_OPT_FS_MASK_SUPPORT 0x00040000
19423+
19424+/**
19425+ * struct dpni_extended_cfg - Structure representing extended DPNI configuration
19426+ * @tc_cfg: TCs configuration
19427+ * @ipr_cfg: IP reassembly configuration
19428+ */
19429+struct dpni_extended_cfg {
19430+ /**
19431+ * struct tc_cfg - TC configuration
19432+ * @max_dist: Maximum distribution size for Rx traffic class;
19433+ * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96,
19434+ * 112,128,192,224,256,384,448,512,768,896,1024;
19435+ * value '0' will be treated as '1'.
19436+ * other unsupported values will be round down to the nearest
19437+ * supported value.
19438+ * @max_fs_entries: Maximum FS entries for Rx traffic class;
19439+ * '0' means no support for this TC;
19440+ */
19441+ struct {
19442+ uint16_t max_dist;
19443+ uint16_t max_fs_entries;
19444+ } tc_cfg[DPNI_MAX_TC];
19445+ /**
19446+ * struct ipr_cfg - Structure representing IP reassembly configuration
19447+ * @max_reass_frm_size: Maximum size of the reassembled frame
19448+ * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments
19449+ * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments
19450+ * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly
19451+ * process
19452+ * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly
19453+ * process
19454+ */
19455+ struct {
19456+ uint16_t max_reass_frm_size;
19457+ uint16_t min_frag_size_ipv4;
19458+ uint16_t min_frag_size_ipv6;
19459+ uint16_t max_open_frames_ipv4;
19460+ uint16_t max_open_frames_ipv6;
19461+ } ipr_cfg;
19462+};
19463+
19464+/**
19465+ * dpni_prepare_extended_cfg() - function prepare extended parameters
19466+ * @cfg: extended structure
19467+ * @ext_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA
19468+ *
19469+ * This function has to be called before dpni_create()
19470+ */
19471+int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg,
19472+ uint8_t *ext_cfg_buf);
19473+
19474+/**
19475+ * struct dpni_cfg - Structure representing DPNI configuration
19476+ * @mac_addr: Primary MAC address
19477+ * @adv: Advanced parameters; default is all zeros;
19478+ * use this structure to change default settings
19479+ */
19480+struct dpni_cfg {
19481+ uint8_t mac_addr[6];
19482+ /**
19483+ * struct adv - Advanced parameters
19484+ * @options: Mask of available options; use 'DPNI_OPT_<X>' values
19485+ * @start_hdr: Selects the packet starting header for parsing;
19486+ * 'NET_PROT_NONE' is treated as default: 'NET_PROT_ETH'
19487+ * @max_senders: Maximum number of different senders; used as the number
19488+ * of dedicated Tx flows; Non-power-of-2 values are rounded
19489+ * up to the next power-of-2 value as hardware demands it;
19490+ * '0' will be treated as '1'
19491+ * @max_tcs: Maximum number of traffic classes (for both Tx and Rx);
19492+ * '0' will e treated as '1'
19493+ * @max_unicast_filters: Maximum number of unicast filters;
19494+ * '0' is treated as '16'
19495+ * @max_multicast_filters: Maximum number of multicast filters;
19496+ * '0' is treated as '64'
19497+ * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in
19498+ * the QoS table; '0' is treated as '64'
19499+ * @max_qos_key_size: Maximum key size for the QoS look-up;
19500+ * '0' is treated as '24' which is enough for IPv4
19501+ * 5-tuple
19502+ * @max_dist_key_size: Maximum key size for the distribution;
19503+ * '0' is treated as '24' which is enough for IPv4 5-tuple
19504+ * @max_policers: Maximum number of policers;
19505+ * should be between '0' and max_tcs
19506+ * @max_congestion_ctrl: Maximum number of congestion control groups
19507+ * (CGs); covers early drop and congestion notification
19508+ * requirements;
19509+ * should be between '0' and ('max_tcs' + 'max_senders')
19510+ * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory
19511+ * filled with the extended configuration by calling
19512+ * dpni_prepare_extended_cfg()
19513+ */
19514+ struct {
19515+ uint32_t options;
19516+ enum net_prot start_hdr;
19517+ uint8_t max_senders;
19518+ uint8_t max_tcs;
19519+ uint8_t max_unicast_filters;
19520+ uint8_t max_multicast_filters;
19521+ uint8_t max_vlan_filters;
19522+ uint8_t max_qos_entries;
19523+ uint8_t max_qos_key_size;
19524+ uint8_t max_dist_key_size;
19525+ uint8_t max_policers;
19526+ uint8_t max_congestion_ctrl;
19527+ uint64_t ext_cfg_iova;
19528+ } adv;
19529+};
19530+
19531+/**
19532+ * dpni_create() - Create the DPNI object
19533+ * @mc_io: Pointer to MC portal's I/O object
19534+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19535+ * @cfg: Configuration structure
19536+ * @token: Returned token; use in subsequent API calls
19537+ *
19538+ * Create the DPNI object, allocate required resources and
19539+ * perform required initialization.
19540+ *
19541+ * The object can be created either by declaring it in the
19542+ * DPL file, or by calling this function.
19543+ *
19544+ * This function returns a unique authentication token,
19545+ * associated with the specific object ID and the specific MC
19546+ * portal; this token must be used in all subsequent calls to
19547+ * this specific object. For objects that are created using the
19548+ * DPL file, call dpni_open() function to get an authentication
19549+ * token first.
19550+ *
19551+ * Return: '0' on Success; Error code otherwise.
19552+ */
19553+int dpni_create(struct fsl_mc_io *mc_io,
19554+ uint32_t cmd_flags,
19555+ const struct dpni_cfg *cfg,
19556+ uint16_t *token);
19557+
19558+/**
19559+ * dpni_destroy() - Destroy the DPNI object and release all its resources.
19560+ * @mc_io: Pointer to MC portal's I/O object
19561+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19562+ * @token: Token of DPNI object
19563+ *
19564+ * Return: '0' on Success; error code otherwise.
19565+ */
19566+int dpni_destroy(struct fsl_mc_io *mc_io,
19567+ uint32_t cmd_flags,
19568+ uint16_t token);
19569+
19570+/**
19571+ * struct dpni_pools_cfg - Structure representing buffer pools configuration
19572+ * @num_dpbp: Number of DPBPs
19573+ * @pools: Array of buffer pools parameters; The number of valid entries
19574+ * must match 'num_dpbp' value
19575+ */
19576+struct dpni_pools_cfg {
19577+ uint8_t num_dpbp;
19578+ /**
19579+ * struct pools - Buffer pools parameters
19580+ * @dpbp_id: DPBP object ID
19581+ * @buffer_size: Buffer size
19582+ * @backup_pool: Backup pool
19583+ */
19584+ struct {
19585+ int dpbp_id;
19586+ uint16_t buffer_size;
19587+ int backup_pool;
19588+ } pools[DPNI_MAX_DPBP];
19589+};
19590+
19591+/**
19592+ * dpni_set_pools() - Set buffer pools configuration
19593+ * @mc_io: Pointer to MC portal's I/O object
19594+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19595+ * @token: Token of DPNI object
19596+ * @cfg: Buffer pools configuration
19597+ *
19598+ * mandatory for DPNI operation
19599+ * warning:Allowed only when DPNI is disabled
19600+ *
19601+ * Return: '0' on Success; Error code otherwise.
19602+ */
19603+int dpni_set_pools(struct fsl_mc_io *mc_io,
19604+ uint32_t cmd_flags,
19605+ uint16_t token,
19606+ const struct dpni_pools_cfg *cfg);
19607+
19608+/**
19609+ * dpni_enable() - Enable the DPNI, allow sending and receiving frames.
19610+ * @mc_io: Pointer to MC portal's I/O object
19611+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19612+ * @token: Token of DPNI object
19613+ *
19614+ * Return: '0' on Success; Error code otherwise.
19615+ */
19616+int dpni_enable(struct fsl_mc_io *mc_io,
19617+ uint32_t cmd_flags,
19618+ uint16_t token);
19619+
19620+/**
19621+ * dpni_disable() - Disable the DPNI, stop sending and receiving frames.
19622+ * @mc_io: Pointer to MC portal's I/O object
19623+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19624+ * @token: Token of DPNI object
19625+ *
19626+ * Return: '0' on Success; Error code otherwise.
19627+ */
19628+int dpni_disable(struct fsl_mc_io *mc_io,
19629+ uint32_t cmd_flags,
19630+ uint16_t token);
19631+
19632+/**
19633+ * dpni_is_enabled() - Check if the DPNI is enabled.
19634+ * @mc_io: Pointer to MC portal's I/O object
19635+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19636+ * @token: Token of DPNI object
19637+ * @en: Returns '1' if object is enabled; '0' otherwise
19638+ *
19639+ * Return: '0' on Success; Error code otherwise.
19640+ */
19641+int dpni_is_enabled(struct fsl_mc_io *mc_io,
19642+ uint32_t cmd_flags,
19643+ uint16_t token,
19644+ int *en);
19645+
19646+/**
19647+ * dpni_reset() - Reset the DPNI, returns the object to initial state.
19648+ * @mc_io: Pointer to MC portal's I/O object
19649+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19650+ * @token: Token of DPNI object
19651+ *
19652+ * Return: '0' on Success; Error code otherwise.
19653+ */
19654+int dpni_reset(struct fsl_mc_io *mc_io,
19655+ uint32_t cmd_flags,
19656+ uint16_t token);
19657+
19658+/**
19659+ * DPNI IRQ Index and Events
19660+ */
19661+
19662+/**
19663+ * IRQ index
19664+ */
19665+#define DPNI_IRQ_INDEX 0
19666+/**
19667+ * IRQ event - indicates a change in link state
19668+ */
19669+#define DPNI_IRQ_EVENT_LINK_CHANGED 0x00000001
19670+
19671+/**
19672+ * struct dpni_irq_cfg - IRQ configuration
19673+ * @addr: Address that must be written to signal a message-based interrupt
19674+ * @val: Value to write into irq_addr address
19675+ * @irq_num: A user defined number associated with this IRQ
19676+ */
19677+struct dpni_irq_cfg {
19678+ uint64_t addr;
19679+ uint32_t val;
19680+ int irq_num;
19681+};
19682+
19683+/**
19684+ * dpni_set_irq() - Set IRQ information for the DPNI to trigger an interrupt.
19685+ * @mc_io: Pointer to MC portal's I/O object
19686+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19687+ * @token: Token of DPNI object
19688+ * @irq_index: Identifies the interrupt index to configure
19689+ * @irq_cfg: IRQ configuration
19690+ *
19691+ * Return: '0' on Success; Error code otherwise.
19692+ */
19693+int dpni_set_irq(struct fsl_mc_io *mc_io,
19694+ uint32_t cmd_flags,
19695+ uint16_t token,
19696+ uint8_t irq_index,
19697+ struct dpni_irq_cfg *irq_cfg);
19698+
19699+/**
19700+ * dpni_get_irq() - Get IRQ information from the DPNI.
19701+ * @mc_io: Pointer to MC portal's I/O object
19702+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19703+ * @token: Token of DPNI object
19704+ * @irq_index: The interrupt index to configure
19705+ * @type: Interrupt type: 0 represents message interrupt
19706+ * type (both irq_addr and irq_val are valid)
19707+ * @irq_cfg: IRQ attributes
19708+ *
19709+ * Return: '0' on Success; Error code otherwise.
19710+ */
19711+int dpni_get_irq(struct fsl_mc_io *mc_io,
19712+ uint32_t cmd_flags,
19713+ uint16_t token,
19714+ uint8_t irq_index,
19715+ int *type,
19716+ struct dpni_irq_cfg *irq_cfg);
19717+
19718+/**
19719+ * dpni_set_irq_enable() - Set overall interrupt state.
19720+ * @mc_io: Pointer to MC portal's I/O object
19721+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19722+ * @token: Token of DPNI object
19723+ * @irq_index: The interrupt index to configure
19724+ * @en: Interrupt state: - enable = 1, disable = 0
19725+ *
19726+ * Allows GPP software to control when interrupts are generated.
19727+ * Each interrupt can have up to 32 causes. The enable/disable control's the
19728+ * overall interrupt state. if the interrupt is disabled no causes will cause
19729+ * an interrupt.
19730+ *
19731+ * Return: '0' on Success; Error code otherwise.
19732+ */
19733+int dpni_set_irq_enable(struct fsl_mc_io *mc_io,
19734+ uint32_t cmd_flags,
19735+ uint16_t token,
19736+ uint8_t irq_index,
19737+ uint8_t en);
19738+
19739+/**
19740+ * dpni_get_irq_enable() - Get overall interrupt state
19741+ * @mc_io: Pointer to MC portal's I/O object
19742+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19743+ * @token: Token of DPNI object
19744+ * @irq_index: The interrupt index to configure
19745+ * @en: Returned interrupt state - enable = 1, disable = 0
19746+ *
19747+ * Return: '0' on Success; Error code otherwise.
19748+ */
19749+int dpni_get_irq_enable(struct fsl_mc_io *mc_io,
19750+ uint32_t cmd_flags,
19751+ uint16_t token,
19752+ uint8_t irq_index,
19753+ uint8_t *en);
19754+
19755+/**
19756+ * dpni_set_irq_mask() - Set interrupt mask.
19757+ * @mc_io: Pointer to MC portal's I/O object
19758+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19759+ * @token: Token of DPNI object
19760+ * @irq_index: The interrupt index to configure
19761+ * @mask: event mask to trigger interrupt;
19762+ * each bit:
19763+ * 0 = ignore event
19764+ * 1 = consider event for asserting IRQ
19765+ *
19766+ * Every interrupt can have up to 32 causes and the interrupt model supports
19767+ * masking/unmasking each cause independently
19768+ *
19769+ * Return: '0' on Success; Error code otherwise.
19770+ */
19771+int dpni_set_irq_mask(struct fsl_mc_io *mc_io,
19772+ uint32_t cmd_flags,
19773+ uint16_t token,
19774+ uint8_t irq_index,
19775+ uint32_t mask);
19776+
19777+/**
19778+ * dpni_get_irq_mask() - Get interrupt mask.
19779+ * @mc_io: Pointer to MC portal's I/O object
19780+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19781+ * @token: Token of DPNI object
19782+ * @irq_index: The interrupt index to configure
19783+ * @mask: Returned event mask to trigger interrupt
19784+ *
19785+ * Every interrupt can have up to 32 causes and the interrupt model supports
19786+ * masking/unmasking each cause independently
19787+ *
19788+ * Return: '0' on Success; Error code otherwise.
19789+ */
19790+int dpni_get_irq_mask(struct fsl_mc_io *mc_io,
19791+ uint32_t cmd_flags,
19792+ uint16_t token,
19793+ uint8_t irq_index,
19794+ uint32_t *mask);
19795+
19796+/**
19797+ * dpni_get_irq_status() - Get the current status of any pending interrupts.
19798+ * @mc_io: Pointer to MC portal's I/O object
19799+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19800+ * @token: Token of DPNI object
19801+ * @irq_index: The interrupt index to configure
19802+ * @status: Returned interrupts status - one bit per cause:
19803+ * 0 = no interrupt pending
19804+ * 1 = interrupt pending
19805+ *
19806+ * Return: '0' on Success; Error code otherwise.
19807+ */
19808+int dpni_get_irq_status(struct fsl_mc_io *mc_io,
19809+ uint32_t cmd_flags,
19810+ uint16_t token,
19811+ uint8_t irq_index,
19812+ uint32_t *status);
19813+
19814+/**
19815+ * dpni_clear_irq_status() - Clear a pending interrupt's status
19816+ * @mc_io: Pointer to MC portal's I/O object
19817+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19818+ * @token: Token of DPNI object
19819+ * @irq_index: The interrupt index to configure
19820+ * @status: bits to clear (W1C) - one bit per cause:
19821+ * 0 = don't change
19822+ * 1 = clear status bit
19823+ *
19824+ * Return: '0' on Success; Error code otherwise.
19825+ */
19826+int dpni_clear_irq_status(struct fsl_mc_io *mc_io,
19827+ uint32_t cmd_flags,
19828+ uint16_t token,
19829+ uint8_t irq_index,
19830+ uint32_t status);
19831+
19832+/**
19833+ * struct dpni_attr - Structure representing DPNI attributes
19834+ * @id: DPNI object ID
19835+ * @version: DPNI version
19836+ * @start_hdr: Indicates the packet starting header for parsing
19837+ * @options: Mask of available options; reflects the value as was given in
19838+ * object's creation
19839+ * @max_senders: Maximum number of different senders; used as the number
19840+ * of dedicated Tx flows;
19841+ * @max_tcs: Maximum number of traffic classes (for both Tx and Rx)
19842+ * @max_unicast_filters: Maximum number of unicast filters
19843+ * @max_multicast_filters: Maximum number of multicast filters
19844+ * @max_vlan_filters: Maximum number of VLAN filters
19845+ * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in QoS table
19846+ * @max_qos_key_size: Maximum key size for the QoS look-up
19847+ * @max_dist_key_size: Maximum key size for the distribution look-up
19848+ * @max_policers: Maximum number of policers;
19849+ * @max_congestion_ctrl: Maximum number of congestion control groups (CGs);
19850+ * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory;
19851+ * call dpni_extract_extended_cfg() to extract the extended configuration
19852+ */
19853+struct dpni_attr {
19854+ int id;
19855+ /**
19856+ * struct version - DPNI version
19857+ * @major: DPNI major version
19858+ * @minor: DPNI minor version
19859+ */
19860+ struct {
19861+ uint16_t major;
19862+ uint16_t minor;
19863+ } version;
19864+ enum net_prot start_hdr;
19865+ uint32_t options;
19866+ uint8_t max_senders;
19867+ uint8_t max_tcs;
19868+ uint8_t max_unicast_filters;
19869+ uint8_t max_multicast_filters;
19870+ uint8_t max_vlan_filters;
19871+ uint8_t max_qos_entries;
19872+ uint8_t max_qos_key_size;
19873+ uint8_t max_dist_key_size;
19874+ uint8_t max_policers;
19875+ uint8_t max_congestion_ctrl;
19876+ uint64_t ext_cfg_iova;
19877+};
19878+
19879+/**
19880+ * dpni_get_attributes() - Retrieve DPNI attributes.
19881+ * @mc_io: Pointer to MC portal's I/O object
19882+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19883+ * @token: Token of DPNI object
19884+ * @attr: Object's attributes
19885+ *
19886+ * Return: '0' on Success; Error code otherwise.
19887+ */
19888+int dpni_get_attributes(struct fsl_mc_io *mc_io,
19889+ uint32_t cmd_flags,
19890+ uint16_t token,
19891+ struct dpni_attr *attr);
19892+
19893+/**
19894+ * dpni_extract_extended_cfg() - extract the extended parameters
19895+ * @cfg: extended structure
19896+ * @ext_cfg_buf: 256 bytes of DMA-able memory
19897+ *
19898+ * This function has to be called after dpni_get_attributes()
19899+ */
19900+int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg,
19901+ const uint8_t *ext_cfg_buf);
19902+
19903+/**
19904+ * DPNI errors
19905+ */
19906+
19907+/**
19908+ * Extract out of frame header error
19909+ */
19910+#define DPNI_ERROR_EOFHE 0x00020000
19911+/**
19912+ * Frame length error
19913+ */
19914+#define DPNI_ERROR_FLE 0x00002000
19915+/**
19916+ * Frame physical error
19917+ */
19918+#define DPNI_ERROR_FPE 0x00001000
19919+/**
19920+ * Parsing header error
19921+ */
19922+#define DPNI_ERROR_PHE 0x00000020
19923+/**
19924+ * Parser L3 checksum error
19925+ */
19926+#define DPNI_ERROR_L3CE 0x00000004
19927+/**
19928+ * Parser L3 checksum error
19929+ */
19930+#define DPNI_ERROR_L4CE 0x00000001
19931+
19932+/**
19933+ * enum dpni_error_action - Defines DPNI behavior for errors
19934+ * @DPNI_ERROR_ACTION_DISCARD: Discard the frame
19935+ * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow
19936+ * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue
19937+ */
19938+enum dpni_error_action {
19939+ DPNI_ERROR_ACTION_DISCARD = 0,
19940+ DPNI_ERROR_ACTION_CONTINUE = 1,
19941+ DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2
19942+};
19943+
19944+/**
19945+ * struct dpni_error_cfg - Structure representing DPNI errors treatment
19946+ * @errors: Errors mask; use 'DPNI_ERROR__<X>
19947+ * @error_action: The desired action for the errors mask
19948+ * @set_frame_annotation: Set to '1' to mark the errors in frame annotation
19949+ * status (FAS); relevant only for the non-discard action
19950+ */
19951+struct dpni_error_cfg {
19952+ uint32_t errors;
19953+ enum dpni_error_action error_action;
19954+ int set_frame_annotation;
19955+};
19956+
19957+/**
19958+ * dpni_set_errors_behavior() - Set errors behavior
19959+ * @mc_io: Pointer to MC portal's I/O object
19960+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
19961+ * @token: Token of DPNI object
19962+ * @cfg: Errors configuration
19963+ *
19964+ * this function may be called numerous times with different
19965+ * error masks
19966+ *
19967+ * Return: '0' on Success; Error code otherwise.
19968+ */
19969+int dpni_set_errors_behavior(struct fsl_mc_io *mc_io,
19970+ uint32_t cmd_flags,
19971+ uint16_t token,
19972+ struct dpni_error_cfg *cfg);
19973+
19974+/**
19975+ * DPNI buffer layout modification options
19976+ */
19977+
19978+/**
19979+ * Select to modify the time-stamp setting
19980+ */
19981+#define DPNI_BUF_LAYOUT_OPT_TIMESTAMP 0x00000001
19982+/**
19983+ * Select to modify the parser-result setting; not applicable for Tx
19984+ */
19985+#define DPNI_BUF_LAYOUT_OPT_PARSER_RESULT 0x00000002
19986+/**
19987+ * Select to modify the frame-status setting
19988+ */
19989+#define DPNI_BUF_LAYOUT_OPT_FRAME_STATUS 0x00000004
19990+/**
19991+ * Select to modify the private-data-size setting
19992+ */
19993+#define DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE 0x00000008
19994+/**
19995+ * Select to modify the data-alignment setting
19996+ */
19997+#define DPNI_BUF_LAYOUT_OPT_DATA_ALIGN 0x00000010
19998+/**
19999+ * Select to modify the data-head-room setting
20000+ */
20001+#define DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM 0x00000020
20002+/**
20003+ * Select to modify the data-tail-room setting
20004+ */
20005+#define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM 0x00000040
20006+
20007+/**
20008+ * struct dpni_buffer_layout - Structure representing DPNI buffer layout
20009+ * @options: Flags representing the suggested modifications to the buffer
20010+ * layout; Use any combination of 'DPNI_BUF_LAYOUT_OPT_<X>' flags
20011+ * @pass_timestamp: Pass timestamp value
20012+ * @pass_parser_result: Pass parser results
20013+ * @pass_frame_status: Pass frame status
20014+ * @private_data_size: Size kept for private data (in bytes)
20015+ * @data_align: Data alignment
20016+ * @data_head_room: Data head room
20017+ * @data_tail_room: Data tail room
20018+ */
20019+struct dpni_buffer_layout {
20020+ uint32_t options;
20021+ int pass_timestamp;
20022+ int pass_parser_result;
20023+ int pass_frame_status;
20024+ uint16_t private_data_size;
20025+ uint16_t data_align;
20026+ uint16_t data_head_room;
20027+ uint16_t data_tail_room;
20028+};
20029+
20030+/**
20031+ * dpni_get_rx_buffer_layout() - Retrieve Rx buffer layout attributes.
20032+ * @mc_io: Pointer to MC portal's I/O object
20033+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20034+ * @token: Token of DPNI object
20035+ * @layout: Returns buffer layout attributes
20036+ *
20037+ * Return: '0' on Success; Error code otherwise.
20038+ */
20039+int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io,
20040+ uint32_t cmd_flags,
20041+ uint16_t token,
20042+ struct dpni_buffer_layout *layout);
20043+
20044+/**
20045+ * dpni_set_rx_buffer_layout() - Set Rx buffer layout configuration.
20046+ * @mc_io: Pointer to MC portal's I/O object
20047+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20048+ * @token: Token of DPNI object
20049+ * @layout: Buffer layout configuration
20050+ *
20051+ * Return: '0' on Success; Error code otherwise.
20052+ *
20053+ * @warning Allowed only when DPNI is disabled
20054+ */
20055+int dpni_set_rx_buffer_layout(struct fsl_mc_io *mc_io,
20056+ uint32_t cmd_flags,
20057+ uint16_t token,
20058+ const struct dpni_buffer_layout *layout);
20059+
20060+/**
20061+ * dpni_get_tx_buffer_layout() - Retrieve Tx buffer layout attributes.
20062+ * @mc_io: Pointer to MC portal's I/O object
20063+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20064+ * @token: Token of DPNI object
20065+ * @layout: Returns buffer layout attributes
20066+ *
20067+ * Return: '0' on Success; Error code otherwise.
20068+ */
20069+int dpni_get_tx_buffer_layout(struct fsl_mc_io *mc_io,
20070+ uint32_t cmd_flags,
20071+ uint16_t token,
20072+ struct dpni_buffer_layout *layout);
20073+
20074+/**
20075+ * dpni_set_tx_buffer_layout() - Set Tx buffer layout configuration.
20076+ * @mc_io: Pointer to MC portal's I/O object
20077+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20078+ * @token: Token of DPNI object
20079+ * @layout: Buffer layout configuration
20080+ *
20081+ * Return: '0' on Success; Error code otherwise.
20082+ *
20083+ * @warning Allowed only when DPNI is disabled
20084+ */
20085+int dpni_set_tx_buffer_layout(struct fsl_mc_io *mc_io,
20086+ uint32_t cmd_flags,
20087+ uint16_t token,
20088+ const struct dpni_buffer_layout *layout);
20089+
20090+/**
20091+ * dpni_get_tx_conf_buffer_layout() - Retrieve Tx confirmation buffer layout
20092+ * attributes.
20093+ * @mc_io: Pointer to MC portal's I/O object
20094+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20095+ * @token: Token of DPNI object
20096+ * @layout: Returns buffer layout attributes
20097+ *
20098+ * Return: '0' on Success; Error code otherwise.
20099+ */
20100+int dpni_get_tx_conf_buffer_layout(struct fsl_mc_io *mc_io,
20101+ uint32_t cmd_flags,
20102+ uint16_t token,
20103+ struct dpni_buffer_layout *layout);
20104+
20105+/**
20106+ * dpni_set_tx_conf_buffer_layout() - Set Tx confirmation buffer layout
20107+ * configuration.
20108+ * @mc_io: Pointer to MC portal's I/O object
20109+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20110+ * @token: Token of DPNI object
20111+ * @layout: Buffer layout configuration
20112+ *
20113+ * Return: '0' on Success; Error code otherwise.
20114+ *
20115+ * @warning Allowed only when DPNI is disabled
20116+ */
20117+int dpni_set_tx_conf_buffer_layout(struct fsl_mc_io *mc_io,
20118+ uint32_t cmd_flags,
20119+ uint16_t token,
20120+ const struct dpni_buffer_layout *layout);
20121+
20122+/**
20123+ * dpni_set_l3_chksum_validation() - Enable/disable L3 checksum validation
20124+ * @mc_io: Pointer to MC portal's I/O object
20125+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20126+ * @token: Token of DPNI object
20127+ * @en: Set to '1' to enable; '0' to disable
20128+ *
20129+ * Return: '0' on Success; Error code otherwise.
20130+ */
20131+int dpni_set_l3_chksum_validation(struct fsl_mc_io *mc_io,
20132+ uint32_t cmd_flags,
20133+ uint16_t token,
20134+ int en);
20135+
20136+/**
20137+ * dpni_get_l3_chksum_validation() - Get L3 checksum validation mode
20138+ * @mc_io: Pointer to MC portal's I/O object
20139+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20140+ * @token: Token of DPNI object
20141+ * @en: Returns '1' if enabled; '0' otherwise
20142+ *
20143+ * Return: '0' on Success; Error code otherwise.
20144+ */
20145+int dpni_get_l3_chksum_validation(struct fsl_mc_io *mc_io,
20146+ uint32_t cmd_flags,
20147+ uint16_t token,
20148+ int *en);
20149+
20150+/**
20151+ * dpni_set_l4_chksum_validation() - Enable/disable L4 checksum validation
20152+ * @mc_io: Pointer to MC portal's I/O object
20153+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20154+ * @token: Token of DPNI object
20155+ * @en: Set to '1' to enable; '0' to disable
20156+ *
20157+ * Return: '0' on Success; Error code otherwise.
20158+ */
20159+int dpni_set_l4_chksum_validation(struct fsl_mc_io *mc_io,
20160+ uint32_t cmd_flags,
20161+ uint16_t token,
20162+ int en);
20163+
20164+/**
20165+ * dpni_get_l4_chksum_validation() - Get L4 checksum validation mode
20166+ * @mc_io: Pointer to MC portal's I/O object
20167+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20168+ * @token: Token of DPNI object
20169+ * @en: Returns '1' if enabled; '0' otherwise
20170+ *
20171+ * Return: '0' on Success; Error code otherwise.
20172+ */
20173+int dpni_get_l4_chksum_validation(struct fsl_mc_io *mc_io,
20174+ uint32_t cmd_flags,
20175+ uint16_t token,
20176+ int *en);
20177+
20178+/**
20179+ * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used
20180+ * for enqueue operations
20181+ * @mc_io: Pointer to MC portal's I/O object
20182+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20183+ * @token: Token of DPNI object
20184+ * @qdid: Returned virtual QDID value that should be used as an argument
20185+ * in all enqueue operations
20186+ *
20187+ * Return: '0' on Success; Error code otherwise.
20188+ */
20189+int dpni_get_qdid(struct fsl_mc_io *mc_io,
20190+ uint32_t cmd_flags,
20191+ uint16_t token,
20192+ uint16_t *qdid);
20193+
20194+/**
20195+ * struct dpni_sp_info - Structure representing DPNI storage-profile information
20196+ * (relevant only for DPNI owned by AIOP)
20197+ * @spids: array of storage-profiles
20198+ */
20199+struct dpni_sp_info {
20200+ uint16_t spids[DPNI_MAX_SP];
20201+};
20202+
20203+/**
20204+ * dpni_get_spids() - Get the AIOP storage profile IDs associated with the DPNI
20205+ * @mc_io: Pointer to MC portal's I/O object
20206+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20207+ * @token: Token of DPNI object
20208+ * @sp_info: Returned AIOP storage-profile information
20209+ *
20210+ * Return: '0' on Success; Error code otherwise.
20211+ *
20212+ * @warning Only relevant for DPNI that belongs to AIOP container.
20213+ */
20214+int dpni_get_sp_info(struct fsl_mc_io *mc_io,
20215+ uint32_t cmd_flags,
20216+ uint16_t token,
20217+ struct dpni_sp_info *sp_info);
20218+
20219+/**
20220+ * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer)
20221+ * @mc_io: Pointer to MC portal's I/O object
20222+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20223+ * @token: Token of DPNI object
20224+ * @data_offset: Tx data offset (from start of buffer)
20225+ *
20226+ * Return: '0' on Success; Error code otherwise.
20227+ */
20228+int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io,
20229+ uint32_t cmd_flags,
20230+ uint16_t token,
20231+ uint16_t *data_offset);
20232+
20233+/**
20234+ * enum dpni_counter - DPNI counter types
20235+ * @DPNI_CNT_ING_FRAME: Counts ingress frames
20236+ * @DPNI_CNT_ING_BYTE: Counts ingress bytes
20237+ * @DPNI_CNT_ING_FRAME_DROP: Counts ingress frames dropped due to explicit
20238+ * 'drop' setting
20239+ * @DPNI_CNT_ING_FRAME_DISCARD: Counts ingress frames discarded due to errors
20240+ * @DPNI_CNT_ING_MCAST_FRAME: Counts ingress multicast frames
20241+ * @DPNI_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes
20242+ * @DPNI_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames
20243+ * @DPNI_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes
20244+ * @DPNI_CNT_EGR_FRAME: Counts egress frames
20245+ * @DPNI_CNT_EGR_BYTE: Counts egress bytes
20246+ * @DPNI_CNT_EGR_FRAME_DISCARD: Counts egress frames discarded due to errors
20247+ */
20248+enum dpni_counter {
20249+ DPNI_CNT_ING_FRAME = 0x0,
20250+ DPNI_CNT_ING_BYTE = 0x1,
20251+ DPNI_CNT_ING_FRAME_DROP = 0x2,
20252+ DPNI_CNT_ING_FRAME_DISCARD = 0x3,
20253+ DPNI_CNT_ING_MCAST_FRAME = 0x4,
20254+ DPNI_CNT_ING_MCAST_BYTE = 0x5,
20255+ DPNI_CNT_ING_BCAST_FRAME = 0x6,
20256+ DPNI_CNT_ING_BCAST_BYTES = 0x7,
20257+ DPNI_CNT_EGR_FRAME = 0x8,
20258+ DPNI_CNT_EGR_BYTE = 0x9,
20259+ DPNI_CNT_EGR_FRAME_DISCARD = 0xa
20260+};
20261+
20262+/**
20263+ * dpni_get_counter() - Read a specific DPNI counter
20264+ * @mc_io: Pointer to MC portal's I/O object
20265+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20266+ * @token: Token of DPNI object
20267+ * @counter: The requested counter
20268+ * @value: Returned counter's current value
20269+ *
20270+ * Return: '0' on Success; Error code otherwise.
20271+ */
20272+int dpni_get_counter(struct fsl_mc_io *mc_io,
20273+ uint32_t cmd_flags,
20274+ uint16_t token,
20275+ enum dpni_counter counter,
20276+ uint64_t *value);
20277+
20278+/**
20279+ * dpni_set_counter() - Set (or clear) a specific DPNI counter
20280+ * @mc_io: Pointer to MC portal's I/O object
20281+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20282+ * @token: Token of DPNI object
20283+ * @counter: The requested counter
20284+ * @value: New counter value; typically pass '0' for resetting
20285+ * the counter.
20286+ *
20287+ * Return: '0' on Success; Error code otherwise.
20288+ */
20289+int dpni_set_counter(struct fsl_mc_io *mc_io,
20290+ uint32_t cmd_flags,
20291+ uint16_t token,
20292+ enum dpni_counter counter,
20293+ uint64_t value);
20294+
20295+/**
20296+ * Enable auto-negotiation
20297+ */
20298+#define DPNI_LINK_OPT_AUTONEG 0x0000000000000001ULL
20299+/**
20300+ * Enable half-duplex mode
20301+ */
20302+#define DPNI_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL
20303+/**
20304+ * Enable pause frames
20305+ */
20306+#define DPNI_LINK_OPT_PAUSE 0x0000000000000004ULL
20307+/**
20308+ * Enable a-symmetric pause frames
20309+ */
20310+#define DPNI_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL
20311+
20312+/**
20313+ * struct - Structure representing DPNI link configuration
20314+ * @rate: Rate
20315+ * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values
20316+ */
20317+struct dpni_link_cfg {
20318+ uint32_t rate;
20319+ uint64_t options;
20320+};
20321+
20322+/**
20323+ * dpni_set_link_cfg() - set the link configuration.
20324+ * @mc_io: Pointer to MC portal's I/O object
20325+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20326+ * @token: Token of DPNI object
20327+ * @cfg: Link configuration
20328+ *
20329+ * Return: '0' on Success; Error code otherwise.
20330+ */
20331+int dpni_set_link_cfg(struct fsl_mc_io *mc_io,
20332+ uint32_t cmd_flags,
20333+ uint16_t token,
20334+ const struct dpni_link_cfg *cfg);
20335+
20336+/**
20337+ * struct dpni_link_state - Structure representing DPNI link state
20338+ * @rate: Rate
20339+ * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values
20340+ * @up: Link state; '0' for down, '1' for up
20341+ */
20342+struct dpni_link_state {
20343+ uint32_t rate;
20344+ uint64_t options;
20345+ int up;
20346+};
20347+
20348+/**
20349+ * dpni_get_link_state() - Return the link state (either up or down)
20350+ * @mc_io: Pointer to MC portal's I/O object
20351+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20352+ * @token: Token of DPNI object
20353+ * @state: Returned link state;
20354+ *
20355+ * Return: '0' on Success; Error code otherwise.
20356+ */
20357+int dpni_get_link_state(struct fsl_mc_io *mc_io,
20358+ uint32_t cmd_flags,
20359+ uint16_t token,
20360+ struct dpni_link_state *state);
20361+
20362+/**
20363+ * struct dpni_tx_shaping - Structure representing DPNI tx shaping configuration
20364+ * @rate_limit: rate in Mbps
20365+ * @max_burst_size: burst size in bytes (up to 64KB)
20366+ */
20367+struct dpni_tx_shaping_cfg {
20368+ uint32_t rate_limit;
20369+ uint16_t max_burst_size;
20370+};
20371+
20372+/**
20373+ * dpni_set_tx_shaping() - Set the transmit shaping
20374+ * @mc_io: Pointer to MC portal's I/O object
20375+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20376+ * @token: Token of DPNI object
20377+ * @tx_shaper: tx shaping configuration
20378+ *
20379+ * Return: '0' on Success; Error code otherwise.
20380+ */
20381+int dpni_set_tx_shaping(struct fsl_mc_io *mc_io,
20382+ uint32_t cmd_flags,
20383+ uint16_t token,
20384+ const struct dpni_tx_shaping_cfg *tx_shaper);
20385+
20386+/**
20387+ * dpni_set_max_frame_length() - Set the maximum received frame length.
20388+ * @mc_io: Pointer to MC portal's I/O object
20389+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20390+ * @token: Token of DPNI object
20391+ * @max_frame_length: Maximum received frame length (in
20392+ * bytes); frame is discarded if its
20393+ * length exceeds this value
20394+ *
20395+ * Return: '0' on Success; Error code otherwise.
20396+ */
20397+int dpni_set_max_frame_length(struct fsl_mc_io *mc_io,
20398+ uint32_t cmd_flags,
20399+ uint16_t token,
20400+ uint16_t max_frame_length);
20401+
20402+/**
20403+ * dpni_get_max_frame_length() - Get the maximum received frame length.
20404+ * @mc_io: Pointer to MC portal's I/O object
20405+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20406+ * @token: Token of DPNI object
20407+ * @max_frame_length: Maximum received frame length (in
20408+ * bytes); frame is discarded if its
20409+ * length exceeds this value
20410+ *
20411+ * Return: '0' on Success; Error code otherwise.
20412+ */
20413+int dpni_get_max_frame_length(struct fsl_mc_io *mc_io,
20414+ uint32_t cmd_flags,
20415+ uint16_t token,
20416+ uint16_t *max_frame_length);
20417+
20418+/**
20419+ * dpni_set_mtu() - Set the MTU for the interface.
20420+ * @mc_io: Pointer to MC portal's I/O object
20421+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20422+ * @token: Token of DPNI object
20423+ * @mtu: MTU length (in bytes)
20424+ *
20425+ * MTU determines the maximum fragment size for performing IP
20426+ * fragmentation on egress packets.
20427+ * Return: '0' on Success; Error code otherwise.
20428+ */
20429+int dpni_set_mtu(struct fsl_mc_io *mc_io,
20430+ uint32_t cmd_flags,
20431+ uint16_t token,
20432+ uint16_t mtu);
20433+
20434+/**
20435+ * dpni_get_mtu() - Get the MTU.
20436+ * @mc_io: Pointer to MC portal's I/O object
20437+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20438+ * @token: Token of DPNI object
20439+ * @mtu: Returned MTU length (in bytes)
20440+ *
20441+ * Return: '0' on Success; Error code otherwise.
20442+ */
20443+int dpni_get_mtu(struct fsl_mc_io *mc_io,
20444+ uint32_t cmd_flags,
20445+ uint16_t token,
20446+ uint16_t *mtu);
20447+
20448+/**
20449+ * dpni_set_multicast_promisc() - Enable/disable multicast promiscuous mode
20450+ * @mc_io: Pointer to MC portal's I/O object
20451+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20452+ * @token: Token of DPNI object
20453+ * @en: Set to '1' to enable; '0' to disable
20454+ *
20455+ * Return: '0' on Success; Error code otherwise.
20456+ */
20457+int dpni_set_multicast_promisc(struct fsl_mc_io *mc_io,
20458+ uint32_t cmd_flags,
20459+ uint16_t token,
20460+ int en);
20461+
20462+/**
20463+ * dpni_get_multicast_promisc() - Get multicast promiscuous mode
20464+ * @mc_io: Pointer to MC portal's I/O object
20465+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20466+ * @token: Token of DPNI object
20467+ * @en: Returns '1' if enabled; '0' otherwise
20468+ *
20469+ * Return: '0' on Success; Error code otherwise.
20470+ */
20471+int dpni_get_multicast_promisc(struct fsl_mc_io *mc_io,
20472+ uint32_t cmd_flags,
20473+ uint16_t token,
20474+ int *en);
20475+
20476+/**
20477+ * dpni_set_unicast_promisc() - Enable/disable unicast promiscuous mode
20478+ * @mc_io: Pointer to MC portal's I/O object
20479+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20480+ * @token: Token of DPNI object
20481+ * @en: Set to '1' to enable; '0' to disable
20482+ *
20483+ * Return: '0' on Success; Error code otherwise.
20484+ */
20485+int dpni_set_unicast_promisc(struct fsl_mc_io *mc_io,
20486+ uint32_t cmd_flags,
20487+ uint16_t token,
20488+ int en);
20489+
20490+/**
20491+ * dpni_get_unicast_promisc() - Get unicast promiscuous mode
20492+ * @mc_io: Pointer to MC portal's I/O object
20493+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20494+ * @token: Token of DPNI object
20495+ * @en: Returns '1' if enabled; '0' otherwise
20496+ *
20497+ * Return: '0' on Success; Error code otherwise.
20498+ */
20499+int dpni_get_unicast_promisc(struct fsl_mc_io *mc_io,
20500+ uint32_t cmd_flags,
20501+ uint16_t token,
20502+ int *en);
20503+
20504+/**
20505+ * dpni_set_primary_mac_addr() - Set the primary MAC address
20506+ * @mc_io: Pointer to MC portal's I/O object
20507+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20508+ * @token: Token of DPNI object
20509+ * @mac_addr: MAC address to set as primary address
20510+ *
20511+ * Return: '0' on Success; Error code otherwise.
20512+ */
20513+int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io,
20514+ uint32_t cmd_flags,
20515+ uint16_t token,
20516+ const uint8_t mac_addr[6]);
20517+
20518+/**
20519+ * dpni_get_primary_mac_addr() - Get the primary MAC address
20520+ * @mc_io: Pointer to MC portal's I/O object
20521+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20522+ * @token: Token of DPNI object
20523+ * @mac_addr: Returned MAC address
20524+ *
20525+ * Return: '0' on Success; Error code otherwise.
20526+ */
20527+int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io,
20528+ uint32_t cmd_flags,
20529+ uint16_t token,
20530+ uint8_t mac_addr[6]);
20531+
20532+/**
20533+ * dpni_add_mac_addr() - Add MAC address filter
20534+ * @mc_io: Pointer to MC portal's I/O object
20535+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20536+ * @token: Token of DPNI object
20537+ * @mac_addr: MAC address to add
20538+ *
20539+ * Return: '0' on Success; Error code otherwise.
20540+ */
20541+int dpni_add_mac_addr(struct fsl_mc_io *mc_io,
20542+ uint32_t cmd_flags,
20543+ uint16_t token,
20544+ const uint8_t mac_addr[6]);
20545+
20546+/**
20547+ * dpni_remove_mac_addr() - Remove MAC address filter
20548+ * @mc_io: Pointer to MC portal's I/O object
20549+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20550+ * @token: Token of DPNI object
20551+ * @mac_addr: MAC address to remove
20552+ *
20553+ * Return: '0' on Success; Error code otherwise.
20554+ */
20555+int dpni_remove_mac_addr(struct fsl_mc_io *mc_io,
20556+ uint32_t cmd_flags,
20557+ uint16_t token,
20558+ const uint8_t mac_addr[6]);
20559+
20560+/**
20561+ * dpni_clear_mac_filters() - Clear all unicast and/or multicast MAC filters
20562+ * @mc_io: Pointer to MC portal's I/O object
20563+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20564+ * @token: Token of DPNI object
20565+ * @unicast: Set to '1' to clear unicast addresses
20566+ * @multicast: Set to '1' to clear multicast addresses
20567+ *
20568+ * The primary MAC address is not cleared by this operation.
20569+ *
20570+ * Return: '0' on Success; Error code otherwise.
20571+ */
20572+int dpni_clear_mac_filters(struct fsl_mc_io *mc_io,
20573+ uint32_t cmd_flags,
20574+ uint16_t token,
20575+ int unicast,
20576+ int multicast);
20577+
20578+/**
20579+ * dpni_set_vlan_filters() - Enable/disable VLAN filtering mode
20580+ * @mc_io: Pointer to MC portal's I/O object
20581+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20582+ * @token: Token of DPNI object
20583+ * @en: Set to '1' to enable; '0' to disable
20584+ *
20585+ * Return: '0' on Success; Error code otherwise.
20586+ */
20587+int dpni_set_vlan_filters(struct fsl_mc_io *mc_io,
20588+ uint32_t cmd_flags,
20589+ uint16_t token,
20590+ int en);
20591+
20592+/**
20593+ * dpni_add_vlan_id() - Add VLAN ID filter
20594+ * @mc_io: Pointer to MC portal's I/O object
20595+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20596+ * @token: Token of DPNI object
20597+ * @vlan_id: VLAN ID to add
20598+ *
20599+ * Return: '0' on Success; Error code otherwise.
20600+ */
20601+int dpni_add_vlan_id(struct fsl_mc_io *mc_io,
20602+ uint32_t cmd_flags,
20603+ uint16_t token,
20604+ uint16_t vlan_id);
20605+
20606+/**
20607+ * dpni_remove_vlan_id() - Remove VLAN ID filter
20608+ * @mc_io: Pointer to MC portal's I/O object
20609+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20610+ * @token: Token of DPNI object
20611+ * @vlan_id: VLAN ID to remove
20612+ *
20613+ * Return: '0' on Success; Error code otherwise.
20614+ */
20615+int dpni_remove_vlan_id(struct fsl_mc_io *mc_io,
20616+ uint32_t cmd_flags,
20617+ uint16_t token,
20618+ uint16_t vlan_id);
20619+
20620+/**
20621+ * dpni_clear_vlan_filters() - Clear all VLAN filters
20622+ * @mc_io: Pointer to MC portal's I/O object
20623+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20624+ * @token: Token of DPNI object
20625+ *
20626+ * Return: '0' on Success; Error code otherwise.
20627+ */
20628+int dpni_clear_vlan_filters(struct fsl_mc_io *mc_io,
20629+ uint32_t cmd_flags,
20630+ uint16_t token);
20631+
20632+/**
20633+ * enum dpni_tx_schedule_mode - DPNI Tx scheduling mode
20634+ * @DPNI_TX_SCHED_STRICT_PRIORITY: strict priority
20635+ * @DPNI_TX_SCHED_WEIGHTED: weighted based scheduling
20636+ */
20637+enum dpni_tx_schedule_mode {
20638+ DPNI_TX_SCHED_STRICT_PRIORITY,
20639+ DPNI_TX_SCHED_WEIGHTED,
20640+};
20641+
20642+/**
20643+ * struct dpni_tx_schedule_cfg - Structure representing Tx
20644+ * scheduling configuration
20645+ * @mode: scheduling mode
20646+ * @delta_bandwidth: Bandwidth represented in weights from 100 to 10000;
20647+ * not applicable for 'strict-priority' mode;
20648+ */
20649+struct dpni_tx_schedule_cfg {
20650+ enum dpni_tx_schedule_mode mode;
20651+ uint16_t delta_bandwidth;
20652+};
20653+
20654+/**
20655+ * struct dpni_tx_selection_cfg - Structure representing transmission
20656+ * selection configuration
20657+ * @tc_sched: an array of traffic-classes
20658+ */
20659+struct dpni_tx_selection_cfg {
20660+ struct dpni_tx_schedule_cfg tc_sched[DPNI_MAX_TC];
20661+};
20662+
20663+/**
20664+ * dpni_set_tx_selection() - Set transmission selection configuration
20665+ * @mc_io: Pointer to MC portal's I/O object
20666+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20667+ * @token: Token of DPNI object
20668+ * @cfg: transmission selection configuration
20669+ *
20670+ * warning: Allowed only when DPNI is disabled
20671+ *
20672+ * Return: '0' on Success; Error code otherwise.
20673+ */
20674+int dpni_set_tx_selection(struct fsl_mc_io *mc_io,
20675+ uint32_t cmd_flags,
20676+ uint16_t token,
20677+ const struct dpni_tx_selection_cfg *cfg);
20678+
20679+/**
20680+ * enum dpni_dist_mode - DPNI distribution mode
20681+ * @DPNI_DIST_MODE_NONE: No distribution
20682+ * @DPNI_DIST_MODE_HASH: Use hash distribution; only relevant if
20683+ * the 'DPNI_OPT_DIST_HASH' option was set at DPNI creation
20684+ * @DPNI_DIST_MODE_FS: Use explicit flow steering; only relevant if
20685+ * the 'DPNI_OPT_DIST_FS' option was set at DPNI creation
20686+ */
20687+enum dpni_dist_mode {
20688+ DPNI_DIST_MODE_NONE = 0,
20689+ DPNI_DIST_MODE_HASH = 1,
20690+ DPNI_DIST_MODE_FS = 2
20691+};
20692+
20693+/**
20694+ * enum dpni_fs_miss_action - DPNI Flow Steering miss action
20695+ * @DPNI_FS_MISS_DROP: In case of no-match, drop the frame
20696+ * @DPNI_FS_MISS_EXPLICIT_FLOWID: In case of no-match, use explicit flow-id
20697+ * @DPNI_FS_MISS_HASH: In case of no-match, distribute using hash
20698+ */
20699+enum dpni_fs_miss_action {
20700+ DPNI_FS_MISS_DROP = 0,
20701+ DPNI_FS_MISS_EXPLICIT_FLOWID = 1,
20702+ DPNI_FS_MISS_HASH = 2
20703+};
20704+
20705+/**
20706+ * struct dpni_fs_tbl_cfg - Flow Steering table configuration
20707+ * @miss_action: Miss action selection
20708+ * @default_flow_id: Used when 'miss_action = DPNI_FS_MISS_EXPLICIT_FLOWID'
20709+ */
20710+struct dpni_fs_tbl_cfg {
20711+ enum dpni_fs_miss_action miss_action;
20712+ uint16_t default_flow_id;
20713+};
20714+
20715+/**
20716+ * dpni_prepare_key_cfg() - function prepare extract parameters
20717+ * @cfg: defining a full Key Generation profile (rule)
20718+ * @key_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA
20719+ *
20720+ * This function has to be called before the following functions:
20721+ * - dpni_set_rx_tc_dist()
20722+ * - dpni_set_qos_table()
20723+ */
20724+int dpni_prepare_key_cfg(const struct dpkg_profile_cfg *cfg,
20725+ uint8_t *key_cfg_buf);
20726+
20727+/**
20728+ * struct dpni_rx_tc_dist_cfg - Rx traffic class distribution configuration
20729+ * @dist_size: Set the distribution size;
20730+ * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96,
20731+ * 112,128,192,224,256,384,448,512,768,896,1024
20732+ * @dist_mode: Distribution mode
20733+ * @key_cfg_iova: I/O virtual address of 256 bytes DMA-able memory filled with
20734+ * the extractions to be used for the distribution key by calling
20735+ * dpni_prepare_key_cfg() relevant only when
20736+ * 'dist_mode != DPNI_DIST_MODE_NONE', otherwise it can be '0'
20737+ * @fs_cfg: Flow Steering table configuration; only relevant if
20738+ * 'dist_mode = DPNI_DIST_MODE_FS'
20739+ */
20740+struct dpni_rx_tc_dist_cfg {
20741+ uint16_t dist_size;
20742+ enum dpni_dist_mode dist_mode;
20743+ uint64_t key_cfg_iova;
20744+ struct dpni_fs_tbl_cfg fs_cfg;
20745+};
20746+
20747+/**
20748+ * dpni_set_rx_tc_dist() - Set Rx traffic class distribution configuration
20749+ * @mc_io: Pointer to MC portal's I/O object
20750+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20751+ * @token: Token of DPNI object
20752+ * @tc_id: Traffic class selection (0-7)
20753+ * @cfg: Traffic class distribution configuration
20754+ *
20755+ * warning: if 'dist_mode != DPNI_DIST_MODE_NONE', call dpni_prepare_key_cfg()
20756+ * first to prepare the key_cfg_iova parameter
20757+ *
20758+ * Return: '0' on Success; error code otherwise.
20759+ */
20760+int dpni_set_rx_tc_dist(struct fsl_mc_io *mc_io,
20761+ uint32_t cmd_flags,
20762+ uint16_t token,
20763+ uint8_t tc_id,
20764+ const struct dpni_rx_tc_dist_cfg *cfg);
20765+
20766+/**
20767+ * Set to select color aware mode (otherwise - color blind)
20768+ */
20769+#define DPNI_POLICER_OPT_COLOR_AWARE 0x00000001
20770+/**
20771+ * Set to discard frame with RED color
20772+ */
20773+#define DPNI_POLICER_OPT_DISCARD_RED 0x00000002
20774+
20775+/**
20776+ * enum dpni_policer_mode - selecting the policer mode
20777+ * @DPNI_POLICER_MODE_NONE: Policer is disabled
20778+ * @DPNI_POLICER_MODE_PASS_THROUGH: Policer pass through
20779+ * @DPNI_POLICER_MODE_RFC_2698: Policer algorithm RFC 2698
20780+ * @DPNI_POLICER_MODE_RFC_4115: Policer algorithm RFC 4115
20781+ */
20782+enum dpni_policer_mode {
20783+ DPNI_POLICER_MODE_NONE = 0,
20784+ DPNI_POLICER_MODE_PASS_THROUGH,
20785+ DPNI_POLICER_MODE_RFC_2698,
20786+ DPNI_POLICER_MODE_RFC_4115
20787+};
20788+
20789+/**
20790+ * enum dpni_policer_unit - DPNI policer units
20791+ * @DPNI_POLICER_UNIT_BYTES: bytes units
20792+ * @DPNI_POLICER_UNIT_FRAMES: frames units
20793+ */
20794+enum dpni_policer_unit {
20795+ DPNI_POLICER_UNIT_BYTES = 0,
20796+ DPNI_POLICER_UNIT_FRAMES
20797+};
20798+
20799+/**
20800+ * enum dpni_policer_color - selecting the policer color
20801+ * @DPNI_POLICER_COLOR_GREEN: Green color
20802+ * @DPNI_POLICER_COLOR_YELLOW: Yellow color
20803+ * @DPNI_POLICER_COLOR_RED: Red color
20804+ */
20805+enum dpni_policer_color {
20806+ DPNI_POLICER_COLOR_GREEN = 0,
20807+ DPNI_POLICER_COLOR_YELLOW,
20808+ DPNI_POLICER_COLOR_RED
20809+};
20810+
20811+/**
20812+ * struct dpni_rx_tc_policing_cfg - Policer configuration
20813+ * @options: Mask of available options; use 'DPNI_POLICER_OPT_<X>' values
20814+ * @mode: policer mode
20815+ * @default_color: For pass-through mode the policer re-colors with this
20816+ * color any incoming packets. For Color aware non-pass-through mode:
20817+ * policer re-colors with this color all packets with FD[DROPP]>2.
20818+ * @units: Bytes or Packets
20819+ * @cir: Committed information rate (CIR) in Kbps or packets/second
20820+ * @cbs: Committed burst size (CBS) in bytes or packets
20821+ * @eir: Peak information rate (PIR, rfc2698) in Kbps or packets/second
20822+ * Excess information rate (EIR, rfc4115) in Kbps or packets/second
20823+ * @ebs: Peak burst size (PBS, rfc2698) in bytes or packets
20824+ * Excess burst size (EBS, rfc4115) in bytes or packets
20825+ */
20826+struct dpni_rx_tc_policing_cfg {
20827+ uint32_t options;
20828+ enum dpni_policer_mode mode;
20829+ enum dpni_policer_unit units;
20830+ enum dpni_policer_color default_color;
20831+ uint32_t cir;
20832+ uint32_t cbs;
20833+ uint32_t eir;
20834+ uint32_t ebs;
20835+};
20836+
20837+/**
20838+ * dpni_set_rx_tc_policing() - Set Rx traffic class policing configuration
20839+ * @mc_io: Pointer to MC portal's I/O object
20840+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20841+ * @token: Token of DPNI object
20842+ * @tc_id: Traffic class selection (0-7)
20843+ * @cfg: Traffic class policing configuration
20844+ *
20845+ * Return: '0' on Success; error code otherwise.
20846+ */
20847+int dpni_set_rx_tc_policing(struct fsl_mc_io *mc_io,
20848+ uint32_t cmd_flags,
20849+ uint16_t token,
20850+ uint8_t tc_id,
20851+ const struct dpni_rx_tc_policing_cfg *cfg);
20852+
20853+/**
20854+ * dpni_get_rx_tc_policing() - Get Rx traffic class policing configuration
20855+ * @mc_io: Pointer to MC portal's I/O object
20856+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20857+ * @token: Token of DPNI object
20858+ * @tc_id: Traffic class selection (0-7)
20859+ * @cfg: Traffic class policing configuration
20860+ *
20861+ * Return: '0' on Success; error code otherwise.
20862+ */
20863+int dpni_get_rx_tc_policing(struct fsl_mc_io *mc_io,
20864+ uint32_t cmd_flags,
20865+ uint16_t token,
20866+ uint8_t tc_id,
20867+ struct dpni_rx_tc_policing_cfg *cfg);
20868+
20869+/**
20870+ * enum dpni_congestion_unit - DPNI congestion units
20871+ * @DPNI_CONGESTION_UNIT_BYTES: bytes units
20872+ * @DPNI_CONGESTION_UNIT_FRAMES: frames units
20873+ */
20874+enum dpni_congestion_unit {
20875+ DPNI_CONGESTION_UNIT_BYTES = 0,
20876+ DPNI_CONGESTION_UNIT_FRAMES
20877+};
20878+
20879+/**
20880+ * enum dpni_early_drop_mode - DPNI early drop mode
20881+ * @DPNI_EARLY_DROP_MODE_NONE: early drop is disabled
20882+ * @DPNI_EARLY_DROP_MODE_TAIL: early drop in taildrop mode
20883+ * @DPNI_EARLY_DROP_MODE_WRED: early drop in WRED mode
20884+ */
20885+enum dpni_early_drop_mode {
20886+ DPNI_EARLY_DROP_MODE_NONE = 0,
20887+ DPNI_EARLY_DROP_MODE_TAIL,
20888+ DPNI_EARLY_DROP_MODE_WRED
20889+};
20890+
20891+/**
20892+ * struct dpni_wred_cfg - WRED configuration
20893+ * @max_threshold: maximum threshold that packets may be discarded. Above this
20894+ * threshold all packets are discarded; must be less than 2^39;
20895+ * approximated to be expressed as (x+256)*2^(y-1) due to HW
20896+ * implementation.
20897+ * @min_threshold: minimum threshold that packets may be discarded at
20898+ * @drop_probability: probability that a packet will be discarded (1-100,
20899+ * associated with the max_threshold).
20900+ */
20901+struct dpni_wred_cfg {
20902+ uint64_t max_threshold;
20903+ uint64_t min_threshold;
20904+ uint8_t drop_probability;
20905+};
20906+
20907+/**
20908+ * struct dpni_early_drop_cfg - early-drop configuration
20909+ * @mode: drop mode
20910+ * @units: units type
20911+ * @green: WRED - 'green' configuration
20912+ * @yellow: WRED - 'yellow' configuration
20913+ * @red: WRED - 'red' configuration
20914+ * @tail_drop_threshold: tail drop threshold
20915+ */
20916+struct dpni_early_drop_cfg {
20917+ enum dpni_early_drop_mode mode;
20918+ enum dpni_congestion_unit units;
20919+
20920+ struct dpni_wred_cfg green;
20921+ struct dpni_wred_cfg yellow;
20922+ struct dpni_wred_cfg red;
20923+
20924+ uint32_t tail_drop_threshold;
20925+};
20926+
20927+/**
20928+ * dpni_prepare_early_drop() - prepare an early drop.
20929+ * @cfg: Early-drop configuration
20930+ * @early_drop_buf: Zeroed 256 bytes of memory before mapping it to DMA
20931+ *
20932+ * This function has to be called before dpni_set_rx_tc_early_drop or
20933+ * dpni_set_tx_tc_early_drop
20934+ *
20935+ */
20936+void dpni_prepare_early_drop(const struct dpni_early_drop_cfg *cfg,
20937+ uint8_t *early_drop_buf);
20938+
20939+/**
20940+ * dpni_extract_early_drop() - extract the early drop configuration.
20941+ * @cfg: Early-drop configuration
20942+ * @early_drop_buf: Zeroed 256 bytes of memory before mapping it to DMA
20943+ *
20944+ * This function has to be called after dpni_get_rx_tc_early_drop or
20945+ * dpni_get_tx_tc_early_drop
20946+ *
20947+ */
20948+void dpni_extract_early_drop(struct dpni_early_drop_cfg *cfg,
20949+ const uint8_t *early_drop_buf);
20950+
20951+/**
20952+ * dpni_set_rx_tc_early_drop() - Set Rx traffic class early-drop configuration
20953+ * @mc_io: Pointer to MC portal's I/O object
20954+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20955+ * @token: Token of DPNI object
20956+ * @tc_id: Traffic class selection (0-7)
20957+ * @early_drop_iova: I/O virtual address of 256 bytes DMA-able memory filled
20958+ * with the early-drop configuration by calling dpni_prepare_early_drop()
20959+ *
20960+ * warning: Before calling this function, call dpni_prepare_early_drop() to
20961+ * prepare the early_drop_iova parameter
20962+ *
20963+ * Return: '0' on Success; error code otherwise.
20964+ */
20965+int dpni_set_rx_tc_early_drop(struct fsl_mc_io *mc_io,
20966+ uint32_t cmd_flags,
20967+ uint16_t token,
20968+ uint8_t tc_id,
20969+ uint64_t early_drop_iova);
20970+
20971+/**
20972+ * dpni_get_rx_tc_early_drop() - Get Rx traffic class early-drop configuration
20973+ * @mc_io: Pointer to MC portal's I/O object
20974+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20975+ * @token: Token of DPNI object
20976+ * @tc_id: Traffic class selection (0-7)
20977+ * @early_drop_iova: I/O virtual address of 256 bytes DMA-able memory
20978+ *
20979+ * warning: After calling this function, call dpni_extract_early_drop() to
20980+ * get the early drop configuration
20981+ *
20982+ * Return: '0' on Success; error code otherwise.
20983+ */
20984+int dpni_get_rx_tc_early_drop(struct fsl_mc_io *mc_io,
20985+ uint32_t cmd_flags,
20986+ uint16_t token,
20987+ uint8_t tc_id,
20988+ uint64_t early_drop_iova);
20989+
20990+/**
20991+ * dpni_set_tx_tc_early_drop() - Set Tx traffic class early-drop configuration
20992+ * @mc_io: Pointer to MC portal's I/O object
20993+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
20994+ * @token: Token of DPNI object
20995+ * @tc_id: Traffic class selection (0-7)
20996+ * @early_drop_iova: I/O virtual address of 256 bytes DMA-able memory filled
20997+ * with the early-drop configuration by calling dpni_prepare_early_drop()
20998+ *
20999+ * warning: Before calling this function, call dpni_prepare_early_drop() to
21000+ * prepare the early_drop_iova parameter
21001+ *
21002+ * Return: '0' on Success; error code otherwise.
21003+ */
21004+int dpni_set_tx_tc_early_drop(struct fsl_mc_io *mc_io,
21005+ uint32_t cmd_flags,
21006+ uint16_t token,
21007+ uint8_t tc_id,
21008+ uint64_t early_drop_iova);
21009+
21010+/**
21011+ * dpni_get_tx_tc_early_drop() - Get Tx traffic class early-drop configuration
21012+ * @mc_io: Pointer to MC portal's I/O object
21013+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21014+ * @token: Token of DPNI object
21015+ * @tc_id: Traffic class selection (0-7)
21016+ * @early_drop_iova: I/O virtual address of 256 bytes DMA-able memory
21017+ *
21018+ * warning: After calling this function, call dpni_extract_early_drop() to
21019+ * get the early drop configuration
21020+ *
21021+ * Return: '0' on Success; error code otherwise.
21022+ */
21023+int dpni_get_tx_tc_early_drop(struct fsl_mc_io *mc_io,
21024+ uint32_t cmd_flags,
21025+ uint16_t token,
21026+ uint8_t tc_id,
21027+ uint64_t early_drop_iova);
21028+
21029+/**
21030+ * enum dpni_dest - DPNI destination types
21031+ * @DPNI_DEST_NONE: Unassigned destination; The queue is set in parked mode and
21032+ * does not generate FQDAN notifications; user is expected to
21033+ * dequeue from the queue based on polling or other user-defined
21034+ * method
21035+ * @DPNI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN
21036+ * notifications to the specified DPIO; user is expected to dequeue
21037+ * from the queue only after notification is received
21038+ * @DPNI_DEST_DPCON: The queue is set in schedule mode and does not generate
21039+ * FQDAN notifications, but is connected to the specified DPCON
21040+ * object; user is expected to dequeue from the DPCON channel
21041+ */
21042+enum dpni_dest {
21043+ DPNI_DEST_NONE = 0,
21044+ DPNI_DEST_DPIO = 1,
21045+ DPNI_DEST_DPCON = 2
21046+};
21047+
21048+/**
21049+ * struct dpni_dest_cfg - Structure representing DPNI destination parameters
21050+ * @dest_type: Destination type
21051+ * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type
21052+ * @priority: Priority selection within the DPIO or DPCON channel; valid values
21053+ * are 0-1 or 0-7, depending on the number of priorities in that
21054+ * channel; not relevant for 'DPNI_DEST_NONE' option
21055+ */
21056+struct dpni_dest_cfg {
21057+ enum dpni_dest dest_type;
21058+ int dest_id;
21059+ uint8_t priority;
21060+};
21061+
21062+/* DPNI congestion options */
21063+
21064+/**
21065+ * CSCN message is written to message_iova once entering a
21066+ * congestion state (see 'threshold_entry')
21067+ */
21068+#define DPNI_CONG_OPT_WRITE_MEM_ON_ENTER 0x00000001
21069+/**
21070+ * CSCN message is written to message_iova once exiting a
21071+ * congestion state (see 'threshold_exit')
21072+ */
21073+#define DPNI_CONG_OPT_WRITE_MEM_ON_EXIT 0x00000002
21074+/**
21075+ * CSCN write will attempt to allocate into a cache (coherent write);
21076+ * valid only if 'DPNI_CONG_OPT_WRITE_MEM_<X>' is selected
21077+ */
21078+#define DPNI_CONG_OPT_COHERENT_WRITE 0x00000004
21079+/**
21080+ * if 'dest_cfg.dest_type != DPNI_DEST_NONE' CSCN message is sent to
21081+ * DPIO/DPCON's WQ channel once entering a congestion state
21082+ * (see 'threshold_entry')
21083+ */
21084+#define DPNI_CONG_OPT_NOTIFY_DEST_ON_ENTER 0x00000008
21085+/**
21086+ * if 'dest_cfg.dest_type != DPNI_DEST_NONE' CSCN message is sent to
21087+ * DPIO/DPCON's WQ channel once exiting a congestion state
21088+ * (see 'threshold_exit')
21089+ */
21090+#define DPNI_CONG_OPT_NOTIFY_DEST_ON_EXIT 0x00000010
21091+/**
21092+ * if 'dest_cfg.dest_type != DPNI_DEST_NONE' when the CSCN is written to the
21093+ * sw-portal's DQRR, the DQRI interrupt is asserted immediately (if enabled)
21094+ */
21095+#define DPNI_CONG_OPT_INTR_COALESCING_DISABLED 0x00000020
21096+
21097+/**
21098+ * struct dpni_congestion_notification_cfg - congestion notification
21099+ * configuration
21100+ * @units: units type
21101+ * @threshold_entry: above this threshold we enter a congestion state.
21102+ * set it to '0' to disable it
21103+ * @threshold_exit: below this threshold we exit the congestion state.
21104+ * @message_ctx: The context that will be part of the CSCN message
21105+ * @message_iova: I/O virtual address (must be in DMA-able memory),
21106+ * must be 16B aligned; valid only if 'DPNI_CONG_OPT_WRITE_MEM_<X>' is
21107+ * contained in 'options'
21108+ * @dest_cfg: CSCN can be send to either DPIO or DPCON WQ channel
21109+ * @options: Mask of available options; use 'DPNI_CONG_OPT_<X>' values
21110+ */
21111+
21112+struct dpni_congestion_notification_cfg {
21113+ enum dpni_congestion_unit units;
21114+ uint32_t threshold_entry;
21115+ uint32_t threshold_exit;
21116+ uint64_t message_ctx;
21117+ uint64_t message_iova;
21118+ struct dpni_dest_cfg dest_cfg;
21119+ uint16_t options;
21120+};
21121+
21122+/**
21123+ * dpni_set_rx_tc_congestion_notification() - Set Rx traffic class congestion
21124+ * notification configuration
21125+ * @mc_io: Pointer to MC portal's I/O object
21126+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21127+ * @token: Token of DPNI object
21128+ * @tc_id: Traffic class selection (0-7)
21129+ * @cfg: congestion notification configuration
21130+ *
21131+ * Return: '0' on Success; error code otherwise.
21132+ */
21133+int dpni_set_rx_tc_congestion_notification(struct fsl_mc_io *mc_io,
21134+ uint32_t cmd_flags,
21135+ uint16_t token,
21136+ uint8_t tc_id,
21137+ const struct dpni_congestion_notification_cfg *cfg);
21138+
21139+/**
21140+ * dpni_get_rx_tc_congestion_notification() - Get Rx traffic class congestion
21141+ * notification configuration
21142+ * @mc_io: Pointer to MC portal's I/O object
21143+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21144+ * @token: Token of DPNI object
21145+ * @tc_id: Traffic class selection (0-7)
21146+ * @cfg: congestion notification configuration
21147+ *
21148+ * Return: '0' on Success; error code otherwise.
21149+ */
21150+int dpni_get_rx_tc_congestion_notification(struct fsl_mc_io *mc_io,
21151+ uint32_t cmd_flags,
21152+ uint16_t token,
21153+ uint8_t tc_id,
21154+ struct dpni_congestion_notification_cfg *cfg);
21155+
21156+/**
21157+ * dpni_set_tx_tc_congestion_notification() - Set Tx traffic class congestion
21158+ * notification configuration
21159+ * @mc_io: Pointer to MC portal's I/O object
21160+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21161+ * @token: Token of DPNI object
21162+ * @tc_id: Traffic class selection (0-7)
21163+ * @cfg: congestion notification configuration
21164+ *
21165+ * Return: '0' on Success; error code otherwise.
21166+ */
21167+int dpni_set_tx_tc_congestion_notification(struct fsl_mc_io *mc_io,
21168+ uint32_t cmd_flags,
21169+ uint16_t token,
21170+ uint8_t tc_id,
21171+ const struct dpni_congestion_notification_cfg *cfg);
21172+
21173+/**
21174+ * dpni_get_tx_tc_congestion_notification() - Get Tx traffic class congestion
21175+ * notification configuration
21176+ * @mc_io: Pointer to MC portal's I/O object
21177+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21178+ * @token: Token of DPNI object
21179+ * @tc_id: Traffic class selection (0-7)
21180+ * @cfg: congestion notification configuration
21181+ *
21182+ * Return: '0' on Success; error code otherwise.
21183+ */
21184+int dpni_get_tx_tc_congestion_notification(struct fsl_mc_io *mc_io,
21185+ uint32_t cmd_flags,
21186+ uint16_t token,
21187+ uint8_t tc_id,
21188+ struct dpni_congestion_notification_cfg *cfg);
21189+
21190+/**
21191+ * enum dpni_flc_type - DPNI FLC types
21192+ * @DPNI_FLC_USER_DEFINED: select the FLC to be used for user defined value
21193+ * @DPNI_FLC_STASH: select the FLC to be used for stash control
21194+ */
21195+enum dpni_flc_type {
21196+ DPNI_FLC_USER_DEFINED = 0,
21197+ DPNI_FLC_STASH = 1,
21198+};
21199+
21200+/**
21201+ * enum dpni_stash_size - DPNI FLC stashing size
21202+ * @DPNI_STASH_SIZE_0B: no stash
21203+ * @DPNI_STASH_SIZE_64B: stashes 64 bytes
21204+ * @DPNI_STASH_SIZE_128B: stashes 128 bytes
21205+ * @DPNI_STASH_SIZE_192B: stashes 192 bytes
21206+ */
21207+enum dpni_stash_size {
21208+ DPNI_STASH_SIZE_0B = 0,
21209+ DPNI_STASH_SIZE_64B = 1,
21210+ DPNI_STASH_SIZE_128B = 2,
21211+ DPNI_STASH_SIZE_192B = 3,
21212+};
21213+
21214+/* DPNI FLC stash options */
21215+
21216+/**
21217+ * stashes the whole annotation area (up to 192 bytes)
21218+ */
21219+#define DPNI_FLC_STASH_FRAME_ANNOTATION 0x00000001
21220+
21221+/**
21222+ * struct dpni_flc_cfg - Structure representing DPNI FLC configuration
21223+ * @flc_type: FLC type
21224+ * @options: Mask of available options;
21225+ * use 'DPNI_FLC_STASH_<X>' values
21226+ * @frame_data_size: Size of frame data to be stashed
21227+ * @flow_context_size: Size of flow context to be stashed
21228+ * @flow_context: 1. In case flc_type is 'DPNI_FLC_USER_DEFINED':
21229+ * this value will be provided in the frame descriptor
21230+ * (FD[FLC])
21231+ * 2. In case flc_type is 'DPNI_FLC_STASH':
21232+ * this value will be I/O virtual address of the
21233+ * flow-context;
21234+ * Must be cacheline-aligned and DMA-able memory
21235+ */
21236+struct dpni_flc_cfg {
21237+ enum dpni_flc_type flc_type;
21238+ uint32_t options;
21239+ enum dpni_stash_size frame_data_size;
21240+ enum dpni_stash_size flow_context_size;
21241+ uint64_t flow_context;
21242+};
21243+
21244+/**
21245+ * DPNI queue modification options
21246+ */
21247+
21248+/**
21249+ * Select to modify the user's context associated with the queue
21250+ */
21251+#define DPNI_QUEUE_OPT_USER_CTX 0x00000001
21252+/**
21253+ * Select to modify the queue's destination
21254+ */
21255+#define DPNI_QUEUE_OPT_DEST 0x00000002
21256+/** Select to modify the flow-context parameters;
21257+ * not applicable for Tx-conf/Err queues as the FD comes from the user
21258+ */
21259+#define DPNI_QUEUE_OPT_FLC 0x00000004
21260+/**
21261+ * Select to modify the queue's order preservation
21262+ */
21263+#define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008
21264+/* Select to modify the queue's tail-drop threshold */
21265+#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010
21266+
21267+/**
21268+ * struct dpni_queue_cfg - Structure representing queue configuration
21269+ * @options: Flags representing the suggested modifications to the queue;
21270+ * Use any combination of 'DPNI_QUEUE_OPT_<X>' flags
21271+ * @user_ctx: User context value provided in the frame descriptor of each
21272+ * dequeued frame; valid only if 'DPNI_QUEUE_OPT_USER_CTX'
21273+ * is contained in 'options'
21274+ * @dest_cfg: Queue destination parameters;
21275+ * valid only if 'DPNI_QUEUE_OPT_DEST' is contained in 'options'
21276+ * @flc_cfg: Flow context configuration; in case the TC's distribution
21277+ * is either NONE or HASH the FLC's settings of flow#0 are used.
21278+ * in the case of FS (flow-steering) the flow's FLC settings
21279+ * are used.
21280+ * valid only if 'DPNI_QUEUE_OPT_FLC' is contained in 'options'
21281+ * @order_preservation_en: enable/disable order preservation;
21282+ * valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained
21283+ * in 'options'
21284+ * @tail_drop_threshold: set the queue's tail drop threshold in bytes;
21285+ * '0' value disable the threshold; maximum value is 0xE000000;
21286+ * valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained
21287+ * in 'options'
21288+ */
21289+struct dpni_queue_cfg {
21290+ uint32_t options;
21291+ uint64_t user_ctx;
21292+ struct dpni_dest_cfg dest_cfg;
21293+ struct dpni_flc_cfg flc_cfg;
21294+ int order_preservation_en;
21295+ uint32_t tail_drop_threshold;
21296+};
21297+
21298+/**
21299+ * struct dpni_queue_attr - Structure representing queue attributes
21300+ * @user_ctx: User context value provided in the frame descriptor of each
21301+ * dequeued frame
21302+ * @dest_cfg: Queue destination configuration
21303+ * @flc_cfg: Flow context configuration
21304+ * @order_preservation_en: enable/disable order preservation
21305+ * @tail_drop_threshold: queue's tail drop threshold in bytes;
21306+ * @fqid: Virtual fqid value to be used for dequeue operations
21307+ */
21308+struct dpni_queue_attr {
21309+ uint64_t user_ctx;
21310+ struct dpni_dest_cfg dest_cfg;
21311+ struct dpni_flc_cfg flc_cfg;
21312+ int order_preservation_en;
21313+ uint32_t tail_drop_threshold;
21314+
21315+ uint32_t fqid;
21316+};
21317+
21318+/**
21319+ * DPNI Tx flow modification options
21320+ */
21321+
21322+/**
21323+ * Select to modify the settings for dedicate Tx confirmation/error
21324+ */
21325+#define DPNI_TX_FLOW_OPT_TX_CONF_ERROR 0x00000001
21326+/**
21327+ * Select to modify the L3 checksum generation setting
21328+ */
21329+#define DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN 0x00000010
21330+/**
21331+ * Select to modify the L4 checksum generation setting
21332+ */
21333+#define DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN 0x00000020
21334+
21335+/**
21336+ * struct dpni_tx_flow_cfg - Structure representing Tx flow configuration
21337+ * @options: Flags representing the suggested modifications to the Tx flow;
21338+ * Use any combination 'DPNI_TX_FLOW_OPT_<X>' flags
21339+ * @use_common_tx_conf_queue: Set to '1' to use the common (default) Tx
21340+ * confirmation and error queue; Set to '0' to use the private
21341+ * Tx confirmation and error queue; valid only if
21342+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' wasn't set at DPNI creation
21343+ * and 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in 'options'
21344+ * @l3_chksum_gen: Set to '1' to enable L3 checksum generation; '0' to disable;
21345+ * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in 'options'
21346+ * @l4_chksum_gen: Set to '1' to enable L4 checksum generation; '0' to disable;
21347+ * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in 'options'
21348+ */
21349+struct dpni_tx_flow_cfg {
21350+ uint32_t options;
21351+ int use_common_tx_conf_queue;
21352+ int l3_chksum_gen;
21353+ int l4_chksum_gen;
21354+};
21355+
21356+/**
21357+ * dpni_set_tx_flow() - Set Tx flow configuration
21358+ * @mc_io: Pointer to MC portal's I/O object
21359+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21360+ * @token: Token of DPNI object
21361+ * @flow_id: Provides (or returns) the sender's flow ID;
21362+ * for each new sender set (*flow_id) to 'DPNI_NEW_FLOW_ID' to generate
21363+ * a new flow_id; this ID should be used as the QDBIN argument
21364+ * in enqueue operations
21365+ * @cfg: Tx flow configuration
21366+ *
21367+ * Return: '0' on Success; Error code otherwise.
21368+ */
21369+int dpni_set_tx_flow(struct fsl_mc_io *mc_io,
21370+ uint32_t cmd_flags,
21371+ uint16_t token,
21372+ uint16_t *flow_id,
21373+ const struct dpni_tx_flow_cfg *cfg);
21374+
21375+/**
21376+ * struct dpni_tx_flow_attr - Structure representing Tx flow attributes
21377+ * @use_common_tx_conf_queue: '1' if using common (default) Tx confirmation and
21378+ * error queue; '0' if using private Tx confirmation and error queue
21379+ * @l3_chksum_gen: '1' if L3 checksum generation is enabled; '0' if disabled
21380+ * @l4_chksum_gen: '1' if L4 checksum generation is enabled; '0' if disabled
21381+ */
21382+struct dpni_tx_flow_attr {
21383+ int use_common_tx_conf_queue;
21384+ int l3_chksum_gen;
21385+ int l4_chksum_gen;
21386+};
21387+
21388+/**
21389+ * dpni_get_tx_flow() - Get Tx flow attributes
21390+ * @mc_io: Pointer to MC portal's I/O object
21391+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21392+ * @token: Token of DPNI object
21393+ * @flow_id: The sender's flow ID, as returned by the
21394+ * dpni_set_tx_flow() function
21395+ * @attr: Returned Tx flow attributes
21396+ *
21397+ * Return: '0' on Success; Error code otherwise.
21398+ */
21399+int dpni_get_tx_flow(struct fsl_mc_io *mc_io,
21400+ uint32_t cmd_flags,
21401+ uint16_t token,
21402+ uint16_t flow_id,
21403+ struct dpni_tx_flow_attr *attr);
21404+
21405+/**
21406+ * struct dpni_tx_conf_cfg - Structure representing Tx conf configuration
21407+ * @errors_only: Set to '1' to report back only error frames;
21408+ * Set to '0' to confirm transmission/error for all transmitted frames;
21409+ * @queue_cfg: Queue configuration
21410+ */
21411+struct dpni_tx_conf_cfg {
21412+ int errors_only;
21413+ struct dpni_queue_cfg queue_cfg;
21414+};
21415+
21416+/**
21417+ * dpni_set_tx_conf() - Set Tx confirmation and error queue configuration
21418+ * @mc_io: Pointer to MC portal's I/O object
21419+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21420+ * @token: Token of DPNI object
21421+ * @flow_id: The sender's flow ID, as returned by the
21422+ * dpni_set_tx_flow() function;
21423+ * use 'DPNI_COMMON_TX_CONF' for common tx-conf
21424+ * @cfg: Queue configuration
21425+ *
21426+ * If either 'DPNI_OPT_TX_CONF_DISABLED' or
21427+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation,
21428+ * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF';
21429+ * i.e. only serve the common tx-conf-err queue;
21430+ * if 'DPNI_OPT_TX_CONF_DISABLED' was selected, only error frames are reported
21431+ * back - successfully transmitted frames are not confirmed. Otherwise, all
21432+ * transmitted frames are sent for confirmation.
21433+ *
21434+ * Return: '0' on Success; Error code otherwise.
21435+ */
21436+int dpni_set_tx_conf(struct fsl_mc_io *mc_io,
21437+ uint32_t cmd_flags,
21438+ uint16_t token,
21439+ uint16_t flow_id,
21440+ const struct dpni_tx_conf_cfg *cfg);
21441+
21442+/**
21443+ * struct dpni_tx_conf_attr - Structure representing Tx conf attributes
21444+ * @errors_only: '1' if only error frames are reported back; '0' if all
21445+ * transmitted frames are confirmed
21446+ * @queue_attr: Queue attributes
21447+ */
21448+struct dpni_tx_conf_attr {
21449+ int errors_only;
21450+ struct dpni_queue_attr queue_attr;
21451+};
21452+
21453+/**
21454+ * dpni_get_tx_conf() - Get Tx confirmation and error queue attributes
21455+ * @mc_io: Pointer to MC portal's I/O object
21456+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21457+ * @token: Token of DPNI object
21458+ * @flow_id: The sender's flow ID, as returned by the
21459+ * dpni_set_tx_flow() function;
21460+ * use 'DPNI_COMMON_TX_CONF' for common tx-conf
21461+ * @attr: Returned tx-conf attributes
21462+ *
21463+ * If either 'DPNI_OPT_TX_CONF_DISABLED' or
21464+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation,
21465+ * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF';
21466+ * i.e. only serve the common tx-conf-err queue;
21467+ *
21468+ * Return: '0' on Success; Error code otherwise.
21469+ */
21470+int dpni_get_tx_conf(struct fsl_mc_io *mc_io,
21471+ uint32_t cmd_flags,
21472+ uint16_t token,
21473+ uint16_t flow_id,
21474+ struct dpni_tx_conf_attr *attr);
21475+
21476+/**
21477+ * dpni_set_tx_conf_congestion_notification() - Set Tx conf congestion
21478+ * notification configuration
21479+ * @mc_io: Pointer to MC portal's I/O object
21480+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21481+ * @token: Token of DPNI object
21482+ * @flow_id: The sender's flow ID, as returned by the
21483+ * dpni_set_tx_flow() function;
21484+ * use 'DPNI_COMMON_TX_CONF' for common tx-conf
21485+ * @cfg: congestion notification configuration
21486+ *
21487+ * If either 'DPNI_OPT_TX_CONF_DISABLED' or
21488+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation,
21489+ * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF';
21490+ * i.e. only serve the common tx-conf-err queue;
21491+ *
21492+ * Return: '0' on Success; error code otherwise.
21493+ */
21494+int dpni_set_tx_conf_congestion_notification(struct fsl_mc_io *mc_io,
21495+ uint32_t cmd_flags,
21496+ uint16_t token,
21497+ uint16_t flow_id,
21498+ const struct dpni_congestion_notification_cfg *cfg);
21499+
21500+/**
21501+ * dpni_get_tx_conf_congestion_notification() - Get Tx conf congestion
21502+ * notification configuration
21503+ * @mc_io: Pointer to MC portal's I/O object
21504+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21505+ * @token: Token of DPNI object
21506+ * @flow_id: The sender's flow ID, as returned by the
21507+ * dpni_set_tx_flow() function;
21508+ * use 'DPNI_COMMON_TX_CONF' for common tx-conf
21509+ * @cfg: congestion notification
21510+ *
21511+ * If either 'DPNI_OPT_TX_CONF_DISABLED' or
21512+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation,
21513+ * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF';
21514+ * i.e. only serve the common tx-conf-err queue;
21515+ *
21516+ * Return: '0' on Success; error code otherwise.
21517+ */
21518+int dpni_get_tx_conf_congestion_notification(struct fsl_mc_io *mc_io,
21519+ uint32_t cmd_flags,
21520+ uint16_t token,
21521+ uint16_t flow_id,
21522+ struct dpni_congestion_notification_cfg *cfg);
21523+
21524+/**
21525+ * dpni_set_tx_conf_revoke() - Tx confirmation revocation
21526+ * @mc_io: Pointer to MC portal's I/O object
21527+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21528+ * @token: Token of DPNI object
21529+ * @revoke: revoke or not
21530+ *
21531+ * This function is useful only when 'DPNI_OPT_TX_CONF_DISABLED' is not
21532+ * selected at DPNI creation.
21533+ * Calling this function with 'revoke' set to '1' disables all transmit
21534+ * confirmation (including the private confirmation queues), regardless of
21535+ * previous settings; Note that in this case, Tx error frames are still
21536+ * enqueued to the general transmit errors queue.
21537+ * Calling this function with 'revoke' set to '0' restores the previous
21538+ * settings for both general and private transmit confirmation.
21539+ *
21540+ * Return: '0' on Success; Error code otherwise.
21541+ */
21542+int dpni_set_tx_conf_revoke(struct fsl_mc_io *mc_io,
21543+ uint32_t cmd_flags,
21544+ uint16_t token,
21545+ int revoke);
21546+
21547+/**
21548+ * dpni_set_rx_flow() - Set Rx flow configuration
21549+ * @mc_io: Pointer to MC portal's I/O object
21550+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21551+ * @token: Token of DPNI object
21552+ * @tc_id: Traffic class selection (0-7);
21553+ * use 'DPNI_ALL_TCS' to set all TCs and all flows
21554+ * @flow_id: Rx flow id within the traffic class; use
21555+ * 'DPNI_ALL_TC_FLOWS' to set all flows within
21556+ * this tc_id; ignored if tc_id is set to
21557+ * 'DPNI_ALL_TCS';
21558+ * @cfg: Rx flow configuration
21559+ *
21560+ * Return: '0' on Success; Error code otherwise.
21561+ */
21562+int dpni_set_rx_flow(struct fsl_mc_io *mc_io,
21563+ uint32_t cmd_flags,
21564+ uint16_t token,
21565+ uint8_t tc_id,
21566+ uint16_t flow_id,
21567+ const struct dpni_queue_cfg *cfg);
21568+
21569+/**
21570+ * dpni_get_rx_flow() - Get Rx flow attributes
21571+ * @mc_io: Pointer to MC portal's I/O object
21572+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21573+ * @token: Token of DPNI object
21574+ * @tc_id: Traffic class selection (0-7)
21575+ * @flow_id: Rx flow id within the traffic class
21576+ * @attr: Returned Rx flow attributes
21577+ *
21578+ * Return: '0' on Success; Error code otherwise.
21579+ */
21580+int dpni_get_rx_flow(struct fsl_mc_io *mc_io,
21581+ uint32_t cmd_flags,
21582+ uint16_t token,
21583+ uint8_t tc_id,
21584+ uint16_t flow_id,
21585+ struct dpni_queue_attr *attr);
21586+
21587+/**
21588+ * dpni_set_rx_err_queue() - Set Rx error queue configuration
21589+ * @mc_io: Pointer to MC portal's I/O object
21590+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21591+ * @token: Token of DPNI object
21592+ * @cfg: Queue configuration
21593+ *
21594+ * Return: '0' on Success; Error code otherwise.
21595+ */
21596+int dpni_set_rx_err_queue(struct fsl_mc_io *mc_io,
21597+ uint32_t cmd_flags,
21598+ uint16_t token,
21599+ const struct dpni_queue_cfg *cfg);
21600+
21601+/**
21602+ * dpni_get_rx_err_queue() - Get Rx error queue attributes
21603+ * @mc_io: Pointer to MC portal's I/O object
21604+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21605+ * @token: Token of DPNI object
21606+ * @attr: Returned Queue attributes
21607+ *
21608+ * Return: '0' on Success; Error code otherwise.
21609+ */
21610+int dpni_get_rx_err_queue(struct fsl_mc_io *mc_io,
21611+ uint32_t cmd_flags,
21612+ uint16_t token,
21613+ struct dpni_queue_attr *attr);
21614+
21615+/**
21616+ * struct dpni_qos_tbl_cfg - Structure representing QOS table configuration
21617+ * @key_cfg_iova: I/O virtual address of 256 bytes DMA-able memory filled with
21618+ * key extractions to be used as the QoS criteria by calling
21619+ * dpni_prepare_key_cfg()
21620+ * @discard_on_miss: Set to '1' to discard frames in case of no match (miss);
21621+ * '0' to use the 'default_tc' in such cases
21622+ * @default_tc: Used in case of no-match and 'discard_on_miss'= 0
21623+ */
21624+struct dpni_qos_tbl_cfg {
21625+ uint64_t key_cfg_iova;
21626+ int discard_on_miss;
21627+ uint8_t default_tc;
21628+};
21629+
21630+/**
21631+ * dpni_set_qos_table() - Set QoS mapping table
21632+ * @mc_io: Pointer to MC portal's I/O object
21633+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21634+ * @token: Token of DPNI object
21635+ * @cfg: QoS table configuration
21636+ *
21637+ * This function and all QoS-related functions require that
21638+ *'max_tcs > 1' was set at DPNI creation.
21639+ *
21640+ * warning: Before calling this function, call dpni_prepare_key_cfg() to
21641+ * prepare the key_cfg_iova parameter
21642+ *
21643+ * Return: '0' on Success; Error code otherwise.
21644+ */
21645+int dpni_set_qos_table(struct fsl_mc_io *mc_io,
21646+ uint32_t cmd_flags,
21647+ uint16_t token,
21648+ const struct dpni_qos_tbl_cfg *cfg);
21649+
21650+/**
21651+ * struct dpni_rule_cfg - Rule configuration for table lookup
21652+ * @key_iova: I/O virtual address of the key (must be in DMA-able memory)
21653+ * @mask_iova: I/O virtual address of the mask (must be in DMA-able memory)
21654+ * @key_size: key and mask size (in bytes)
21655+ */
21656+struct dpni_rule_cfg {
21657+ uint64_t key_iova;
21658+ uint64_t mask_iova;
21659+ uint8_t key_size;
21660+};
21661+
21662+/**
21663+ * dpni_add_qos_entry() - Add QoS mapping entry (to select a traffic class)
21664+ * @mc_io: Pointer to MC portal's I/O object
21665+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21666+ * @token: Token of DPNI object
21667+ * @cfg: QoS rule to add
21668+ * @tc_id: Traffic class selection (0-7)
21669+ *
21670+ * Return: '0' on Success; Error code otherwise.
21671+ */
21672+int dpni_add_qos_entry(struct fsl_mc_io *mc_io,
21673+ uint32_t cmd_flags,
21674+ uint16_t token,
21675+ const struct dpni_rule_cfg *cfg,
21676+ uint8_t tc_id);
21677+
21678+/**
21679+ * dpni_remove_qos_entry() - Remove QoS mapping entry
21680+ * @mc_io: Pointer to MC portal's I/O object
21681+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21682+ * @token: Token of DPNI object
21683+ * @cfg: QoS rule to remove
21684+ *
21685+ * Return: '0' on Success; Error code otherwise.
21686+ */
21687+int dpni_remove_qos_entry(struct fsl_mc_io *mc_io,
21688+ uint32_t cmd_flags,
21689+ uint16_t token,
21690+ const struct dpni_rule_cfg *cfg);
21691+
21692+/**
21693+ * dpni_clear_qos_table() - Clear all QoS mapping entries
21694+ * @mc_io: Pointer to MC portal's I/O object
21695+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21696+ * @token: Token of DPNI object
21697+ *
21698+ * Following this function call, all frames are directed to
21699+ * the default traffic class (0)
21700+ *
21701+ * Return: '0' on Success; Error code otherwise.
21702+ */
21703+int dpni_clear_qos_table(struct fsl_mc_io *mc_io,
21704+ uint32_t cmd_flags,
21705+ uint16_t token);
21706+
21707+/**
21708+ * dpni_add_fs_entry() - Add Flow Steering entry for a specific traffic class
21709+ * (to select a flow ID)
21710+ * @mc_io: Pointer to MC portal's I/O object
21711+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21712+ * @token: Token of DPNI object
21713+ * @tc_id: Traffic class selection (0-7)
21714+ * @cfg: Flow steering rule to add
21715+ * @flow_id: Flow id selection (must be smaller than the
21716+ * distribution size of the traffic class)
21717+ *
21718+ * Return: '0' on Success; Error code otherwise.
21719+ */
21720+int dpni_add_fs_entry(struct fsl_mc_io *mc_io,
21721+ uint32_t cmd_flags,
21722+ uint16_t token,
21723+ uint8_t tc_id,
21724+ const struct dpni_rule_cfg *cfg,
21725+ uint16_t flow_id);
21726+
21727+/**
21728+ * dpni_remove_fs_entry() - Remove Flow Steering entry from a specific
21729+ * traffic class
21730+ * @mc_io: Pointer to MC portal's I/O object
21731+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21732+ * @token: Token of DPNI object
21733+ * @tc_id: Traffic class selection (0-7)
21734+ * @cfg: Flow steering rule to remove
21735+ *
21736+ * Return: '0' on Success; Error code otherwise.
21737+ */
21738+int dpni_remove_fs_entry(struct fsl_mc_io *mc_io,
21739+ uint32_t cmd_flags,
21740+ uint16_t token,
21741+ uint8_t tc_id,
21742+ const struct dpni_rule_cfg *cfg);
21743+
21744+/**
21745+ * dpni_clear_fs_entries() - Clear all Flow Steering entries of a specific
21746+ * traffic class
21747+ * @mc_io: Pointer to MC portal's I/O object
21748+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21749+ * @token: Token of DPNI object
21750+ * @tc_id: Traffic class selection (0-7)
21751+ *
21752+ * Return: '0' on Success; Error code otherwise.
21753+ */
21754+int dpni_clear_fs_entries(struct fsl_mc_io *mc_io,
21755+ uint32_t cmd_flags,
21756+ uint16_t token,
21757+ uint8_t tc_id);
21758+
21759+/**
21760+ * dpni_set_vlan_insertion() - Enable/disable VLAN insertion for egress frames
21761+ * @mc_io: Pointer to MC portal's I/O object
21762+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21763+ * @token: Token of DPNI object
21764+ * @en: Set to '1' to enable; '0' to disable
21765+ *
21766+ * Requires that the 'DPNI_OPT_VLAN_MANIPULATION' option is set
21767+ * at DPNI creation.
21768+ *
21769+ * Return: '0' on Success; Error code otherwise.
21770+ */
21771+int dpni_set_vlan_insertion(struct fsl_mc_io *mc_io,
21772+ uint32_t cmd_flags,
21773+ uint16_t token,
21774+ int en);
21775+
21776+/**
21777+ * dpni_set_vlan_removal() - Enable/disable VLAN removal for ingress frames
21778+ * @mc_io: Pointer to MC portal's I/O object
21779+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21780+ * @token: Token of DPNI object
21781+ * @en: Set to '1' to enable; '0' to disable
21782+ *
21783+ * Requires that the 'DPNI_OPT_VLAN_MANIPULATION' option is set
21784+ * at DPNI creation.
21785+ *
21786+ * Return: '0' on Success; Error code otherwise.
21787+ */
21788+int dpni_set_vlan_removal(struct fsl_mc_io *mc_io,
21789+ uint32_t cmd_flags,
21790+ uint16_t token,
21791+ int en);
21792+
21793+/**
21794+ * dpni_set_ipr() - Enable/disable IP reassembly of ingress frames
21795+ * @mc_io: Pointer to MC portal's I/O object
21796+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21797+ * @token: Token of DPNI object
21798+ * @en: Set to '1' to enable; '0' to disable
21799+ *
21800+ * Requires that the 'DPNI_OPT_IPR' option is set at DPNI creation.
21801+ *
21802+ * Return: '0' on Success; Error code otherwise.
21803+ */
21804+int dpni_set_ipr(struct fsl_mc_io *mc_io,
21805+ uint32_t cmd_flags,
21806+ uint16_t token,
21807+ int en);
21808+
21809+/**
21810+ * dpni_set_ipf() - Enable/disable IP fragmentation of egress frames
21811+ * @mc_io: Pointer to MC portal's I/O object
21812+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
21813+ * @token: Token of DPNI object
21814+ * @en: Set to '1' to enable; '0' to disable
21815+ *
21816+ * Requires that the 'DPNI_OPT_IPF' option is set at DPNI
21817+ * creation. Fragmentation is performed according to MTU value
21818+ * set by dpni_set_mtu() function
21819+ *
21820+ * Return: '0' on Success; Error code otherwise.
21821+ */
21822+int dpni_set_ipf(struct fsl_mc_io *mc_io,
21823+ uint32_t cmd_flags,
21824+ uint16_t token,
21825+ int en);
21826+
21827+#endif /* __FSL_DPNI_H */
21828diff --git a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h
21829new file mode 100644
21830index 0000000..c0f8af0
21831--- /dev/null
21832+++ b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h
21833@@ -0,0 +1,1058 @@
21834+/* Copyright 2013-2015 Freescale Semiconductor Inc.
21835+ *
21836+ * Redistribution and use in source and binary forms, with or without
21837+ * modification, are permitted provided that the following conditions are met:
21838+ * * Redistributions of source code must retain the above copyright
21839+ * notice, this list of conditions and the following disclaimer.
21840+ * * Redistributions in binary form must reproduce the above copyright
21841+ * notice, this list of conditions and the following disclaimer in the
21842+ * documentation and/or other materials provided with the distribution.
21843+ * * Neither the name of the above-listed copyright holders nor the
21844+ * names of any contributors may be used to endorse or promote products
21845+ * derived from this software without specific prior written permission.
21846+ *
21847+ *
21848+ * ALTERNATIVELY, this software may be distributed under the terms of the
21849+ * GNU General Public License ("GPL") as published by the Free Software
21850+ * Foundation, either version 2 of that License or (at your option) any
21851+ * later version.
21852+ *
21853+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21854+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21855+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21856+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
21857+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21858+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21859+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21860+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21861+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
21862+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
21863+ * POSSIBILITY OF SUCH DAMAGE.
21864+ */
21865+#ifndef _FSL_DPNI_CMD_H
21866+#define _FSL_DPNI_CMD_H
21867+
21868+/* DPNI Version */
21869+#define DPNI_VER_MAJOR 6
21870+#define DPNI_VER_MINOR 0
21871+
21872+/* Command IDs */
21873+#define DPNI_CMDID_OPEN 0x801
21874+#define DPNI_CMDID_CLOSE 0x800
21875+#define DPNI_CMDID_CREATE 0x901
21876+#define DPNI_CMDID_DESTROY 0x900
21877+
21878+#define DPNI_CMDID_ENABLE 0x002
21879+#define DPNI_CMDID_DISABLE 0x003
21880+#define DPNI_CMDID_GET_ATTR 0x004
21881+#define DPNI_CMDID_RESET 0x005
21882+#define DPNI_CMDID_IS_ENABLED 0x006
21883+
21884+#define DPNI_CMDID_SET_IRQ 0x010
21885+#define DPNI_CMDID_GET_IRQ 0x011
21886+#define DPNI_CMDID_SET_IRQ_ENABLE 0x012
21887+#define DPNI_CMDID_GET_IRQ_ENABLE 0x013
21888+#define DPNI_CMDID_SET_IRQ_MASK 0x014
21889+#define DPNI_CMDID_GET_IRQ_MASK 0x015
21890+#define DPNI_CMDID_GET_IRQ_STATUS 0x016
21891+#define DPNI_CMDID_CLEAR_IRQ_STATUS 0x017
21892+
21893+#define DPNI_CMDID_SET_POOLS 0x200
21894+#define DPNI_CMDID_GET_RX_BUFFER_LAYOUT 0x201
21895+#define DPNI_CMDID_SET_RX_BUFFER_LAYOUT 0x202
21896+#define DPNI_CMDID_GET_TX_BUFFER_LAYOUT 0x203
21897+#define DPNI_CMDID_SET_TX_BUFFER_LAYOUT 0x204
21898+#define DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT 0x205
21899+#define DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT 0x206
21900+#define DPNI_CMDID_SET_L3_CHKSUM_VALIDATION 0x207
21901+#define DPNI_CMDID_GET_L3_CHKSUM_VALIDATION 0x208
21902+#define DPNI_CMDID_SET_L4_CHKSUM_VALIDATION 0x209
21903+#define DPNI_CMDID_GET_L4_CHKSUM_VALIDATION 0x20A
21904+#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B
21905+#define DPNI_CMDID_SET_TX_CONF_REVOKE 0x20C
21906+
21907+#define DPNI_CMDID_GET_QDID 0x210
21908+#define DPNI_CMDID_GET_SP_INFO 0x211
21909+#define DPNI_CMDID_GET_TX_DATA_OFFSET 0x212
21910+#define DPNI_CMDID_GET_COUNTER 0x213
21911+#define DPNI_CMDID_SET_COUNTER 0x214
21912+#define DPNI_CMDID_GET_LINK_STATE 0x215
21913+#define DPNI_CMDID_SET_MAX_FRAME_LENGTH 0x216
21914+#define DPNI_CMDID_GET_MAX_FRAME_LENGTH 0x217
21915+#define DPNI_CMDID_SET_MTU 0x218
21916+#define DPNI_CMDID_GET_MTU 0x219
21917+#define DPNI_CMDID_SET_LINK_CFG 0x21A
21918+#define DPNI_CMDID_SET_TX_SHAPING 0x21B
21919+
21920+#define DPNI_CMDID_SET_MCAST_PROMISC 0x220
21921+#define DPNI_CMDID_GET_MCAST_PROMISC 0x221
21922+#define DPNI_CMDID_SET_UNICAST_PROMISC 0x222
21923+#define DPNI_CMDID_GET_UNICAST_PROMISC 0x223
21924+#define DPNI_CMDID_SET_PRIM_MAC 0x224
21925+#define DPNI_CMDID_GET_PRIM_MAC 0x225
21926+#define DPNI_CMDID_ADD_MAC_ADDR 0x226
21927+#define DPNI_CMDID_REMOVE_MAC_ADDR 0x227
21928+#define DPNI_CMDID_CLR_MAC_FILTERS 0x228
21929+
21930+#define DPNI_CMDID_SET_VLAN_FILTERS 0x230
21931+#define DPNI_CMDID_ADD_VLAN_ID 0x231
21932+#define DPNI_CMDID_REMOVE_VLAN_ID 0x232
21933+#define DPNI_CMDID_CLR_VLAN_FILTERS 0x233
21934+
21935+#define DPNI_CMDID_SET_RX_TC_DIST 0x235
21936+#define DPNI_CMDID_SET_TX_FLOW 0x236
21937+#define DPNI_CMDID_GET_TX_FLOW 0x237
21938+#define DPNI_CMDID_SET_RX_FLOW 0x238
21939+#define DPNI_CMDID_GET_RX_FLOW 0x239
21940+#define DPNI_CMDID_SET_RX_ERR_QUEUE 0x23A
21941+#define DPNI_CMDID_GET_RX_ERR_QUEUE 0x23B
21942+
21943+#define DPNI_CMDID_SET_RX_TC_POLICING 0x23E
21944+#define DPNI_CMDID_SET_RX_TC_EARLY_DROP 0x23F
21945+
21946+#define DPNI_CMDID_SET_QOS_TBL 0x240
21947+#define DPNI_CMDID_ADD_QOS_ENT 0x241
21948+#define DPNI_CMDID_REMOVE_QOS_ENT 0x242
21949+#define DPNI_CMDID_CLR_QOS_TBL 0x243
21950+#define DPNI_CMDID_ADD_FS_ENT 0x244
21951+#define DPNI_CMDID_REMOVE_FS_ENT 0x245
21952+#define DPNI_CMDID_CLR_FS_ENT 0x246
21953+#define DPNI_CMDID_SET_VLAN_INSERTION 0x247
21954+#define DPNI_CMDID_SET_VLAN_REMOVAL 0x248
21955+#define DPNI_CMDID_SET_IPR 0x249
21956+#define DPNI_CMDID_SET_IPF 0x24A
21957+
21958+#define DPNI_CMDID_SET_TX_SELECTION 0x250
21959+#define DPNI_CMDID_GET_RX_TC_POLICING 0x251
21960+#define DPNI_CMDID_GET_RX_TC_EARLY_DROP 0x252
21961+#define DPNI_CMDID_SET_RX_TC_CONGESTION_NOTIFICATION 0x253
21962+#define DPNI_CMDID_GET_RX_TC_CONGESTION_NOTIFICATION 0x254
21963+#define DPNI_CMDID_SET_TX_TC_CONGESTION_NOTIFICATION 0x255
21964+#define DPNI_CMDID_GET_TX_TC_CONGESTION_NOTIFICATION 0x256
21965+#define DPNI_CMDID_SET_TX_CONF 0x257
21966+#define DPNI_CMDID_GET_TX_CONF 0x258
21967+#define DPNI_CMDID_SET_TX_CONF_CONGESTION_NOTIFICATION 0x259
21968+#define DPNI_CMDID_GET_TX_CONF_CONGESTION_NOTIFICATION 0x25A
21969+#define DPNI_CMDID_SET_TX_TC_EARLY_DROP 0x25B
21970+#define DPNI_CMDID_GET_TX_TC_EARLY_DROP 0x25C
21971+
21972+/* cmd, param, offset, width, type, arg_name */
21973+#define DPNI_CMD_OPEN(cmd, dpni_id) \
21974+ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id)
21975+
21976+#define DPNI_PREP_EXTENDED_CFG(ext, cfg) \
21977+do { \
21978+ MC_PREP_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \
21979+ MC_PREP_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \
21980+ MC_PREP_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \
21981+ MC_PREP_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \
21982+ MC_PREP_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \
21983+ MC_PREP_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \
21984+ MC_PREP_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \
21985+ MC_PREP_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \
21986+ MC_PREP_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \
21987+ MC_PREP_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \
21988+ MC_PREP_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \
21989+ MC_PREP_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \
21990+ MC_PREP_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \
21991+ MC_PREP_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \
21992+ MC_PREP_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \
21993+ MC_PREP_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \
21994+ MC_PREP_OP(ext, 4, 0, 16, uint16_t, \
21995+ cfg->ipr_cfg.max_open_frames_ipv4); \
21996+ MC_PREP_OP(ext, 4, 16, 16, uint16_t, \
21997+ cfg->ipr_cfg.max_open_frames_ipv6); \
21998+ MC_PREP_OP(ext, 4, 32, 16, uint16_t, \
21999+ cfg->ipr_cfg.max_reass_frm_size); \
22000+ MC_PREP_OP(ext, 5, 0, 16, uint16_t, \
22001+ cfg->ipr_cfg.min_frag_size_ipv4); \
22002+ MC_PREP_OP(ext, 5, 16, 16, uint16_t, \
22003+ cfg->ipr_cfg.min_frag_size_ipv6); \
22004+} while (0)
22005+
22006+#define DPNI_EXT_EXTENDED_CFG(ext, cfg) \
22007+do { \
22008+ MC_EXT_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \
22009+ MC_EXT_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \
22010+ MC_EXT_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \
22011+ MC_EXT_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \
22012+ MC_EXT_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \
22013+ MC_EXT_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \
22014+ MC_EXT_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \
22015+ MC_EXT_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \
22016+ MC_EXT_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \
22017+ MC_EXT_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \
22018+ MC_EXT_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \
22019+ MC_EXT_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \
22020+ MC_EXT_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \
22021+ MC_EXT_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \
22022+ MC_EXT_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \
22023+ MC_EXT_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \
22024+ MC_EXT_OP(ext, 4, 0, 16, uint16_t, \
22025+ cfg->ipr_cfg.max_open_frames_ipv4); \
22026+ MC_EXT_OP(ext, 4, 16, 16, uint16_t, \
22027+ cfg->ipr_cfg.max_open_frames_ipv6); \
22028+ MC_EXT_OP(ext, 4, 32, 16, uint16_t, \
22029+ cfg->ipr_cfg.max_reass_frm_size); \
22030+ MC_EXT_OP(ext, 5, 0, 16, uint16_t, \
22031+ cfg->ipr_cfg.min_frag_size_ipv4); \
22032+ MC_EXT_OP(ext, 5, 16, 16, uint16_t, \
22033+ cfg->ipr_cfg.min_frag_size_ipv6); \
22034+} while (0)
22035+
22036+/* cmd, param, offset, width, type, arg_name */
22037+#define DPNI_CMD_CREATE(cmd, cfg) \
22038+do { \
22039+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->adv.max_tcs); \
22040+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->adv.max_senders); \
22041+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]); \
22042+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]); \
22043+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]); \
22044+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]); \
22045+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]); \
22046+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]); \
22047+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->adv.options); \
22048+ MC_CMD_OP(cmd, 2, 0, 8, uint8_t, cfg->adv.max_unicast_filters); \
22049+ MC_CMD_OP(cmd, 2, 8, 8, uint8_t, cfg->adv.max_multicast_filters); \
22050+ MC_CMD_OP(cmd, 2, 16, 8, uint8_t, cfg->adv.max_vlan_filters); \
22051+ MC_CMD_OP(cmd, 2, 24, 8, uint8_t, cfg->adv.max_qos_entries); \
22052+ MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \
22053+ MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \
22054+ MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \
22055+ MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \
22056+ MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \
22057+ MC_CMD_OP(cmd, 5, 0, 64, uint64_t, cfg->adv.ext_cfg_iova); \
22058+} while (0)
22059+
22060+/* cmd, param, offset, width, type, arg_name */
22061+#define DPNI_CMD_SET_POOLS(cmd, cfg) \
22062+do { \
22063+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \
22064+ MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \
22065+ MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \
22066+ MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \
22067+ MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \
22068+ MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \
22069+ MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \
22070+ MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \
22071+ MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \
22072+ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \
22073+ MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\
22074+ MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \
22075+ MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\
22076+ MC_CMD_OP(cmd, 1, 32, 32, int, cfg->pools[2].dpbp_id); \
22077+ MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->pools[2].buffer_size);\
22078+ MC_CMD_OP(cmd, 2, 0, 32, int, cfg->pools[3].dpbp_id); \
22079+ MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\
22080+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->pools[4].dpbp_id); \
22081+ MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\
22082+ MC_CMD_OP(cmd, 3, 0, 32, int, cfg->pools[5].dpbp_id); \
22083+ MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\
22084+ MC_CMD_OP(cmd, 3, 32, 32, int, cfg->pools[6].dpbp_id); \
22085+ MC_CMD_OP(cmd, 6, 0, 16, uint16_t, cfg->pools[6].buffer_size);\
22086+ MC_CMD_OP(cmd, 4, 0, 32, int, cfg->pools[7].dpbp_id); \
22087+ MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\
22088+} while (0)
22089+
22090+/* cmd, param, offset, width, type, arg_name */
22091+#define DPNI_RSP_IS_ENABLED(cmd, en) \
22092+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
22093+
22094+/* cmd, param, offset, width, type, arg_name */
22095+#define DPNI_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
22096+do { \
22097+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
22098+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
22099+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
22100+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
22101+} while (0)
22102+
22103+/* cmd, param, offset, width, type, arg_name */
22104+#define DPNI_CMD_GET_IRQ(cmd, irq_index) \
22105+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
22106+
22107+/* cmd, param, offset, width, type, arg_name */
22108+#define DPNI_RSP_GET_IRQ(cmd, type, irq_cfg) \
22109+do { \
22110+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
22111+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
22112+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
22113+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
22114+} while (0)
22115+
22116+/* cmd, param, offset, width, type, arg_name */
22117+#define DPNI_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \
22118+do { \
22119+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \
22120+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
22121+} while (0)
22122+
22123+/* cmd, param, offset, width, type, arg_name */
22124+#define DPNI_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
22125+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
22126+
22127+/* cmd, param, offset, width, type, arg_name */
22128+#define DPNI_RSP_GET_IRQ_ENABLE(cmd, en) \
22129+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en)
22130+
22131+/* cmd, param, offset, width, type, arg_name */
22132+#define DPNI_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
22133+do { \
22134+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
22135+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
22136+} while (0)
22137+
22138+/* cmd, param, offset, width, type, arg_name */
22139+#define DPNI_CMD_GET_IRQ_MASK(cmd, irq_index) \
22140+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
22141+
22142+/* cmd, param, offset, width, type, arg_name */
22143+#define DPNI_RSP_GET_IRQ_MASK(cmd, mask) \
22144+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
22145+
22146+/* cmd, param, offset, width, type, arg_name */
22147+#define DPNI_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
22148+do { \
22149+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
22150+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
22151+} while (0)
22152+
22153+/* cmd, param, offset, width, type, arg_name */
22154+#define DPNI_RSP_GET_IRQ_STATUS(cmd, status) \
22155+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
22156+
22157+/* cmd, param, offset, width, type, arg_name */
22158+#define DPNI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
22159+do { \
22160+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
22161+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
22162+} while (0)
22163+
22164+/* cmd, param, offset, width, type, arg_name */
22165+#define DPNI_CMD_GET_ATTR(cmd, attr) \
22166+ MC_CMD_OP(cmd, 6, 0, 64, uint64_t, attr->ext_cfg_iova)
22167+
22168+/* cmd, param, offset, width, type, arg_name */
22169+#define DPNI_RSP_GET_ATTR(cmd, attr) \
22170+do { \
22171+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\
22172+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->max_tcs); \
22173+ MC_RSP_OP(cmd, 0, 40, 8, uint8_t, attr->max_senders); \
22174+ MC_RSP_OP(cmd, 0, 48, 8, enum net_prot, attr->start_hdr); \
22175+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options); \
22176+ MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->max_unicast_filters); \
22177+ MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->max_multicast_filters);\
22178+ MC_RSP_OP(cmd, 2, 16, 8, uint8_t, attr->max_vlan_filters); \
22179+ MC_RSP_OP(cmd, 2, 24, 8, uint8_t, attr->max_qos_entries); \
22180+ MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->max_qos_key_size); \
22181+ MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->max_dist_key_size); \
22182+ MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \
22183+ MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \
22184+ MC_RSP_OP(cmd, 5, 32, 16, uint16_t, attr->version.major);\
22185+ MC_RSP_OP(cmd, 5, 48, 16, uint16_t, attr->version.minor);\
22186+} while (0)
22187+
22188+/* cmd, param, offset, width, type, arg_name */
22189+#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \
22190+do { \
22191+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->errors); \
22192+ MC_CMD_OP(cmd, 0, 32, 4, enum dpni_error_action, cfg->error_action); \
22193+ MC_CMD_OP(cmd, 0, 36, 1, int, cfg->set_frame_annotation); \
22194+} while (0)
22195+
22196+/* cmd, param, offset, width, type, arg_name */
22197+#define DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout) \
22198+do { \
22199+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
22200+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
22201+ MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
22202+ MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
22203+ MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
22204+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
22205+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
22206+} while (0)
22207+
22208+/* cmd, param, offset, width, type, arg_name */
22209+#define DPNI_CMD_SET_RX_BUFFER_LAYOUT(cmd, layout) \
22210+do { \
22211+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
22212+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
22213+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \
22214+ MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
22215+ MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
22216+ MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
22217+ MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
22218+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
22219+} while (0)
22220+
22221+/* cmd, param, offset, width, type, arg_name */
22222+#define DPNI_RSP_GET_TX_BUFFER_LAYOUT(cmd, layout) \
22223+do { \
22224+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
22225+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
22226+ MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
22227+ MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
22228+ MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
22229+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
22230+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
22231+} while (0)
22232+
22233+/* cmd, param, offset, width, type, arg_name */
22234+#define DPNI_CMD_SET_TX_BUFFER_LAYOUT(cmd, layout) \
22235+do { \
22236+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
22237+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
22238+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \
22239+ MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
22240+ MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
22241+ MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
22242+ MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
22243+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
22244+} while (0)
22245+
22246+/* cmd, param, offset, width, type, arg_name */
22247+#define DPNI_RSP_GET_TX_CONF_BUFFER_LAYOUT(cmd, layout) \
22248+do { \
22249+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
22250+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
22251+ MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
22252+ MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
22253+ MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
22254+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
22255+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
22256+} while (0)
22257+
22258+/* cmd, param, offset, width, type, arg_name */
22259+#define DPNI_CMD_SET_TX_CONF_BUFFER_LAYOUT(cmd, layout) \
22260+do { \
22261+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \
22262+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \
22263+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \
22264+ MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \
22265+ MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \
22266+ MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \
22267+ MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \
22268+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \
22269+} while (0)
22270+
22271+/* cmd, param, offset, width, type, arg_name */
22272+#define DPNI_CMD_SET_L3_CHKSUM_VALIDATION(cmd, en) \
22273+ MC_CMD_OP(cmd, 0, 0, 1, int, en)
22274+
22275+/* cmd, param, offset, width, type, arg_name */
22276+#define DPNI_RSP_GET_L3_CHKSUM_VALIDATION(cmd, en) \
22277+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
22278+
22279+/* cmd, param, offset, width, type, arg_name */
22280+#define DPNI_CMD_SET_L4_CHKSUM_VALIDATION(cmd, en) \
22281+ MC_CMD_OP(cmd, 0, 0, 1, int, en)
22282+
22283+/* cmd, param, offset, width, type, arg_name */
22284+#define DPNI_RSP_GET_L4_CHKSUM_VALIDATION(cmd, en) \
22285+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
22286+
22287+/* cmd, param, offset, width, type, arg_name */
22288+#define DPNI_RSP_GET_QDID(cmd, qdid) \
22289+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, qdid)
22290+
22291+/* cmd, param, offset, width, type, arg_name */
22292+#define DPNI_RSP_GET_SP_INFO(cmd, sp_info) \
22293+do { \
22294+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, sp_info->spids[0]); \
22295+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, sp_info->spids[1]); \
22296+} while (0)
22297+
22298+/* cmd, param, offset, width, type, arg_name */
22299+#define DPNI_RSP_GET_TX_DATA_OFFSET(cmd, data_offset) \
22300+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, data_offset)
22301+
22302+/* cmd, param, offset, width, type, arg_name */
22303+#define DPNI_CMD_GET_COUNTER(cmd, counter) \
22304+ MC_CMD_OP(cmd, 0, 0, 16, enum dpni_counter, counter)
22305+
22306+/* cmd, param, offset, width, type, arg_name */
22307+#define DPNI_RSP_GET_COUNTER(cmd, value) \
22308+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, value)
22309+
22310+/* cmd, param, offset, width, type, arg_name */
22311+#define DPNI_CMD_SET_COUNTER(cmd, counter, value) \
22312+do { \
22313+ MC_CMD_OP(cmd, 0, 0, 16, enum dpni_counter, counter); \
22314+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, value); \
22315+} while (0)
22316+
22317+/* cmd, param, offset, width, type, arg_name */
22318+#define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \
22319+do { \
22320+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate);\
22321+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options);\
22322+} while (0)
22323+
22324+/* cmd, param, offset, width, type, arg_name */
22325+#define DPNI_RSP_GET_LINK_STATE(cmd, state) \
22326+do { \
22327+ MC_RSP_OP(cmd, 0, 32, 1, int, state->up);\
22328+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, state->rate);\
22329+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\
22330+} while (0)
22331+
22332+/* cmd, param, offset, width, type, arg_name */
22333+#define DPNI_CMD_SET_TX_SHAPING(cmd, tx_shaper) \
22334+do { \
22335+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, tx_shaper->max_burst_size);\
22336+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, tx_shaper->rate_limit);\
22337+} while (0)
22338+
22339+/* cmd, param, offset, width, type, arg_name */
22340+#define DPNI_CMD_SET_MAX_FRAME_LENGTH(cmd, max_frame_length) \
22341+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, max_frame_length)
22342+
22343+/* cmd, param, offset, width, type, arg_name */
22344+#define DPNI_RSP_GET_MAX_FRAME_LENGTH(cmd, max_frame_length) \
22345+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, max_frame_length)
22346+
22347+/* cmd, param, offset, width, type, arg_name */
22348+#define DPNI_CMD_SET_MTU(cmd, mtu) \
22349+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, mtu)
22350+
22351+/* cmd, param, offset, width, type, arg_name */
22352+#define DPNI_RSP_GET_MTU(cmd, mtu) \
22353+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, mtu)
22354+
22355+/* cmd, param, offset, width, type, arg_name */
22356+#define DPNI_CMD_SET_MULTICAST_PROMISC(cmd, en) \
22357+ MC_CMD_OP(cmd, 0, 0, 1, int, en)
22358+
22359+/* cmd, param, offset, width, type, arg_name */
22360+#define DPNI_RSP_GET_MULTICAST_PROMISC(cmd, en) \
22361+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
22362+
22363+/* cmd, param, offset, width, type, arg_name */
22364+#define DPNI_CMD_SET_UNICAST_PROMISC(cmd, en) \
22365+ MC_CMD_OP(cmd, 0, 0, 1, int, en)
22366+
22367+/* cmd, param, offset, width, type, arg_name */
22368+#define DPNI_RSP_GET_UNICAST_PROMISC(cmd, en) \
22369+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
22370+
22371+/* cmd, param, offset, width, type, arg_name */
22372+#define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \
22373+do { \
22374+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \
22375+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \
22376+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \
22377+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \
22378+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \
22379+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \
22380+} while (0)
22381+
22382+/* cmd, param, offset, width, type, arg_name */
22383+#define DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr) \
22384+do { \
22385+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \
22386+ MC_RSP_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \
22387+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \
22388+ MC_RSP_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \
22389+ MC_RSP_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \
22390+ MC_RSP_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \
22391+} while (0)
22392+
22393+/* cmd, param, offset, width, type, arg_name */
22394+#define DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr) \
22395+do { \
22396+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \
22397+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \
22398+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \
22399+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \
22400+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \
22401+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \
22402+} while (0)
22403+
22404+/* cmd, param, offset, width, type, arg_name */
22405+#define DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr) \
22406+do { \
22407+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \
22408+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \
22409+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \
22410+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \
22411+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \
22412+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \
22413+} while (0)
22414+
22415+/* cmd, param, offset, width, type, arg_name */
22416+#define DPNI_CMD_CLEAR_MAC_FILTERS(cmd, unicast, multicast) \
22417+do { \
22418+ MC_CMD_OP(cmd, 0, 0, 1, int, unicast); \
22419+ MC_CMD_OP(cmd, 0, 1, 1, int, multicast); \
22420+} while (0)
22421+
22422+/* cmd, param, offset, width, type, arg_name */
22423+#define DPNI_CMD_SET_VLAN_FILTERS(cmd, en) \
22424+ MC_CMD_OP(cmd, 0, 0, 1, int, en)
22425+
22426+/* cmd, param, offset, width, type, arg_name */
22427+#define DPNI_CMD_ADD_VLAN_ID(cmd, vlan_id) \
22428+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, vlan_id)
22429+
22430+/* cmd, param, offset, width, type, arg_name */
22431+#define DPNI_CMD_REMOVE_VLAN_ID(cmd, vlan_id) \
22432+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, vlan_id)
22433+
22434+/* cmd, param, offset, width, type, arg_name */
22435+#define DPNI_CMD_SET_TX_SELECTION(cmd, cfg) \
22436+do { \
22437+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->tc_sched[0].delta_bandwidth);\
22438+ MC_CMD_OP(cmd, 0, 16, 4, enum dpni_tx_schedule_mode, \
22439+ cfg->tc_sched[0].mode); \
22440+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->tc_sched[1].delta_bandwidth);\
22441+ MC_CMD_OP(cmd, 0, 48, 4, enum dpni_tx_schedule_mode, \
22442+ cfg->tc_sched[1].mode); \
22443+ MC_CMD_OP(cmd, 1, 0, 16, uint16_t, cfg->tc_sched[2].delta_bandwidth);\
22444+ MC_CMD_OP(cmd, 1, 16, 4, enum dpni_tx_schedule_mode, \
22445+ cfg->tc_sched[2].mode); \
22446+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, cfg->tc_sched[3].delta_bandwidth);\
22447+ MC_CMD_OP(cmd, 1, 48, 4, enum dpni_tx_schedule_mode, \
22448+ cfg->tc_sched[3].mode); \
22449+ MC_CMD_OP(cmd, 2, 0, 16, uint16_t, cfg->tc_sched[4].delta_bandwidth);\
22450+ MC_CMD_OP(cmd, 2, 16, 4, enum dpni_tx_schedule_mode, \
22451+ cfg->tc_sched[4].mode); \
22452+ MC_CMD_OP(cmd, 2, 32, 16, uint16_t, cfg->tc_sched[5].delta_bandwidth);\
22453+ MC_CMD_OP(cmd, 2, 48, 4, enum dpni_tx_schedule_mode, \
22454+ cfg->tc_sched[5].mode); \
22455+ MC_CMD_OP(cmd, 3, 0, 16, uint16_t, cfg->tc_sched[6].delta_bandwidth);\
22456+ MC_CMD_OP(cmd, 3, 16, 4, enum dpni_tx_schedule_mode, \
22457+ cfg->tc_sched[6].mode); \
22458+ MC_CMD_OP(cmd, 3, 32, 16, uint16_t, cfg->tc_sched[7].delta_bandwidth);\
22459+ MC_CMD_OP(cmd, 3, 48, 4, enum dpni_tx_schedule_mode, \
22460+ cfg->tc_sched[7].mode); \
22461+} while (0)
22462+
22463+/* cmd, param, offset, width, type, arg_name */
22464+#define DPNI_CMD_SET_RX_TC_DIST(cmd, tc_id, cfg) \
22465+do { \
22466+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->dist_size); \
22467+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \
22468+ MC_CMD_OP(cmd, 0, 24, 4, enum dpni_dist_mode, cfg->dist_mode); \
22469+ MC_CMD_OP(cmd, 0, 28, 4, enum dpni_fs_miss_action, \
22470+ cfg->fs_cfg.miss_action); \
22471+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, cfg->fs_cfg.default_flow_id); \
22472+ MC_CMD_OP(cmd, 6, 0, 64, uint64_t, cfg->key_cfg_iova); \
22473+} while (0)
22474+
22475+/* cmd, param, offset, width, type, arg_name */
22476+#define DPNI_CMD_SET_TX_FLOW(cmd, flow_id, cfg) \
22477+do { \
22478+ MC_CMD_OP(cmd, 0, 43, 1, int, cfg->l3_chksum_gen);\
22479+ MC_CMD_OP(cmd, 0, 44, 1, int, cfg->l4_chksum_gen);\
22480+ MC_CMD_OP(cmd, 0, 45, 1, int, cfg->use_common_tx_conf_queue);\
22481+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id);\
22482+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
22483+} while (0)
22484+
22485+/* cmd, param, offset, width, type, arg_name */
22486+#define DPNI_RSP_SET_TX_FLOW(cmd, flow_id) \
22487+ MC_RSP_OP(cmd, 0, 48, 16, uint16_t, flow_id)
22488+
22489+/* cmd, param, offset, width, type, arg_name */
22490+#define DPNI_CMD_GET_TX_FLOW(cmd, flow_id) \
22491+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id)
22492+
22493+/* cmd, param, offset, width, type, arg_name */
22494+#define DPNI_RSP_GET_TX_FLOW(cmd, attr) \
22495+do { \
22496+ MC_RSP_OP(cmd, 0, 43, 1, int, attr->l3_chksum_gen);\
22497+ MC_RSP_OP(cmd, 0, 44, 1, int, attr->l4_chksum_gen);\
22498+ MC_RSP_OP(cmd, 0, 45, 1, int, attr->use_common_tx_conf_queue);\
22499+} while (0)
22500+
22501+/* cmd, param, offset, width, type, arg_name */
22502+#define DPNI_CMD_SET_RX_FLOW(cmd, tc_id, flow_id, cfg) \
22503+do { \
22504+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \
22505+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority);\
22506+ MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, cfg->dest_cfg.dest_type);\
22507+ MC_CMD_OP(cmd, 0, 42, 1, int, cfg->order_preservation_en);\
22508+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
22509+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \
22510+ MC_CMD_OP(cmd, 2, 16, 8, uint8_t, tc_id); \
22511+ MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \
22512+ MC_CMD_OP(cmd, 3, 0, 4, enum dpni_flc_type, cfg->flc_cfg.flc_type); \
22513+ MC_CMD_OP(cmd, 3, 4, 4, enum dpni_stash_size, \
22514+ cfg->flc_cfg.frame_data_size);\
22515+ MC_CMD_OP(cmd, 3, 8, 4, enum dpni_stash_size, \
22516+ cfg->flc_cfg.flow_context_size);\
22517+ MC_CMD_OP(cmd, 3, 32, 32, uint32_t, cfg->flc_cfg.options);\
22518+ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->flc_cfg.flow_context);\
22519+ MC_CMD_OP(cmd, 5, 0, 32, uint32_t, cfg->tail_drop_threshold); \
22520+} while (0)
22521+
22522+/* cmd, param, offset, width, type, arg_name */
22523+#define DPNI_CMD_GET_RX_FLOW(cmd, tc_id, flow_id) \
22524+do { \
22525+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \
22526+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
22527+} while (0)
22528+
22529+/* cmd, param, offset, width, type, arg_name */
22530+#define DPNI_RSP_GET_RX_FLOW(cmd, attr) \
22531+do { \
22532+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id); \
22533+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
22534+ MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, attr->dest_cfg.dest_type); \
22535+ MC_RSP_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\
22536+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx); \
22537+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tail_drop_threshold); \
22538+ MC_RSP_OP(cmd, 2, 32, 32, uint32_t, attr->fqid); \
22539+ MC_RSP_OP(cmd, 3, 0, 4, enum dpni_flc_type, attr->flc_cfg.flc_type); \
22540+ MC_RSP_OP(cmd, 3, 4, 4, enum dpni_stash_size, \
22541+ attr->flc_cfg.frame_data_size);\
22542+ MC_RSP_OP(cmd, 3, 8, 4, enum dpni_stash_size, \
22543+ attr->flc_cfg.flow_context_size);\
22544+ MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->flc_cfg.options);\
22545+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, attr->flc_cfg.flow_context);\
22546+} while (0)
22547+
22548+/* cmd, param, offset, width, type, arg_name */
22549+#define DPNI_CMD_SET_RX_ERR_QUEUE(cmd, cfg) \
22550+do { \
22551+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \
22552+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority);\
22553+ MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, cfg->dest_cfg.dest_type);\
22554+ MC_CMD_OP(cmd, 0, 42, 1, int, cfg->order_preservation_en);\
22555+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \
22556+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options); \
22557+ MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->tail_drop_threshold); \
22558+ MC_CMD_OP(cmd, 3, 0, 4, enum dpni_flc_type, cfg->flc_cfg.flc_type); \
22559+ MC_CMD_OP(cmd, 3, 4, 4, enum dpni_stash_size, \
22560+ cfg->flc_cfg.frame_data_size);\
22561+ MC_CMD_OP(cmd, 3, 8, 4, enum dpni_stash_size, \
22562+ cfg->flc_cfg.flow_context_size);\
22563+ MC_CMD_OP(cmd, 3, 32, 32, uint32_t, cfg->flc_cfg.options);\
22564+ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->flc_cfg.flow_context);\
22565+} while (0)
22566+
22567+/* cmd, param, offset, width, type, arg_name */
22568+#define DPNI_RSP_GET_RX_ERR_QUEUE(cmd, attr) \
22569+do { \
22570+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id); \
22571+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
22572+ MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, attr->dest_cfg.dest_type);\
22573+ MC_RSP_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\
22574+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx); \
22575+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tail_drop_threshold); \
22576+ MC_RSP_OP(cmd, 2, 32, 32, uint32_t, attr->fqid); \
22577+ MC_RSP_OP(cmd, 3, 0, 4, enum dpni_flc_type, attr->flc_cfg.flc_type); \
22578+ MC_RSP_OP(cmd, 3, 4, 4, enum dpni_stash_size, \
22579+ attr->flc_cfg.frame_data_size);\
22580+ MC_RSP_OP(cmd, 3, 8, 4, enum dpni_stash_size, \
22581+ attr->flc_cfg.flow_context_size);\
22582+ MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->flc_cfg.options);\
22583+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, attr->flc_cfg.flow_context);\
22584+} while (0)
22585+
22586+/* cmd, param, offset, width, type, arg_name */
22587+#define DPNI_CMD_SET_TX_CONF_REVOKE(cmd, revoke) \
22588+ MC_CMD_OP(cmd, 0, 0, 1, int, revoke)
22589+
22590+/* cmd, param, offset, width, type, arg_name */
22591+#define DPNI_CMD_SET_QOS_TABLE(cmd, cfg) \
22592+do { \
22593+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->default_tc); \
22594+ MC_CMD_OP(cmd, 0, 40, 1, int, cfg->discard_on_miss); \
22595+ MC_CMD_OP(cmd, 6, 0, 64, uint64_t, cfg->key_cfg_iova); \
22596+} while (0)
22597+
22598+/* cmd, param, offset, width, type, arg_name */
22599+#define DPNI_CMD_ADD_QOS_ENTRY(cmd, cfg, tc_id) \
22600+do { \
22601+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \
22602+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->key_size); \
22603+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->key_iova); \
22604+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->mask_iova); \
22605+} while (0)
22606+
22607+/* cmd, param, offset, width, type, arg_name */
22608+#define DPNI_CMD_REMOVE_QOS_ENTRY(cmd, cfg) \
22609+do { \
22610+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->key_size); \
22611+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->key_iova); \
22612+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->mask_iova); \
22613+} while (0)
22614+
22615+/* cmd, param, offset, width, type, arg_name */
22616+#define DPNI_CMD_ADD_FS_ENTRY(cmd, tc_id, cfg, flow_id) \
22617+do { \
22618+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \
22619+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
22620+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->key_size); \
22621+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->key_iova); \
22622+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->mask_iova); \
22623+} while (0)
22624+
22625+/* cmd, param, offset, width, type, arg_name */
22626+#define DPNI_CMD_REMOVE_FS_ENTRY(cmd, tc_id, cfg) \
22627+do { \
22628+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \
22629+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->key_size); \
22630+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->key_iova); \
22631+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->mask_iova); \
22632+} while (0)
22633+
22634+/* cmd, param, offset, width, type, arg_name */
22635+#define DPNI_CMD_CLEAR_FS_ENTRIES(cmd, tc_id) \
22636+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id)
22637+
22638+/* cmd, param, offset, width, type, arg_name */
22639+#define DPNI_CMD_SET_VLAN_INSERTION(cmd, en) \
22640+ MC_CMD_OP(cmd, 0, 0, 1, int, en)
22641+
22642+/* cmd, param, offset, width, type, arg_name */
22643+#define DPNI_CMD_SET_VLAN_REMOVAL(cmd, en) \
22644+ MC_CMD_OP(cmd, 0, 0, 1, int, en)
22645+
22646+/* cmd, param, offset, width, type, arg_name */
22647+#define DPNI_CMD_SET_IPR(cmd, en) \
22648+ MC_CMD_OP(cmd, 0, 0, 1, int, en)
22649+
22650+/* cmd, param, offset, width, type, arg_name */
22651+#define DPNI_CMD_SET_IPF(cmd, en) \
22652+ MC_CMD_OP(cmd, 0, 0, 1, int, en)
22653+
22654+/* cmd, param, offset, width, type, arg_name */
22655+#define DPNI_CMD_SET_RX_TC_POLICING(cmd, tc_id, cfg) \
22656+do { \
22657+ MC_CMD_OP(cmd, 0, 0, 4, enum dpni_policer_mode, cfg->mode); \
22658+ MC_CMD_OP(cmd, 0, 4, 4, enum dpni_policer_color, cfg->default_color); \
22659+ MC_CMD_OP(cmd, 0, 8, 4, enum dpni_policer_unit, cfg->units); \
22660+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \
22661+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, cfg->options); \
22662+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->cir); \
22663+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->cbs); \
22664+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->eir); \
22665+ MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->ebs);\
22666+} while (0)
22667+
22668+/* cmd, param, offset, width, type, arg_name */
22669+#define DPNI_CMD_GET_RX_TC_POLICING(cmd, tc_id) \
22670+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id)
22671+
22672+/* cmd, param, offset, width, type, arg_name */
22673+#define DPNI_RSP_GET_RX_TC_POLICING(cmd, cfg) \
22674+do { \
22675+ MC_RSP_OP(cmd, 0, 0, 4, enum dpni_policer_mode, cfg->mode); \
22676+ MC_RSP_OP(cmd, 0, 4, 4, enum dpni_policer_color, cfg->default_color); \
22677+ MC_RSP_OP(cmd, 0, 8, 4, enum dpni_policer_unit, cfg->units); \
22678+ MC_RSP_OP(cmd, 0, 32, 32, uint32_t, cfg->options); \
22679+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->cir); \
22680+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, cfg->cbs); \
22681+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, cfg->eir); \
22682+ MC_RSP_OP(cmd, 2, 32, 32, uint32_t, cfg->ebs);\
22683+} while (0)
22684+
22685+/* cmd, param, offset, width, type, arg_name */
22686+#define DPNI_PREP_EARLY_DROP(ext, cfg) \
22687+do { \
22688+ MC_PREP_OP(ext, 0, 0, 2, enum dpni_early_drop_mode, cfg->mode); \
22689+ MC_PREP_OP(ext, 0, 2, 2, \
22690+ enum dpni_congestion_unit, cfg->units); \
22691+ MC_PREP_OP(ext, 0, 32, 32, uint32_t, cfg->tail_drop_threshold); \
22692+ MC_PREP_OP(ext, 1, 0, 8, uint8_t, cfg->green.drop_probability); \
22693+ MC_PREP_OP(ext, 2, 0, 64, uint64_t, cfg->green.max_threshold); \
22694+ MC_PREP_OP(ext, 3, 0, 64, uint64_t, cfg->green.min_threshold); \
22695+ MC_PREP_OP(ext, 5, 0, 8, uint8_t, cfg->yellow.drop_probability);\
22696+ MC_PREP_OP(ext, 6, 0, 64, uint64_t, cfg->yellow.max_threshold); \
22697+ MC_PREP_OP(ext, 7, 0, 64, uint64_t, cfg->yellow.min_threshold); \
22698+ MC_PREP_OP(ext, 9, 0, 8, uint8_t, cfg->red.drop_probability); \
22699+ MC_PREP_OP(ext, 10, 0, 64, uint64_t, cfg->red.max_threshold); \
22700+ MC_PREP_OP(ext, 11, 0, 64, uint64_t, cfg->red.min_threshold); \
22701+} while (0)
22702+
22703+/* cmd, param, offset, width, type, arg_name */
22704+#define DPNI_EXT_EARLY_DROP(ext, cfg) \
22705+do { \
22706+ MC_EXT_OP(ext, 0, 0, 2, enum dpni_early_drop_mode, cfg->mode); \
22707+ MC_EXT_OP(ext, 0, 2, 2, \
22708+ enum dpni_congestion_unit, cfg->units); \
22709+ MC_EXT_OP(ext, 0, 32, 32, uint32_t, cfg->tail_drop_threshold); \
22710+ MC_EXT_OP(ext, 1, 0, 8, uint8_t, cfg->green.drop_probability); \
22711+ MC_EXT_OP(ext, 2, 0, 64, uint64_t, cfg->green.max_threshold); \
22712+ MC_EXT_OP(ext, 3, 0, 64, uint64_t, cfg->green.min_threshold); \
22713+ MC_EXT_OP(ext, 5, 0, 8, uint8_t, cfg->yellow.drop_probability);\
22714+ MC_EXT_OP(ext, 6, 0, 64, uint64_t, cfg->yellow.max_threshold); \
22715+ MC_EXT_OP(ext, 7, 0, 64, uint64_t, cfg->yellow.min_threshold); \
22716+ MC_EXT_OP(ext, 9, 0, 8, uint8_t, cfg->red.drop_probability); \
22717+ MC_EXT_OP(ext, 10, 0, 64, uint64_t, cfg->red.max_threshold); \
22718+ MC_EXT_OP(ext, 11, 0, 64, uint64_t, cfg->red.min_threshold); \
22719+} while (0)
22720+
22721+/* cmd, param, offset, width, type, arg_name */
22722+#define DPNI_CMD_SET_RX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova) \
22723+do { \
22724+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \
22725+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, early_drop_iova); \
22726+} while (0)
22727+
22728+/* cmd, param, offset, width, type, arg_name */
22729+#define DPNI_CMD_GET_RX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova) \
22730+do { \
22731+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \
22732+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, early_drop_iova); \
22733+} while (0)
22734+
22735+/* cmd, param, offset, width, type, arg_name */
22736+#define DPNI_CMD_SET_TX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova) \
22737+do { \
22738+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \
22739+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, early_drop_iova); \
22740+} while (0)
22741+
22742+/* cmd, param, offset, width, type, arg_name */
22743+#define DPNI_CMD_GET_TX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova) \
22744+do { \
22745+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \
22746+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, early_drop_iova); \
22747+} while (0)
22748+
22749+#define DPNI_CMD_SET_RX_TC_CONGESTION_NOTIFICATION(cmd, tc_id, cfg) \
22750+do { \
22751+ MC_CMD_OP(cmd, 0, 0, 2, enum dpni_congestion_unit, cfg->units); \
22752+ MC_CMD_OP(cmd, 0, 4, 4, enum dpni_dest, cfg->dest_cfg.dest_type); \
22753+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \
22754+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->dest_cfg.priority); \
22755+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->threshold_entry); \
22756+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->threshold_exit); \
22757+ MC_CMD_OP(cmd, 2, 0, 16, uint16_t, cfg->options); \
22758+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->dest_cfg.dest_id); \
22759+ MC_CMD_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx); \
22760+ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova); \
22761+} while (0)
22762+
22763+#define DPNI_CMD_GET_RX_TC_CONGESTION_NOTIFICATION(cmd, tc_id) \
22764+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id)
22765+
22766+#define DPNI_RSP_GET_RX_TC_CONGESTION_NOTIFICATION(cmd, cfg) \
22767+do { \
22768+ MC_RSP_OP(cmd, 0, 0, 2, enum dpni_congestion_unit, cfg->units); \
22769+ MC_RSP_OP(cmd, 0, 4, 4, enum dpni_dest, cfg->dest_cfg.dest_type); \
22770+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, cfg->dest_cfg.priority); \
22771+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->threshold_entry); \
22772+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, cfg->threshold_exit); \
22773+ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, cfg->options); \
22774+ MC_RSP_OP(cmd, 2, 32, 32, int, cfg->dest_cfg.dest_id); \
22775+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx); \
22776+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova); \
22777+} while (0)
22778+
22779+#define DPNI_CMD_SET_TX_TC_CONGESTION_NOTIFICATION(cmd, tc_id, cfg) \
22780+do { \
22781+ MC_CMD_OP(cmd, 0, 0, 2, enum dpni_congestion_unit, cfg->units); \
22782+ MC_CMD_OP(cmd, 0, 4, 4, enum dpni_dest, cfg->dest_cfg.dest_type); \
22783+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \
22784+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->dest_cfg.priority); \
22785+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->threshold_entry); \
22786+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->threshold_exit); \
22787+ MC_CMD_OP(cmd, 2, 0, 16, uint16_t, cfg->options); \
22788+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->dest_cfg.dest_id); \
22789+ MC_CMD_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx); \
22790+ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova); \
22791+} while (0)
22792+
22793+#define DPNI_CMD_GET_TX_TC_CONGESTION_NOTIFICATION(cmd, tc_id) \
22794+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id)
22795+
22796+#define DPNI_RSP_GET_TX_TC_CONGESTION_NOTIFICATION(cmd, cfg) \
22797+do { \
22798+ MC_RSP_OP(cmd, 0, 0, 2, enum dpni_congestion_unit, cfg->units); \
22799+ MC_RSP_OP(cmd, 0, 4, 4, enum dpni_dest, cfg->dest_cfg.dest_type); \
22800+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, cfg->dest_cfg.priority); \
22801+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->threshold_entry); \
22802+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, cfg->threshold_exit); \
22803+ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, cfg->options); \
22804+ MC_RSP_OP(cmd, 2, 32, 32, int, cfg->dest_cfg.dest_id); \
22805+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx); \
22806+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova); \
22807+} while (0)
22808+
22809+#define DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg) \
22810+do { \
22811+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->queue_cfg.dest_cfg.priority); \
22812+ MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \
22813+ cfg->queue_cfg.dest_cfg.dest_type); \
22814+ MC_CMD_OP(cmd, 0, 42, 1, int, cfg->errors_only); \
22815+ MC_CMD_OP(cmd, 0, 46, 1, int, cfg->queue_cfg.order_preservation_en); \
22816+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
22817+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->queue_cfg.user_ctx); \
22818+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->queue_cfg.options); \
22819+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->queue_cfg.dest_cfg.dest_id); \
22820+ MC_CMD_OP(cmd, 3, 0, 32, uint32_t, \
22821+ cfg->queue_cfg.tail_drop_threshold); \
22822+ MC_CMD_OP(cmd, 4, 0, 4, enum dpni_flc_type, \
22823+ cfg->queue_cfg.flc_cfg.flc_type); \
22824+ MC_CMD_OP(cmd, 4, 4, 4, enum dpni_stash_size, \
22825+ cfg->queue_cfg.flc_cfg.frame_data_size); \
22826+ MC_CMD_OP(cmd, 4, 8, 4, enum dpni_stash_size, \
22827+ cfg->queue_cfg.flc_cfg.flow_context_size); \
22828+ MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->queue_cfg.flc_cfg.options); \
22829+ MC_CMD_OP(cmd, 5, 0, 64, uint64_t, \
22830+ cfg->queue_cfg.flc_cfg.flow_context); \
22831+} while (0)
22832+
22833+#define DPNI_CMD_GET_TX_CONF(cmd, flow_id) \
22834+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id)
22835+
22836+#define DPNI_RSP_GET_TX_CONF(cmd, attr) \
22837+do { \
22838+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \
22839+ attr->queue_attr.dest_cfg.priority); \
22840+ MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \
22841+ attr->queue_attr.dest_cfg.dest_type); \
22842+ MC_RSP_OP(cmd, 0, 42, 1, int, attr->errors_only); \
22843+ MC_RSP_OP(cmd, 0, 46, 1, int, \
22844+ attr->queue_attr.order_preservation_en); \
22845+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->queue_attr.user_ctx); \
22846+ MC_RSP_OP(cmd, 2, 32, 32, int, attr->queue_attr.dest_cfg.dest_id); \
22847+ MC_RSP_OP(cmd, 3, 0, 32, uint32_t, \
22848+ attr->queue_attr.tail_drop_threshold); \
22849+ MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->queue_attr.fqid); \
22850+ MC_RSP_OP(cmd, 4, 0, 4, enum dpni_flc_type, \
22851+ attr->queue_attr.flc_cfg.flc_type); \
22852+ MC_RSP_OP(cmd, 4, 4, 4, enum dpni_stash_size, \
22853+ attr->queue_attr.flc_cfg.frame_data_size); \
22854+ MC_RSP_OP(cmd, 4, 8, 4, enum dpni_stash_size, \
22855+ attr->queue_attr.flc_cfg.flow_context_size); \
22856+ MC_RSP_OP(cmd, 4, 32, 32, uint32_t, attr->queue_attr.flc_cfg.options); \
22857+ MC_RSP_OP(cmd, 5, 0, 64, uint64_t, \
22858+ attr->queue_attr.flc_cfg.flow_context); \
22859+} while (0)
22860+
22861+#define DPNI_CMD_SET_TX_CONF_CONGESTION_NOTIFICATION(cmd, flow_id, cfg) \
22862+do { \
22863+ MC_CMD_OP(cmd, 0, 0, 2, enum dpni_congestion_unit, cfg->units); \
22864+ MC_CMD_OP(cmd, 0, 4, 4, enum dpni_dest, cfg->dest_cfg.dest_type); \
22865+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->dest_cfg.priority); \
22866+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \
22867+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->threshold_entry); \
22868+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->threshold_exit); \
22869+ MC_CMD_OP(cmd, 2, 0, 16, uint16_t, cfg->options); \
22870+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->dest_cfg.dest_id); \
22871+ MC_CMD_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx); \
22872+ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova); \
22873+} while (0)
22874+
22875+#define DPNI_CMD_GET_TX_CONF_CONGESTION_NOTIFICATION(cmd, flow_id) \
22876+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id)
22877+
22878+#define DPNI_RSP_GET_TX_CONF_CONGESTION_NOTIFICATION(cmd, cfg) \
22879+do { \
22880+ MC_RSP_OP(cmd, 0, 0, 2, enum dpni_congestion_unit, cfg->units); \
22881+ MC_RSP_OP(cmd, 0, 4, 4, enum dpni_dest, cfg->dest_cfg.dest_type); \
22882+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, cfg->dest_cfg.priority); \
22883+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->threshold_entry); \
22884+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, cfg->threshold_exit); \
22885+ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, cfg->options); \
22886+ MC_RSP_OP(cmd, 2, 32, 32, int, cfg->dest_cfg.dest_id); \
22887+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx); \
22888+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova); \
22889+} while (0)
22890+
22891+#endif /* _FSL_DPNI_CMD_H */
22892diff --git a/drivers/net/dpaa2/mc/fsl_dprc.h b/drivers/net/dpaa2/mc/fsl_dprc.h
22893new file mode 100644
22894index 0000000..c831f46
22895--- /dev/null
22896+++ b/drivers/net/dpaa2/mc/fsl_dprc.h
22897@@ -0,0 +1,1032 @@
22898+/* Copyright 2013-2015 Freescale Semiconductor Inc.
22899+ *
22900+ * Redistribution and use in source and binary forms, with or without
22901+ * modification, are permitted provided that the following conditions are met:
22902+ * * Redistributions of source code must retain the above copyright
22903+ * notice, this list of conditions and the following disclaimer.
22904+ * * Redistributions in binary form must reproduce the above copyright
22905+ * notice, this list of conditions and the following disclaimer in the
22906+ * documentation and/or other materials provided with the distribution.
22907+ * * Neither the name of the above-listed copyright holders nor the
22908+ * names of any contributors may be used to endorse or promote products
22909+ * derived from this software without specific prior written permission.
22910+ *
22911+ *
22912+ * ALTERNATIVELY, this software may be distributed under the terms of the
22913+ * GNU General Public License ("GPL") as published by the Free Software
22914+ * Foundation, either version 2 of that License or (at your option) any
22915+ * later version.
22916+ *
22917+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22918+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22919+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22920+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
22921+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22922+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22923+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22924+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22925+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22926+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
22927+ * POSSIBILITY OF SUCH DAMAGE.
22928+ */
22929+#ifndef _FSL_DPRC_H
22930+#define _FSL_DPRC_H
22931+
22932+/* Data Path Resource Container API
22933+ * Contains DPRC API for managing and querying DPAA resources
22934+ */
22935+
22936+struct fsl_mc_io;
22937+
22938+/**
22939+ * Set this value as the icid value in dprc_cfg structure when creating a
22940+ * container, in case the ICID is not selected by the user and should be
22941+ * allocated by the DPRC from the pool of ICIDs.
22942+ */
22943+#define DPRC_GET_ICID_FROM_POOL (uint16_t)(~(0))
22944+
22945+/**
22946+ * Set this value as the portal_id value in dprc_cfg structure when creating a
22947+ * container, in case the portal ID is not specifically selected by the
22948+ * user and should be allocated by the DPRC from the pool of portal ids.
22949+ */
22950+#define DPRC_GET_PORTAL_ID_FROM_POOL (int)(~(0))
22951+
22952+/**
22953+ * dprc_get_container_id() - Get container ID associated with a given portal.
22954+ * @mc_io: Pointer to MC portal's I/O object
22955+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
22956+ * @container_id: Requested container ID
22957+ *
22958+ * Return: '0' on Success; Error code otherwise.
22959+ */
22960+int dprc_get_container_id(struct fsl_mc_io *mc_io,
22961+ uint32_t cmd_flags,
22962+ int *container_id);
22963+
22964+/**
22965+ * dprc_open() - Open DPRC object for use
22966+ * @mc_io: Pointer to MC portal's I/O object
22967+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
22968+ * @container_id: Container ID to open
22969+ * @token: Returned token of DPRC object
22970+ *
22971+ * Return: '0' on Success; Error code otherwise.
22972+ *
22973+ * @warning Required before any operation on the object.
22974+ */
22975+int dprc_open(struct fsl_mc_io *mc_io,
22976+ uint32_t cmd_flags,
22977+ int container_id,
22978+ uint16_t *token);
22979+
22980+/**
22981+ * dprc_close() - Close the control session of the object
22982+ * @mc_io: Pointer to MC portal's I/O object
22983+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
22984+ * @token: Token of DPRC object
22985+ *
22986+ * After this function is called, no further operations are
22987+ * allowed on the object without opening a new control session.
22988+ *
22989+ * Return: '0' on Success; Error code otherwise.
22990+ */
22991+int dprc_close(struct fsl_mc_io *mc_io,
22992+ uint32_t cmd_flags,
22993+ uint16_t token);
22994+
22995+/**
22996+ * Container general options
22997+ *
22998+ * These options may be selected at container creation by the container creator
22999+ * and can be retrieved using dprc_get_attributes()
23000+ */
23001+
23002+/**
23003+ * Spawn Policy Option allowed - Indicates that the new container is allowed
23004+ * to spawn and have its own child containers.
23005+ */
23006+#define DPRC_CFG_OPT_SPAWN_ALLOWED 0x00000001
23007+
23008+/**
23009+ * General Container allocation policy - Indicates that the new container is
23010+ * allowed to allocate requested resources from its parent container; if not
23011+ * set, the container is only allowed to use resources in its own pools; Note
23012+ * that this is a container's global policy, but the parent container may
23013+ * override it and set specific quota per resource type.
23014+ */
23015+#define DPRC_CFG_OPT_ALLOC_ALLOWED 0x00000002
23016+
23017+/**
23018+ * Object initialization allowed - software context associated with this
23019+ * container is allowed to invoke object initialization operations.
23020+ */
23021+#define DPRC_CFG_OPT_OBJ_CREATE_ALLOWED 0x00000004
23022+
23023+/**
23024+ * Topology change allowed - software context associated with this
23025+ * container is allowed to invoke topology operations, such as attach/detach
23026+ * of network objects.
23027+ */
23028+#define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED 0x00000008
23029+
23030+/**
23031+ * AIOP - Indicates that container belongs to AIOP.
23032+ */
23033+#define DPRC_CFG_OPT_AIOP 0x00000020
23034+
23035+/**
23036+ * IRQ Config - Indicates that the container allowed to configure its IRQs.
23037+ */
23038+#define DPRC_CFG_OPT_IRQ_CFG_ALLOWED 0x00000040
23039+
23040+/**
23041+ * struct dprc_cfg - Container configuration options
23042+ * @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free
23043+ * ICID value is allocated by the DPRC
23044+ * @portal_id: Portal ID; if set to 'DPRC_GET_PORTAL_ID_FROM_POOL', a free
23045+ * portal ID is allocated by the DPRC
23046+ * @options: Combination of 'DPRC_CFG_OPT_<X>' options
23047+ * @label: Object's label
23048+ */
23049+struct dprc_cfg {
23050+ uint16_t icid;
23051+ int portal_id;
23052+ uint64_t options;
23053+ char label[16];
23054+};
23055+
23056+/**
23057+ * dprc_create_container() - Create child container
23058+ * @mc_io: Pointer to MC portal's I/O object
23059+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23060+ * @token: Token of DPRC object
23061+ * @cfg: Child container configuration
23062+ * @child_container_id: Returned child container ID
23063+ * @child_portal_offset: Returned child portal offset from MC portal base
23064+ *
23065+ *
23066+ * Return: '0' on Success; Error code otherwise.
23067+ */
23068+int dprc_create_container(struct fsl_mc_io *mc_io,
23069+ uint32_t cmd_flags,
23070+ uint16_t token,
23071+ struct dprc_cfg *cfg,
23072+ int *child_container_id,
23073+ uint64_t *child_portal_offset);
23074+
23075+/**
23076+ * dprc_destroy_container() - Destroy child container.
23077+ * @mc_io: Pointer to MC portal's I/O object
23078+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23079+ * @token: Token of DPRC object
23080+ * @child_container_id: ID of the container to destroy
23081+ *
23082+ * This function terminates the child container, so following this call the
23083+ * child container ID becomes invalid.
23084+ *
23085+ * Notes:
23086+ * - All resources and objects of the destroyed container are returned to the
23087+ * parent container or destroyed if were created be the destroyed container.
23088+ * - This function destroy all the child containers of the specified
23089+ * container prior to destroying the container itself.
23090+ *
23091+ * warning: Only the parent container is allowed to destroy a child policy
23092+ * Container 0 can't be destroyed
23093+ *
23094+ * Return: '0' on Success; Error code otherwise.
23095+ *
23096+ */
23097+int dprc_destroy_container(struct fsl_mc_io *mc_io,
23098+ uint32_t cmd_flags,
23099+ uint16_t token,
23100+ int child_container_id);
23101+
23102+/**
23103+ * dprc_reset_container - Reset child container.
23104+ * @mc_io: Pointer to MC portal's I/O object
23105+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23106+ * @token: Token of DPRC object
23107+ * @child_container_id: ID of the container to reset
23108+ *
23109+ * In case a software context crashes or becomes non-responsive, the parent
23110+ * may wish to reset its resources container before the software context is
23111+ * restarted.
23112+ *
23113+ * This routine informs all objects assigned to the child container that the
23114+ * container is being reset, so they may perform any cleanup operations that are
23115+ * needed. All objects handles that were owned by the child container shall be
23116+ * closed.
23117+ *
23118+ * Note that such request may be submitted even if the child software context
23119+ * has not crashed, but the resulting object cleanup operations will not be
23120+ * aware of that.
23121+ *
23122+ * Return: '0' on Success; Error code otherwise.
23123+ */
23124+int dprc_reset_container(struct fsl_mc_io *mc_io,
23125+ uint32_t cmd_flags,
23126+ uint16_t token,
23127+ int child_container_id);
23128+
23129+/**
23130+ * DPRC IRQ Index and Events
23131+ */
23132+
23133+/**
23134+ * IRQ index
23135+ */
23136+#define DPRC_IRQ_INDEX 0
23137+
23138+/**
23139+ * Number of dprc's IRQs
23140+ */
23141+#define DPRC_NUM_OF_IRQS 1
23142+
23143+/* DPRC IRQ events */
23144+/**
23145+ * IRQ event - Indicates that a new object added to the container
23146+ */
23147+#define DPRC_IRQ_EVENT_OBJ_ADDED 0x00000001
23148+/**
23149+ * IRQ event - Indicates that an object was removed from the container
23150+ */
23151+#define DPRC_IRQ_EVENT_OBJ_REMOVED 0x00000002
23152+/**
23153+ * IRQ event - Indicates that resources added to the container
23154+ */
23155+#define DPRC_IRQ_EVENT_RES_ADDED 0x00000004
23156+/**
23157+ * IRQ event - Indicates that resources removed from the container
23158+ */
23159+#define DPRC_IRQ_EVENT_RES_REMOVED 0x00000008
23160+/**
23161+ * IRQ event - Indicates that one of the descendant containers that opened by
23162+ * this container is destroyed
23163+ */
23164+#define DPRC_IRQ_EVENT_CONTAINER_DESTROYED 0x00000010
23165+/**
23166+ * IRQ event - Indicates that on one of the container's opened object is
23167+ * destroyed
23168+ */
23169+#define DPRC_IRQ_EVENT_OBJ_DESTROYED 0x00000020
23170+/**
23171+ * Irq event - Indicates that object is created at the container
23172+ */
23173+#define DPRC_IRQ_EVENT_OBJ_CREATED 0x00000040
23174+
23175+/**
23176+ * struct dprc_irq_cfg - IRQ configuration
23177+ * @addr: Address that must be written to signal a message-based interrupt
23178+ * @val: Value to write into irq_addr address
23179+ * @irq_num: A user defined number associated with this IRQ
23180+ */
23181+struct dprc_irq_cfg {
23182+ uint64_t addr;
23183+ uint32_t val;
23184+ int irq_num;
23185+};
23186+
23187+/**
23188+ * dprc_set_irq() - Set IRQ information for the DPRC to trigger an interrupt.
23189+ * @mc_io: Pointer to MC portal's I/O object
23190+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23191+ * @token: Token of DPRC object
23192+ * @irq_index: Identifies the interrupt index to configure
23193+ * @irq_cfg: IRQ configuration
23194+ *
23195+ * Return: '0' on Success; Error code otherwise.
23196+ */
23197+int dprc_set_irq(struct fsl_mc_io *mc_io,
23198+ uint32_t cmd_flags,
23199+ uint16_t token,
23200+ uint8_t irq_index,
23201+ struct dprc_irq_cfg *irq_cfg);
23202+
23203+/**
23204+ * dprc_get_irq() - Get IRQ information from the DPRC.
23205+ * @mc_io: Pointer to MC portal's I/O object
23206+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23207+ * @token: Token of DPRC object
23208+ * @irq_index: The interrupt index to configure
23209+ * @type: Interrupt type: 0 represents message interrupt
23210+ * type (both irq_addr and irq_val are valid)
23211+ * @irq_cfg: IRQ attributes
23212+ *
23213+ * Return: '0' on Success; Error code otherwise.
23214+ */
23215+int dprc_get_irq(struct fsl_mc_io *mc_io,
23216+ uint32_t cmd_flags,
23217+ uint16_t token,
23218+ uint8_t irq_index,
23219+ int *type,
23220+ struct dprc_irq_cfg *irq_cfg);
23221+
23222+/**
23223+ * dprc_set_irq_enable() - Set overall interrupt state.
23224+ * @mc_io: Pointer to MC portal's I/O object
23225+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23226+ * @token: Token of DPRC object
23227+ * @irq_index: The interrupt index to configure
23228+ * @en: Interrupt state - enable = 1, disable = 0
23229+ *
23230+ * Allows GPP software to control when interrupts are generated.
23231+ * Each interrupt can have up to 32 causes. The enable/disable control's the
23232+ * overall interrupt state. if the interrupt is disabled no causes will cause
23233+ * an interrupt.
23234+ *
23235+ * Return: '0' on Success; Error code otherwise.
23236+ */
23237+int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
23238+ uint32_t cmd_flags,
23239+ uint16_t token,
23240+ uint8_t irq_index,
23241+ uint8_t en);
23242+
23243+/**
23244+ * dprc_get_irq_enable() - Get overall interrupt state.
23245+ * @mc_io: Pointer to MC portal's I/O object
23246+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23247+ * @token: Token of DPRC object
23248+ * @irq_index: The interrupt index to configure
23249+ * @en: Returned interrupt state - enable = 1, disable = 0
23250+ *
23251+ * Return: '0' on Success; Error code otherwise.
23252+ */
23253+int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
23254+ uint32_t cmd_flags,
23255+ uint16_t token,
23256+ uint8_t irq_index,
23257+ uint8_t *en);
23258+
23259+/**
23260+ * dprc_set_irq_mask() - Set interrupt mask.
23261+ * @mc_io: Pointer to MC portal's I/O object
23262+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23263+ * @token: Token of DPRC object
23264+ * @irq_index: The interrupt index to configure
23265+ * @mask: event mask to trigger interrupt;
23266+ * each bit:
23267+ * 0 = ignore event
23268+ * 1 = consider event for asserting IRQ
23269+ *
23270+ * Every interrupt can have up to 32 causes and the interrupt model supports
23271+ * masking/unmasking each cause independently
23272+ *
23273+ * Return: '0' on Success; Error code otherwise.
23274+ */
23275+int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
23276+ uint32_t cmd_flags,
23277+ uint16_t token,
23278+ uint8_t irq_index,
23279+ uint32_t mask);
23280+
23281+/**
23282+ * dprc_get_irq_mask() - Get interrupt mask.
23283+ * @mc_io: Pointer to MC portal's I/O object
23284+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23285+ * @token: Token of DPRC object
23286+ * @irq_index: The interrupt index to configure
23287+ * @mask: Returned event mask to trigger interrupt
23288+ *
23289+ * Every interrupt can have up to 32 causes and the interrupt model supports
23290+ * masking/unmasking each cause independently
23291+ *
23292+ * Return: '0' on Success; Error code otherwise.
23293+ */
23294+int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
23295+ uint32_t cmd_flags,
23296+ uint16_t token,
23297+ uint8_t irq_index,
23298+ uint32_t *mask);
23299+
23300+/**
23301+ * dprc_get_irq_status() - Get the current status of any pending interrupts.
23302+ * @mc_io: Pointer to MC portal's I/O object
23303+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23304+ * @token: Token of DPRC object
23305+ * @irq_index: The interrupt index to configure
23306+ * @status: Returned interrupts status - one bit per cause:
23307+ * 0 = no interrupt pending
23308+ * 1 = interrupt pending
23309+ *
23310+ * Return: '0' on Success; Error code otherwise.
23311+ */
23312+int dprc_get_irq_status(struct fsl_mc_io *mc_io,
23313+ uint32_t cmd_flags,
23314+ uint16_t token,
23315+ uint8_t irq_index,
23316+ uint32_t *status);
23317+
23318+/**
23319+ * dprc_clear_irq_status() - Clear a pending interrupt's status
23320+ * @mc_io: Pointer to MC portal's I/O object
23321+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23322+ * @token: Token of DPRC object
23323+ * @irq_index: The interrupt index to configure
23324+ * @status: bits to clear (W1C) - one bit per cause:
23325+ * 0 = don't change
23326+ * 1 = clear status bit
23327+ *
23328+ * Return: '0' on Success; Error code otherwise.
23329+ */
23330+int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
23331+ uint32_t cmd_flags,
23332+ uint16_t token,
23333+ uint8_t irq_index,
23334+ uint32_t status);
23335+
23336+/**
23337+ * struct dprc_attributes - Container attributes
23338+ * @container_id: Container's ID
23339+ * @icid: Container's ICID
23340+ * @portal_id: Container's portal ID
23341+ * @options: Container's options as set at container's creation
23342+ * @version: DPRC version
23343+ */
23344+struct dprc_attributes {
23345+ int container_id;
23346+ uint16_t icid;
23347+ int portal_id;
23348+ uint64_t options;
23349+ /**
23350+ * struct version - DPRC version
23351+ * @major: DPRC major version
23352+ * @minor: DPRC minor version
23353+ */
23354+ struct {
23355+ uint16_t major;
23356+ uint16_t minor;
23357+ } version;
23358+};
23359+
23360+/**
23361+ * dprc_get_attributes() - Obtains container attributes
23362+ * @mc_io: Pointer to MC portal's I/O object
23363+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23364+ * @token: Token of DPRC object
23365+ * @attributes: Returned container attributes
23366+ *
23367+ * Return: '0' on Success; Error code otherwise.
23368+ */
23369+int dprc_get_attributes(struct fsl_mc_io *mc_io,
23370+ uint32_t cmd_flags,
23371+ uint16_t token,
23372+ struct dprc_attributes *attributes);
23373+
23374+/**
23375+ * dprc_set_res_quota() - Set allocation policy for a specific resource/object
23376+ * type in a child container
23377+ * @mc_io: Pointer to MC portal's I/O object
23378+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23379+ * @token: Token of DPRC object
23380+ * @child_container_id: ID of the child container
23381+ * @type: Resource/object type
23382+ * @quota: Sets the maximum number of resources of the selected type
23383+ * that the child container is allowed to allocate from its parent;
23384+ * when quota is set to -1, the policy is the same as container's
23385+ * general policy.
23386+ *
23387+ * Allocation policy determines whether or not a container may allocate
23388+ * resources from its parent. Each container has a 'global' allocation policy
23389+ * that is set when the container is created.
23390+ *
23391+ * This function sets allocation policy for a specific resource type.
23392+ * The default policy for all resource types matches the container's 'global'
23393+ * allocation policy.
23394+ *
23395+ * Return: '0' on Success; Error code otherwise.
23396+ *
23397+ * @warning Only the parent container is allowed to change a child policy.
23398+ */
23399+int dprc_set_res_quota(struct fsl_mc_io *mc_io,
23400+ uint32_t cmd_flags,
23401+ uint16_t token,
23402+ int child_container_id,
23403+ char *type,
23404+ uint16_t quota);
23405+
23406+/**
23407+ * dprc_get_res_quota() - Gets the allocation policy of a specific
23408+ * resource/object type in a child container
23409+ * @mc_io: Pointer to MC portal's I/O object
23410+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23411+ * @token: Token of DPRC object
23412+ * @child_container_id: ID of the child container
23413+ * @type: resource/object type
23414+ * @quota: Returnes the maximum number of resources of the selected type
23415+ * that the child container is allowed to allocate from the parent;
23416+ * when quota is set to -1, the policy is the same as container's
23417+ * general policy.
23418+ *
23419+ * Return: '0' on Success; Error code otherwise.
23420+ */
23421+int dprc_get_res_quota(struct fsl_mc_io *mc_io,
23422+ uint32_t cmd_flags,
23423+ uint16_t token,
23424+ int child_container_id,
23425+ char *type,
23426+ uint16_t *quota);
23427+
23428+/* Resource request options */
23429+
23430+/**
23431+ * Explicit resource ID request - The requested objects/resources
23432+ * are explicit and sequential (in case of resources).
23433+ * The base ID is given at res_req at base_align field
23434+ */
23435+#define DPRC_RES_REQ_OPT_EXPLICIT 0x00000001
23436+
23437+/**
23438+ * Aligned resources request - Relevant only for resources
23439+ * request (and not objects). Indicates that resources base ID should be
23440+ * sequential and aligned to the value given at dprc_res_req base_align field
23441+ */
23442+#define DPRC_RES_REQ_OPT_ALIGNED 0x00000002
23443+
23444+/**
23445+ * Plugged Flag - Relevant only for object assignment request.
23446+ * Indicates that after all objects assigned. An interrupt will be invoked at
23447+ * the relevant GPP. The assigned object will be marked as plugged.
23448+ * plugged objects can't be assigned from their container
23449+ */
23450+#define DPRC_RES_REQ_OPT_PLUGGED 0x00000004
23451+
23452+/**
23453+ * struct dprc_res_req - Resource request descriptor, to be used in assignment
23454+ * or un-assignment of resources and objects.
23455+ * @type: Resource/object type: Represent as a NULL terminated string.
23456+ * This string may received by using dprc_get_pool() to get resource
23457+ * type and dprc_get_obj() to get object type;
23458+ * Note: it is not possible to assign/un-assign DPRC objects
23459+ * @num: Number of resources
23460+ * @options: Request options: combination of DPRC_RES_REQ_OPT_ options
23461+ * @id_base_align: In case of explicit assignment (DPRC_RES_REQ_OPT_EXPLICIT
23462+ * is set at option), this field represents the required base ID
23463+ * for resource allocation; In case of aligned assignment
23464+ * (DPRC_RES_REQ_OPT_ALIGNED is set at option), this field
23465+ * indicates the required alignment for the resource ID(s) -
23466+ * use 0 if there is no alignment or explicit ID requirements
23467+ */
23468+struct dprc_res_req {
23469+ char type[16];
23470+ uint32_t num;
23471+ uint32_t options;
23472+ int id_base_align;
23473+};
23474+
23475+/**
23476+ * dprc_assign() - Assigns objects or resource to a child container.
23477+ * @mc_io: Pointer to MC portal's I/O object
23478+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23479+ * @token: Token of DPRC object
23480+ * @container_id: ID of the child container
23481+ * @res_req: Describes the type and amount of resources to
23482+ * assign to the given container
23483+ *
23484+ * Assignment is usually done by a parent (this DPRC) to one of its child
23485+ * containers.
23486+ *
23487+ * According to the DPRC allocation policy, the assigned resources may be taken
23488+ * (allocated) from the container's ancestors, if not enough resources are
23489+ * available in the container itself.
23490+ *
23491+ * The type of assignment depends on the dprc_res_req options, as follows:
23492+ * - DPRC_RES_REQ_OPT_EXPLICIT: indicates that assigned resources should have
23493+ * the explicit base ID specified at the id_base_align field of res_req.
23494+ * - DPRC_RES_REQ_OPT_ALIGNED: indicates that the assigned resources should be
23495+ * aligned to the value given at id_base_align field of res_req.
23496+ * - DPRC_RES_REQ_OPT_PLUGGED: Relevant only for object assignment,
23497+ * and indicates that the object must be set to the plugged state.
23498+ *
23499+ * A container may use this function with its own ID in order to change a
23500+ * object state to plugged or unplugged.
23501+ *
23502+ * If IRQ information has been set in the child DPRC, it will signal an
23503+ * interrupt following every change in its object assignment.
23504+ *
23505+ * Return: '0' on Success; Error code otherwise.
23506+ */
23507+int dprc_assign(struct fsl_mc_io *mc_io,
23508+ uint32_t cmd_flags,
23509+ uint16_t token,
23510+ int container_id,
23511+ struct dprc_res_req *res_req);
23512+
23513+/**
23514+ * dprc_unassign() - Un-assigns objects or resources from a child container
23515+ * and moves them into this (parent) DPRC.
23516+ * @mc_io: Pointer to MC portal's I/O object
23517+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23518+ * @token: Token of DPRC object
23519+ * @child_container_id: ID of the child container
23520+ * @res_req: Describes the type and amount of resources to un-assign from
23521+ * the child container
23522+ *
23523+ * Un-assignment of objects can succeed only if the object is not in the
23524+ * plugged or opened state.
23525+ *
23526+ * Return: '0' on Success; Error code otherwise.
23527+ */
23528+int dprc_unassign(struct fsl_mc_io *mc_io,
23529+ uint32_t cmd_flags,
23530+ uint16_t token,
23531+ int child_container_id,
23532+ struct dprc_res_req *res_req);
23533+
23534+/**
23535+ * dprc_get_pool_count() - Get the number of dprc's pools
23536+ * @mc_io: Pointer to MC portal's I/O object
23537+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23538+ * @token: Token of DPRC object
23539+ * @pool_count: Returned number of resource pools in the dprc
23540+ *
23541+ * Return: '0' on Success; Error code otherwise.
23542+ */
23543+int dprc_get_pool_count(struct fsl_mc_io *mc_io,
23544+ uint32_t cmd_flags,
23545+ uint16_t token,
23546+ int *pool_count);
23547+
23548+/**
23549+ * dprc_get_pool() - Get the type (string) of a certain dprc's pool
23550+ * @mc_io: Pointer to MC portal's I/O object
23551+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23552+ * @token: Token of DPRC object
23553+ * @pool_index: Index of the pool to be queried (< pool_count)
23554+ * @type: The type of the pool
23555+ *
23556+ * The pool types retrieved one by one by incrementing
23557+ * pool_index up to (not including) the value of pool_count returned
23558+ * from dprc_get_pool_count(). dprc_get_pool_count() must
23559+ * be called prior to dprc_get_pool().
23560+ *
23561+ * Return: '0' on Success; Error code otherwise.
23562+ */
23563+int dprc_get_pool(struct fsl_mc_io *mc_io,
23564+ uint32_t cmd_flags,
23565+ uint16_t token,
23566+ int pool_index,
23567+ char *type);
23568+
23569+/**
23570+ * dprc_get_obj_count() - Obtains the number of objects in the DPRC
23571+ * @mc_io: Pointer to MC portal's I/O object
23572+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23573+ * @token: Token of DPRC object
23574+ * @obj_count: Number of objects assigned to the DPRC
23575+ *
23576+ * Return: '0' on Success; Error code otherwise.
23577+ */
23578+int dprc_get_obj_count(struct fsl_mc_io *mc_io,
23579+ uint32_t cmd_flags,
23580+ uint16_t token,
23581+ int *obj_count);
23582+
23583+/**
23584+ * Objects Attributes Flags
23585+ */
23586+
23587+/**
23588+ * Opened state - Indicates that an object is open by at least one owner
23589+ */
23590+#define DPRC_OBJ_STATE_OPEN 0x00000001
23591+/**
23592+ * Plugged state - Indicates that the object is plugged
23593+ */
23594+#define DPRC_OBJ_STATE_PLUGGED 0x00000002
23595+
23596+/**
23597+ * Shareability flag - Object flag indicating no memory shareability.
23598+ * the object generates memory accesses that are non coherent with other
23599+ * masters;
23600+ * user is responsible for proper memory handling through IOMMU configuration.
23601+ */
23602+#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001
23603+
23604+/**
23605+ * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj()
23606+ * @type: Type of object: NULL terminated string
23607+ * @id: ID of logical object resource
23608+ * @vendor: Object vendor identifier
23609+ * @ver_major: Major version number
23610+ * @ver_minor: Minor version number
23611+ * @irq_count: Number of interrupts supported by the object
23612+ * @region_count: Number of mappable regions supported by the object
23613+ * @state: Object state: combination of DPRC_OBJ_STATE_ states
23614+ * @label: Object label
23615+ * @flags: Object's flags
23616+ */
23617+struct dprc_obj_desc {
23618+ char type[16];
23619+ int id;
23620+ uint16_t vendor;
23621+ uint16_t ver_major;
23622+ uint16_t ver_minor;
23623+ uint8_t irq_count;
23624+ uint8_t region_count;
23625+ uint32_t state;
23626+ char label[16];
23627+ uint16_t flags;
23628+};
23629+
23630+/**
23631+ * dprc_get_obj() - Get general information on an object
23632+ * @mc_io: Pointer to MC portal's I/O object
23633+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23634+ * @token: Token of DPRC object
23635+ * @obj_index: Index of the object to be queried (< obj_count)
23636+ * @obj_desc: Returns the requested object descriptor
23637+ *
23638+ * The object descriptors are retrieved one by one by incrementing
23639+ * obj_index up to (not including) the value of obj_count returned
23640+ * from dprc_get_obj_count(). dprc_get_obj_count() must
23641+ * be called prior to dprc_get_obj().
23642+ *
23643+ * Return: '0' on Success; Error code otherwise.
23644+ */
23645+int dprc_get_obj(struct fsl_mc_io *mc_io,
23646+ uint32_t cmd_flags,
23647+ uint16_t token,
23648+ int obj_index,
23649+ struct dprc_obj_desc *obj_desc);
23650+
23651+/**
23652+ * dprc_get_obj_desc() - Get object descriptor.
23653+ *
23654+ * @mc_io: Pointer to MC portal's I/O object
23655+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23656+ * @token: Token of DPRC object
23657+ * @obj_type: The type of the object to get its descriptor.
23658+ * @obj_id: The id of the object to get its descriptor
23659+ * @obj_desc: The returned descriptor to fill and return to the user
23660+ *
23661+ * Return: '0' on Success; Error code otherwise.
23662+ *
23663+ */
23664+int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
23665+ uint32_t cmd_flags,
23666+ uint16_t token,
23667+ char *obj_type,
23668+ int obj_id,
23669+ struct dprc_obj_desc *obj_desc);
23670+
23671+/**
23672+ * dprc_set_obj_irq() - Set IRQ information for object to trigger an interrupt.
23673+ * @mc_io: Pointer to MC portal's I/O object
23674+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23675+ * @token: Token of DPRC object
23676+ * @obj_type: Type of the object to set its IRQ
23677+ * @obj_id: ID of the object to set its IRQ
23678+ * @irq_index: The interrupt index to configure
23679+ * @irq_cfg: IRQ configuration
23680+ *
23681+ * Return: '0' on Success; Error code otherwise.
23682+ */
23683+int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
23684+ uint32_t cmd_flags,
23685+ uint16_t token,
23686+ char *obj_type,
23687+ int obj_id,
23688+ uint8_t irq_index,
23689+ struct dprc_irq_cfg *irq_cfg);
23690+
23691+/**
23692+ * dprc_get_obj_irq() - Get IRQ information from object.
23693+ * @mc_io: Pointer to MC portal's I/O object
23694+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23695+ * @token: Token of DPRC object
23696+ * @obj_type: Type od the object to get its IRQ
23697+ * @obj_id: ID of the object to get its IRQ
23698+ * @irq_index: The interrupt index to configure
23699+ * @type: Interrupt type: 0 represents message interrupt
23700+ * type (both irq_addr and irq_val are valid)
23701+ * @irq_cfg: The returned IRQ attributes
23702+ *
23703+ * Return: '0' on Success; Error code otherwise.
23704+ */
23705+int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
23706+ uint32_t cmd_flags,
23707+ uint16_t token,
23708+ char *obj_type,
23709+ int obj_id,
23710+ uint8_t irq_index,
23711+ int *type,
23712+ struct dprc_irq_cfg *irq_cfg);
23713+
23714+/**
23715+ * dprc_get_res_count() - Obtains the number of free resources that are
23716+ * assigned to this container, by pool type
23717+ * @mc_io: Pointer to MC portal's I/O object
23718+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23719+ * @token: Token of DPRC object
23720+ * @type: pool type
23721+ * @res_count: Returned number of free resources of the given
23722+ * resource type that are assigned to this DPRC
23723+ *
23724+ * Return: '0' on Success; Error code otherwise.
23725+ */
23726+int dprc_get_res_count(struct fsl_mc_io *mc_io,
23727+ uint32_t cmd_flags,
23728+ uint16_t token,
23729+ char *type,
23730+ int *res_count);
23731+
23732+/**
23733+ * enum dprc_iter_status - Iteration status
23734+ * @DPRC_ITER_STATUS_FIRST: Perform first iteration
23735+ * @DPRC_ITER_STATUS_MORE: Indicates more/next iteration is needed
23736+ * @DPRC_ITER_STATUS_LAST: Indicates last iteration
23737+ */
23738+enum dprc_iter_status {
23739+ DPRC_ITER_STATUS_FIRST = 0,
23740+ DPRC_ITER_STATUS_MORE = 1,
23741+ DPRC_ITER_STATUS_LAST = 2
23742+};
23743+
23744+/**
23745+ * struct dprc_res_ids_range_desc - Resource ID range descriptor
23746+ * @base_id: Base resource ID of this range
23747+ * @last_id: Last resource ID of this range
23748+ * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at
23749+ * first iteration; while the returned marker is DPRC_ITER_STATUS_MORE,
23750+ * additional iterations are needed, until the returned marker is
23751+ * DPRC_ITER_STATUS_LAST
23752+ */
23753+struct dprc_res_ids_range_desc {
23754+ int base_id;
23755+ int last_id;
23756+ enum dprc_iter_status iter_status;
23757+};
23758+
23759+/**
23760+ * dprc_get_res_ids() - Obtains IDs of free resources in the container
23761+ * @mc_io: Pointer to MC portal's I/O object
23762+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23763+ * @token: Token of DPRC object
23764+ * @type: pool type
23765+ * @range_desc: range descriptor
23766+ *
23767+ * Return: '0' on Success; Error code otherwise.
23768+ */
23769+int dprc_get_res_ids(struct fsl_mc_io *mc_io,
23770+ uint32_t cmd_flags,
23771+ uint16_t token,
23772+ char *type,
23773+ struct dprc_res_ids_range_desc *range_desc);
23774+
23775+/**
23776+ * Region flags
23777+ */
23778+/**
23779+ * Cacheable - Indicates that region should be mapped as cacheable
23780+ */
23781+#define DPRC_REGION_CACHEABLE 0x00000001
23782+
23783+/**
23784+ * enum dprc_region_type - Region type
23785+ * @DPRC_REGION_TYPE_MC_PORTAL: MC portal region
23786+ * @DPRC_REGION_TYPE_QBMAN_PORTAL: Qbman portal region
23787+ */
23788+enum dprc_region_type {
23789+ DPRC_REGION_TYPE_MC_PORTAL,
23790+ DPRC_REGION_TYPE_QBMAN_PORTAL
23791+};
23792+
23793+/**
23794+ * struct dprc_region_desc - Mappable region descriptor
23795+ * @base_offset: Region offset from region's base address.
23796+ * For DPMCP and DPRC objects, region base is offset from SoC MC portals
23797+ * base address; For DPIO, region base is offset from SoC QMan portals
23798+ * base address
23799+ * @size: Region size (in bytes)
23800+ * @flags: Region attributes
23801+ * @type: Portal region type
23802+ */
23803+struct dprc_region_desc {
23804+ uint32_t base_offset;
23805+ uint32_t size;
23806+ uint32_t flags;
23807+ enum dprc_region_type type;
23808+};
23809+
23810+/**
23811+ * dprc_get_obj_region() - Get region information for a specified object.
23812+ * @mc_io: Pointer to MC portal's I/O object
23813+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23814+ * @token: Token of DPRC object
23815+ * @obj_type: Object type as returned in dprc_get_obj()
23816+ * @obj_id: Unique object instance as returned in dprc_get_obj()
23817+ * @region_index: The specific region to query
23818+ * @region_desc: Returns the requested region descriptor
23819+ *
23820+ * Return: '0' on Success; Error code otherwise.
23821+ */
23822+int dprc_get_obj_region(struct fsl_mc_io *mc_io,
23823+ uint32_t cmd_flags,
23824+ uint16_t token,
23825+ char *obj_type,
23826+ int obj_id,
23827+ uint8_t region_index,
23828+ struct dprc_region_desc *region_desc);
23829+
23830+/**
23831+ * dprc_set_obj_label() - Set object label.
23832+ * @mc_io: Pointer to MC portal's I/O object
23833+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23834+ * @token: Token of DPRC object
23835+ * @obj_type: Object's type
23836+ * @obj_id: Object's ID
23837+ * @label: The required label. The maximum length is 16 chars.
23838+ *
23839+ * Return: '0' on Success; Error code otherwise.
23840+ */
23841+int dprc_set_obj_label(struct fsl_mc_io *mc_io,
23842+ uint32_t cmd_flags,
23843+ uint16_t token,
23844+ char *obj_type,
23845+ int obj_id,
23846+ char *label);
23847+
23848+/**
23849+ * struct dprc_endpoint - Endpoint description for link connect/disconnect
23850+ * operations
23851+ * @type: Endpoint object type: NULL terminated string
23852+ * @id: Endpoint object ID
23853+ * @if_id: Interface ID; should be set for endpoints with multiple
23854+ * interfaces ("dpsw", "dpdmux"); for others, always set to 0
23855+ */
23856+struct dprc_endpoint {
23857+ char type[16];
23858+ int id;
23859+ uint16_t if_id;
23860+};
23861+
23862+/**
23863+ * struct dprc_connection_cfg - Connection configuration.
23864+ * Used for virtual connections only
23865+ * @committed_rate: Committed rate (Mbits/s)
23866+ * @max_rate: Maximum rate (Mbits/s)
23867+ */
23868+struct dprc_connection_cfg {
23869+ uint32_t committed_rate;
23870+ uint32_t max_rate;
23871+};
23872+
23873+/**
23874+ * dprc_connect() - Connect two endpoints to create a network link between them
23875+ * @mc_io: Pointer to MC portal's I/O object
23876+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23877+ * @token: Token of DPRC object
23878+ * @endpoint1: Endpoint 1 configuration parameters
23879+ * @endpoint2: Endpoint 2 configuration parameters
23880+ * @cfg: Connection configuration. The connection configuration is ignored for
23881+ * connections made to DPMAC objects, where rate is retrieved from the
23882+ * MAC configuration.
23883+ *
23884+ * Return: '0' on Success; Error code otherwise.
23885+ */
23886+int dprc_connect(struct fsl_mc_io *mc_io,
23887+ uint32_t cmd_flags,
23888+ uint16_t token,
23889+ const struct dprc_endpoint *endpoint1,
23890+ const struct dprc_endpoint *endpoint2,
23891+ const struct dprc_connection_cfg *cfg);
23892+
23893+/**
23894+ * dprc_disconnect() - Disconnect one endpoint to remove its network connection
23895+ * @mc_io: Pointer to MC portal's I/O object
23896+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23897+ * @token: Token of DPRC object
23898+ * @endpoint: Endpoint configuration parameters
23899+ *
23900+ * Return: '0' on Success; Error code otherwise.
23901+ */
23902+int dprc_disconnect(struct fsl_mc_io *mc_io,
23903+ uint32_t cmd_flags,
23904+ uint16_t token,
23905+ const struct dprc_endpoint *endpoint);
23906+
23907+/**
23908+* dprc_get_connection() - Get connected endpoint and link status if connection
23909+* exists.
23910+* @mc_io: Pointer to MC portal's I/O object
23911+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
23912+* @token: Token of DPRC object
23913+* @endpoint1: Endpoint 1 configuration parameters
23914+* @endpoint2: Returned endpoint 2 configuration parameters
23915+* @state: Returned link state:
23916+* 1 - link is up;
23917+* 0 - link is down;
23918+* -1 - no connection (endpoint2 information is irrelevant)
23919+*
23920+* Return: '0' on Success; -ENAVAIL if connection does not exist.
23921+*/
23922+int dprc_get_connection(struct fsl_mc_io *mc_io,
23923+ uint32_t cmd_flags,
23924+ uint16_t token,
23925+ const struct dprc_endpoint *endpoint1,
23926+ struct dprc_endpoint *endpoint2,
23927+ int *state);
23928+
23929+#endif /* _FSL_DPRC_H */
23930diff --git a/drivers/net/dpaa2/mc/fsl_dprc_cmd.h b/drivers/net/dpaa2/mc/fsl_dprc_cmd.h
23931new file mode 100644
23932index 0000000..469e286
23933--- /dev/null
23934+++ b/drivers/net/dpaa2/mc/fsl_dprc_cmd.h
23935@@ -0,0 +1,755 @@
23936+/* Copyright 2013-2015 Freescale Semiconductor Inc.
23937+ *
23938+ * Redistribution and use in source and binary forms, with or without
23939+ * modification, are permitted provided that the following conditions are met:
23940+ * * Redistributions of source code must retain the above copyright
23941+ * notice, this list of conditions and the following disclaimer.
23942+ * * Redistributions in binary form must reproduce the above copyright
23943+ * notice, this list of conditions and the following disclaimer in the
23944+ * documentation and/or other materials provided with the distribution.
23945+ * * Neither the name of the above-listed copyright holders nor the
23946+ * names of any contributors may be used to endorse or promote products
23947+ * derived from this software without specific prior written permission.
23948+ *
23949+ *
23950+ * ALTERNATIVELY, this software may be distributed under the terms of the
23951+ * GNU General Public License ("GPL") as published by the Free Software
23952+ * Foundation, either version 2 of that License or (at your option) any
23953+ * later version.
23954+ *
23955+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23956+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23957+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23958+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
23959+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23960+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23961+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23962+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23963+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23964+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23965+ * POSSIBILITY OF SUCH DAMAGE.
23966+ */
23967+#ifndef _FSL_DPRC_CMD_H
23968+#define _FSL_DPRC_CMD_H
23969+
23970+/* DPRC Version */
23971+#define DPRC_VER_MAJOR 5
23972+#define DPRC_VER_MINOR 1
23973+
23974+/* Command IDs */
23975+#define DPRC_CMDID_CLOSE 0x800
23976+#define DPRC_CMDID_OPEN 0x805
23977+#define DPRC_CMDID_CREATE 0x905
23978+
23979+#define DPRC_CMDID_GET_ATTR 0x004
23980+#define DPRC_CMDID_RESET_CONT 0x005
23981+
23982+#define DPRC_CMDID_SET_IRQ 0x010
23983+#define DPRC_CMDID_GET_IRQ 0x011
23984+#define DPRC_CMDID_SET_IRQ_ENABLE 0x012
23985+#define DPRC_CMDID_GET_IRQ_ENABLE 0x013
23986+#define DPRC_CMDID_SET_IRQ_MASK 0x014
23987+#define DPRC_CMDID_GET_IRQ_MASK 0x015
23988+#define DPRC_CMDID_GET_IRQ_STATUS 0x016
23989+#define DPRC_CMDID_CLEAR_IRQ_STATUS 0x017
23990+
23991+#define DPRC_CMDID_CREATE_CONT 0x151
23992+#define DPRC_CMDID_DESTROY_CONT 0x152
23993+#define DPRC_CMDID_GET_CONT_ID 0x830
23994+#define DPRC_CMDID_SET_RES_QUOTA 0x155
23995+#define DPRC_CMDID_GET_RES_QUOTA 0x156
23996+#define DPRC_CMDID_ASSIGN 0x157
23997+#define DPRC_CMDID_UNASSIGN 0x158
23998+#define DPRC_CMDID_GET_OBJ_COUNT 0x159
23999+#define DPRC_CMDID_GET_OBJ 0x15A
24000+#define DPRC_CMDID_GET_RES_COUNT 0x15B
24001+#define DPRC_CMDID_GET_RES_IDS 0x15C
24002+#define DPRC_CMDID_GET_OBJ_REG 0x15E
24003+#define DPRC_CMDID_SET_OBJ_IRQ 0x15F
24004+#define DPRC_CMDID_GET_OBJ_IRQ 0x160
24005+#define DPRC_CMDID_SET_OBJ_LABEL 0x161
24006+#define DPRC_CMDID_GET_OBJ_DESC 0x162
24007+
24008+#define DPRC_CMDID_CONNECT 0x167
24009+#define DPRC_CMDID_DISCONNECT 0x168
24010+#define DPRC_CMDID_GET_POOL 0x169
24011+#define DPRC_CMDID_GET_POOL_COUNT 0x16A
24012+
24013+#define DPRC_CMDID_GET_CONNECTION 0x16C
24014+
24015+/* cmd, param, offset, width, type, arg_name */
24016+#define DPRC_RSP_GET_CONTAINER_ID(cmd, container_id) \
24017+ MC_RSP_OP(cmd, 0, 0, 32, int, container_id)
24018+
24019+/* cmd, param, offset, width, type, arg_name */
24020+#define DPRC_CMD_OPEN(cmd, container_id) \
24021+ MC_CMD_OP(cmd, 0, 0, 32, int, container_id)
24022+
24023+/* cmd, param, offset, width, type, arg_name */
24024+#define DPRC_CMD_CREATE_CONTAINER(cmd, cfg) \
24025+do { \
24026+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \
24027+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->options); \
24028+ MC_CMD_OP(cmd, 1, 32, 32, int, cfg->portal_id); \
24029+ MC_CMD_OP(cmd, 2, 0, 8, char, cfg->label[0]);\
24030+ MC_CMD_OP(cmd, 2, 8, 8, char, cfg->label[1]);\
24031+ MC_CMD_OP(cmd, 2, 16, 8, char, cfg->label[2]);\
24032+ MC_CMD_OP(cmd, 2, 24, 8, char, cfg->label[3]);\
24033+ MC_CMD_OP(cmd, 2, 32, 8, char, cfg->label[4]);\
24034+ MC_CMD_OP(cmd, 2, 40, 8, char, cfg->label[5]);\
24035+ MC_CMD_OP(cmd, 2, 48, 8, char, cfg->label[6]);\
24036+ MC_CMD_OP(cmd, 2, 56, 8, char, cfg->label[7]);\
24037+ MC_CMD_OP(cmd, 3, 0, 8, char, cfg->label[8]);\
24038+ MC_CMD_OP(cmd, 3, 8, 8, char, cfg->label[9]);\
24039+ MC_CMD_OP(cmd, 3, 16, 8, char, cfg->label[10]);\
24040+ MC_CMD_OP(cmd, 3, 24, 8, char, cfg->label[11]);\
24041+ MC_CMD_OP(cmd, 3, 32, 8, char, cfg->label[12]);\
24042+ MC_CMD_OP(cmd, 3, 40, 8, char, cfg->label[13]);\
24043+ MC_CMD_OP(cmd, 3, 48, 8, char, cfg->label[14]);\
24044+ MC_CMD_OP(cmd, 3, 56, 8, char, cfg->label[15]);\
24045+} while (0)
24046+
24047+/* cmd, param, offset, width, type, arg_name */
24048+#define DPRC_RSP_CREATE_CONTAINER(cmd, child_container_id, child_portal_offset)\
24049+do { \
24050+ MC_RSP_OP(cmd, 1, 0, 32, int, child_container_id); \
24051+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, child_portal_offset);\
24052+} while (0)
24053+
24054+/* cmd, param, offset, width, type, arg_name */
24055+#define DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id) \
24056+ MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id)
24057+
24058+/* cmd, param, offset, width, type, arg_name */
24059+#define DPRC_CMD_RESET_CONTAINER(cmd, child_container_id) \
24060+ MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id)
24061+
24062+/* cmd, param, offset, width, type, arg_name */
24063+#define DPRC_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
24064+do { \
24065+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
24066+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
24067+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
24068+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
24069+} while (0)
24070+
24071+/* cmd, param, offset, width, type, arg_name */
24072+#define DPRC_CMD_GET_IRQ(cmd, irq_index) \
24073+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
24074+
24075+/* cmd, param, offset, width, type, arg_name */
24076+#define DPRC_RSP_GET_IRQ(cmd, type, irq_cfg) \
24077+do { \
24078+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
24079+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
24080+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
24081+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
24082+} while (0)
24083+
24084+/* cmd, param, offset, width, type, arg_name */
24085+#define DPRC_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \
24086+do { \
24087+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \
24088+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
24089+} while (0)
24090+
24091+/* cmd, param, offset, width, type, arg_name */
24092+#define DPRC_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
24093+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
24094+
24095+/* cmd, param, offset, width, type, arg_name */
24096+#define DPRC_RSP_GET_IRQ_ENABLE(cmd, en) \
24097+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en)
24098+
24099+/* cmd, param, offset, width, type, arg_name */
24100+#define DPRC_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
24101+do { \
24102+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
24103+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
24104+} while (0)
24105+
24106+/* cmd, param, offset, width, type, arg_name */
24107+#define DPRC_CMD_GET_IRQ_MASK(cmd, irq_index) \
24108+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
24109+
24110+/* cmd, param, offset, width, type, arg_name */
24111+#define DPRC_RSP_GET_IRQ_MASK(cmd, mask) \
24112+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
24113+
24114+/* cmd, param, offset, width, type, arg_name */
24115+#define DPRC_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
24116+do { \
24117+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
24118+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
24119+} while (0)
24120+
24121+/* cmd, param, offset, width, type, arg_name */
24122+#define DPRC_RSP_GET_IRQ_STATUS(cmd, status) \
24123+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
24124+
24125+/* cmd, param, offset, width, type, arg_name */
24126+#define DPRC_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
24127+do { \
24128+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
24129+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
24130+} while (0)
24131+
24132+/* cmd, param, offset, width, type, arg_name */
24133+#define DPRC_RSP_GET_ATTRIBUTES(cmd, attr) \
24134+do { \
24135+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->container_id); \
24136+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->icid); \
24137+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options);\
24138+ MC_RSP_OP(cmd, 1, 32, 32, int, attr->portal_id); \
24139+ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, attr->version.major);\
24140+ MC_RSP_OP(cmd, 2, 16, 16, uint16_t, attr->version.minor);\
24141+} while (0)
24142+
24143+/* cmd, param, offset, width, type, arg_name */
24144+#define DPRC_CMD_SET_RES_QUOTA(cmd, child_container_id, type, quota) \
24145+do { \
24146+ MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id); \
24147+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, quota);\
24148+ MC_CMD_OP(cmd, 1, 0, 8, char, type[0]);\
24149+ MC_CMD_OP(cmd, 1, 8, 8, char, type[1]);\
24150+ MC_CMD_OP(cmd, 1, 16, 8, char, type[2]);\
24151+ MC_CMD_OP(cmd, 1, 24, 8, char, type[3]);\
24152+ MC_CMD_OP(cmd, 1, 32, 8, char, type[4]);\
24153+ MC_CMD_OP(cmd, 1, 40, 8, char, type[5]);\
24154+ MC_CMD_OP(cmd, 1, 48, 8, char, type[6]);\
24155+ MC_CMD_OP(cmd, 1, 56, 8, char, type[7]);\
24156+ MC_CMD_OP(cmd, 2, 0, 8, char, type[8]);\
24157+ MC_CMD_OP(cmd, 2, 8, 8, char, type[9]);\
24158+ MC_CMD_OP(cmd, 2, 16, 8, char, type[10]);\
24159+ MC_CMD_OP(cmd, 2, 24, 8, char, type[11]);\
24160+ MC_CMD_OP(cmd, 2, 32, 8, char, type[12]);\
24161+ MC_CMD_OP(cmd, 2, 40, 8, char, type[13]);\
24162+ MC_CMD_OP(cmd, 2, 48, 8, char, type[14]);\
24163+ MC_CMD_OP(cmd, 2, 56, 8, char, type[15]);\
24164+} while (0)
24165+
24166+/* cmd, param, offset, width, type, arg_name */
24167+#define DPRC_CMD_GET_RES_QUOTA(cmd, child_container_id, type) \
24168+do { \
24169+ MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id); \
24170+ MC_CMD_OP(cmd, 1, 0, 8, char, type[0]);\
24171+ MC_CMD_OP(cmd, 1, 8, 8, char, type[1]);\
24172+ MC_CMD_OP(cmd, 1, 16, 8, char, type[2]);\
24173+ MC_CMD_OP(cmd, 1, 24, 8, char, type[3]);\
24174+ MC_CMD_OP(cmd, 1, 32, 8, char, type[4]);\
24175+ MC_CMD_OP(cmd, 1, 40, 8, char, type[5]);\
24176+ MC_CMD_OP(cmd, 1, 48, 8, char, type[6]);\
24177+ MC_CMD_OP(cmd, 1, 56, 8, char, type[7]);\
24178+ MC_CMD_OP(cmd, 2, 0, 8, char, type[8]);\
24179+ MC_CMD_OP(cmd, 2, 8, 8, char, type[9]);\
24180+ MC_CMD_OP(cmd, 2, 16, 8, char, type[10]);\
24181+ MC_CMD_OP(cmd, 2, 24, 8, char, type[11]);\
24182+ MC_CMD_OP(cmd, 2, 32, 8, char, type[12]);\
24183+ MC_CMD_OP(cmd, 2, 40, 8, char, type[13]);\
24184+ MC_CMD_OP(cmd, 2, 48, 8, char, type[14]);\
24185+ MC_CMD_OP(cmd, 2, 56, 8, char, type[15]);\
24186+} while (0)
24187+/* cmd, param, offset, width, type, arg_name */
24188+#define DPRC_RSP_GET_RES_QUOTA(cmd, quota) \
24189+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, quota)
24190+
24191+/* param, offset, width, type, arg_name */
24192+#define DPRC_CMD_ASSIGN(cmd, container_id, res_req) \
24193+do { \
24194+ MC_CMD_OP(cmd, 0, 0, 32, int, container_id); \
24195+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, res_req->options);\
24196+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, res_req->num); \
24197+ MC_CMD_OP(cmd, 1, 32, 32, int, res_req->id_base_align); \
24198+ MC_CMD_OP(cmd, 2, 0, 8, char, res_req->type[0]);\
24199+ MC_CMD_OP(cmd, 2, 8, 8, char, res_req->type[1]);\
24200+ MC_CMD_OP(cmd, 2, 16, 8, char, res_req->type[2]);\
24201+ MC_CMD_OP(cmd, 2, 24, 8, char, res_req->type[3]);\
24202+ MC_CMD_OP(cmd, 2, 32, 8, char, res_req->type[4]);\
24203+ MC_CMD_OP(cmd, 2, 40, 8, char, res_req->type[5]);\
24204+ MC_CMD_OP(cmd, 2, 48, 8, char, res_req->type[6]);\
24205+ MC_CMD_OP(cmd, 2, 56, 8, char, res_req->type[7]);\
24206+ MC_CMD_OP(cmd, 3, 0, 8, char, res_req->type[8]);\
24207+ MC_CMD_OP(cmd, 3, 8, 8, char, res_req->type[9]);\
24208+ MC_CMD_OP(cmd, 3, 16, 8, char, res_req->type[10]);\
24209+ MC_CMD_OP(cmd, 3, 24, 8, char, res_req->type[11]);\
24210+ MC_CMD_OP(cmd, 3, 32, 8, char, res_req->type[12]);\
24211+ MC_CMD_OP(cmd, 3, 40, 8, char, res_req->type[13]);\
24212+ MC_CMD_OP(cmd, 3, 48, 8, char, res_req->type[14]);\
24213+ MC_CMD_OP(cmd, 3, 56, 8, char, res_req->type[15]);\
24214+} while (0)
24215+
24216+/* param, offset, width, type, arg_name */
24217+#define DPRC_CMD_UNASSIGN(cmd, child_container_id, res_req) \
24218+do { \
24219+ MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id); \
24220+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, res_req->options);\
24221+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, res_req->num); \
24222+ MC_CMD_OP(cmd, 1, 32, 32, int, res_req->id_base_align); \
24223+ MC_CMD_OP(cmd, 2, 0, 8, char, res_req->type[0]);\
24224+ MC_CMD_OP(cmd, 2, 8, 8, char, res_req->type[1]);\
24225+ MC_CMD_OP(cmd, 2, 16, 8, char, res_req->type[2]);\
24226+ MC_CMD_OP(cmd, 2, 24, 8, char, res_req->type[3]);\
24227+ MC_CMD_OP(cmd, 2, 32, 8, char, res_req->type[4]);\
24228+ MC_CMD_OP(cmd, 2, 40, 8, char, res_req->type[5]);\
24229+ MC_CMD_OP(cmd, 2, 48, 8, char, res_req->type[6]);\
24230+ MC_CMD_OP(cmd, 2, 56, 8, char, res_req->type[7]);\
24231+ MC_CMD_OP(cmd, 3, 0, 8, char, res_req->type[8]);\
24232+ MC_CMD_OP(cmd, 3, 8, 8, char, res_req->type[9]);\
24233+ MC_CMD_OP(cmd, 3, 16, 8, char, res_req->type[10]);\
24234+ MC_CMD_OP(cmd, 3, 24, 8, char, res_req->type[11]);\
24235+ MC_CMD_OP(cmd, 3, 32, 8, char, res_req->type[12]);\
24236+ MC_CMD_OP(cmd, 3, 40, 8, char, res_req->type[13]);\
24237+ MC_CMD_OP(cmd, 3, 48, 8, char, res_req->type[14]);\
24238+ MC_CMD_OP(cmd, 3, 56, 8, char, res_req->type[15]);\
24239+} while (0)
24240+
24241+/* cmd, param, offset, width, type, arg_name */
24242+#define DPRC_RSP_GET_POOL_COUNT(cmd, pool_count) \
24243+ MC_RSP_OP(cmd, 0, 0, 32, int, pool_count)
24244+
24245+/* cmd, param, offset, width, type, arg_name */
24246+#define DPRC_CMD_GET_POOL(cmd, pool_index) \
24247+ MC_CMD_OP(cmd, 0, 0, 32, int, pool_index)
24248+
24249+/* cmd, param, offset, width, type, arg_name */
24250+#define DPRC_RSP_GET_POOL(cmd, type) \
24251+do { \
24252+ MC_RSP_OP(cmd, 1, 0, 8, char, type[0]);\
24253+ MC_RSP_OP(cmd, 1, 8, 8, char, type[1]);\
24254+ MC_RSP_OP(cmd, 1, 16, 8, char, type[2]);\
24255+ MC_RSP_OP(cmd, 1, 24, 8, char, type[3]);\
24256+ MC_RSP_OP(cmd, 1, 32, 8, char, type[4]);\
24257+ MC_RSP_OP(cmd, 1, 40, 8, char, type[5]);\
24258+ MC_RSP_OP(cmd, 1, 48, 8, char, type[6]);\
24259+ MC_RSP_OP(cmd, 1, 56, 8, char, type[7]);\
24260+ MC_RSP_OP(cmd, 2, 0, 8, char, type[8]);\
24261+ MC_RSP_OP(cmd, 2, 8, 8, char, type[9]);\
24262+ MC_RSP_OP(cmd, 2, 16, 8, char, type[10]);\
24263+ MC_RSP_OP(cmd, 2, 24, 8, char, type[11]);\
24264+ MC_RSP_OP(cmd, 2, 32, 8, char, type[12]);\
24265+ MC_RSP_OP(cmd, 2, 40, 8, char, type[13]);\
24266+ MC_RSP_OP(cmd, 2, 48, 8, char, type[14]);\
24267+ MC_RSP_OP(cmd, 2, 56, 8, char, type[15]);\
24268+} while (0)
24269+
24270+/* cmd, param, offset, width, type, arg_name */
24271+#define DPRC_RSP_GET_OBJ_COUNT(cmd, obj_count) \
24272+ MC_RSP_OP(cmd, 0, 32, 32, int, obj_count)
24273+
24274+/* cmd, param, offset, width, type, arg_name */
24275+#define DPRC_CMD_GET_OBJ(cmd, obj_index) \
24276+ MC_CMD_OP(cmd, 0, 0, 32, int, obj_index)
24277+
24278+/* cmd, param, offset, width, type, arg_name */
24279+#define DPRC_RSP_GET_OBJ(cmd, obj_desc) \
24280+do { \
24281+ MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \
24282+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \
24283+ MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \
24284+ MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \
24285+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\
24286+ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\
24287+ MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\
24288+ MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \
24289+ MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\
24290+ MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\
24291+ MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\
24292+ MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\
24293+ MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\
24294+ MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\
24295+ MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\
24296+ MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\
24297+ MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\
24298+ MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\
24299+ MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\
24300+ MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\
24301+ MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\
24302+ MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\
24303+ MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\
24304+ MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\
24305+ MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\
24306+ MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\
24307+ MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\
24308+ MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\
24309+ MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\
24310+ MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\
24311+ MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\
24312+ MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\
24313+ MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\
24314+ MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\
24315+ MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\
24316+ MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\
24317+ MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\
24318+ MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\
24319+ MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\
24320+ MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\
24321+} while (0)
24322+
24323+/* cmd, param, offset, width, type, arg_name */
24324+#define DPRC_CMD_GET_OBJ_DESC(cmd, obj_type, obj_id) \
24325+do { \
24326+ MC_CMD_OP(cmd, 0, 0, 32, int, obj_id);\
24327+ MC_CMD_OP(cmd, 1, 0, 8, char, obj_type[0]);\
24328+ MC_CMD_OP(cmd, 1, 8, 8, char, obj_type[1]);\
24329+ MC_CMD_OP(cmd, 1, 16, 8, char, obj_type[2]);\
24330+ MC_CMD_OP(cmd, 1, 24, 8, char, obj_type[3]);\
24331+ MC_CMD_OP(cmd, 1, 32, 8, char, obj_type[4]);\
24332+ MC_CMD_OP(cmd, 1, 40, 8, char, obj_type[5]);\
24333+ MC_CMD_OP(cmd, 1, 48, 8, char, obj_type[6]);\
24334+ MC_CMD_OP(cmd, 1, 56, 8, char, obj_type[7]);\
24335+ MC_CMD_OP(cmd, 2, 0, 8, char, obj_type[8]);\
24336+ MC_CMD_OP(cmd, 2, 8, 8, char, obj_type[9]);\
24337+ MC_CMD_OP(cmd, 2, 16, 8, char, obj_type[10]);\
24338+ MC_CMD_OP(cmd, 2, 24, 8, char, obj_type[11]);\
24339+ MC_CMD_OP(cmd, 2, 32, 8, char, obj_type[12]);\
24340+ MC_CMD_OP(cmd, 2, 40, 8, char, obj_type[13]);\
24341+ MC_CMD_OP(cmd, 2, 48, 8, char, obj_type[14]);\
24342+ MC_CMD_OP(cmd, 2, 56, 8, char, obj_type[15]);\
24343+} while (0)
24344+
24345+/* cmd, param, offset, width, type, arg_name */
24346+#define DPRC_RSP_GET_OBJ_DESC(cmd, obj_desc) \
24347+do { \
24348+ MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \
24349+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \
24350+ MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \
24351+ MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \
24352+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\
24353+ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\
24354+ MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\
24355+ MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \
24356+ MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\
24357+ MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\
24358+ MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\
24359+ MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\
24360+ MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\
24361+ MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\
24362+ MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\
24363+ MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\
24364+ MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\
24365+ MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\
24366+ MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\
24367+ MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\
24368+ MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\
24369+ MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\
24370+ MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\
24371+ MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\
24372+ MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\
24373+ MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\
24374+ MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\
24375+ MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\
24376+ MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\
24377+ MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\
24378+ MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\
24379+ MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\
24380+ MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\
24381+ MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\
24382+ MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\
24383+ MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\
24384+ MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\
24385+ MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\
24386+ MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\
24387+ MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\
24388+} while (0)
24389+
24390+/* cmd, param, offset, width, type, arg_name */
24391+#define DPRC_CMD_GET_RES_COUNT(cmd, type) \
24392+do { \
24393+ MC_CMD_OP(cmd, 1, 0, 8, char, type[0]);\
24394+ MC_CMD_OP(cmd, 1, 8, 8, char, type[1]);\
24395+ MC_CMD_OP(cmd, 1, 16, 8, char, type[2]);\
24396+ MC_CMD_OP(cmd, 1, 24, 8, char, type[3]);\
24397+ MC_CMD_OP(cmd, 1, 32, 8, char, type[4]);\
24398+ MC_CMD_OP(cmd, 1, 40, 8, char, type[5]);\
24399+ MC_CMD_OP(cmd, 1, 48, 8, char, type[6]);\
24400+ MC_CMD_OP(cmd, 1, 56, 8, char, type[7]);\
24401+ MC_CMD_OP(cmd, 2, 0, 8, char, type[8]);\
24402+ MC_CMD_OP(cmd, 2, 8, 8, char, type[9]);\
24403+ MC_CMD_OP(cmd, 2, 16, 8, char, type[10]);\
24404+ MC_CMD_OP(cmd, 2, 24, 8, char, type[11]);\
24405+ MC_CMD_OP(cmd, 2, 32, 8, char, type[12]);\
24406+ MC_CMD_OP(cmd, 2, 40, 8, char, type[13]);\
24407+ MC_CMD_OP(cmd, 2, 48, 8, char, type[14]);\
24408+ MC_CMD_OP(cmd, 2, 56, 8, char, type[15]);\
24409+} while (0)
24410+
24411+/* cmd, param, offset, width, type, arg_name */
24412+#define DPRC_RSP_GET_RES_COUNT(cmd, res_count) \
24413+ MC_RSP_OP(cmd, 0, 0, 32, int, res_count)
24414+
24415+/* cmd, param, offset, width, type, arg_name */
24416+#define DPRC_CMD_GET_RES_IDS(cmd, range_desc, type) \
24417+do { \
24418+ MC_CMD_OP(cmd, 0, 42, 7, enum dprc_iter_status, \
24419+ range_desc->iter_status); \
24420+ MC_CMD_OP(cmd, 1, 0, 32, int, range_desc->base_id); \
24421+ MC_CMD_OP(cmd, 1, 32, 32, int, range_desc->last_id);\
24422+ MC_CMD_OP(cmd, 2, 0, 8, char, type[0]);\
24423+ MC_CMD_OP(cmd, 2, 8, 8, char, type[1]);\
24424+ MC_CMD_OP(cmd, 2, 16, 8, char, type[2]);\
24425+ MC_CMD_OP(cmd, 2, 24, 8, char, type[3]);\
24426+ MC_CMD_OP(cmd, 2, 32, 8, char, type[4]);\
24427+ MC_CMD_OP(cmd, 2, 40, 8, char, type[5]);\
24428+ MC_CMD_OP(cmd, 2, 48, 8, char, type[6]);\
24429+ MC_CMD_OP(cmd, 2, 56, 8, char, type[7]);\
24430+ MC_CMD_OP(cmd, 3, 0, 8, char, type[8]);\
24431+ MC_CMD_OP(cmd, 3, 8, 8, char, type[9]);\
24432+ MC_CMD_OP(cmd, 3, 16, 8, char, type[10]);\
24433+ MC_CMD_OP(cmd, 3, 24, 8, char, type[11]);\
24434+ MC_CMD_OP(cmd, 3, 32, 8, char, type[12]);\
24435+ MC_CMD_OP(cmd, 3, 40, 8, char, type[13]);\
24436+ MC_CMD_OP(cmd, 3, 48, 8, char, type[14]);\
24437+ MC_CMD_OP(cmd, 3, 56, 8, char, type[15]);\
24438+} while (0)
24439+
24440+/* cmd, param, offset, width, type, arg_name */
24441+#define DPRC_RSP_GET_RES_IDS(cmd, range_desc) \
24442+do { \
24443+ MC_RSP_OP(cmd, 0, 42, 7, enum dprc_iter_status, \
24444+ range_desc->iter_status);\
24445+ MC_RSP_OP(cmd, 1, 0, 32, int, range_desc->base_id); \
24446+ MC_RSP_OP(cmd, 1, 32, 32, int, range_desc->last_id);\
24447+} while (0)
24448+
24449+/* cmd, param, offset, width, type, arg_name */
24450+#define DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index) \
24451+do { \
24452+ MC_CMD_OP(cmd, 0, 0, 32, int, obj_id); \
24453+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, region_index);\
24454+ MC_CMD_OP(cmd, 3, 0, 8, char, obj_type[0]);\
24455+ MC_CMD_OP(cmd, 3, 8, 8, char, obj_type[1]);\
24456+ MC_CMD_OP(cmd, 3, 16, 8, char, obj_type[2]);\
24457+ MC_CMD_OP(cmd, 3, 24, 8, char, obj_type[3]);\
24458+ MC_CMD_OP(cmd, 3, 32, 8, char, obj_type[4]);\
24459+ MC_CMD_OP(cmd, 3, 40, 8, char, obj_type[5]);\
24460+ MC_CMD_OP(cmd, 3, 48, 8, char, obj_type[6]);\
24461+ MC_CMD_OP(cmd, 3, 56, 8, char, obj_type[7]);\
24462+ MC_CMD_OP(cmd, 4, 0, 8, char, obj_type[8]);\
24463+ MC_CMD_OP(cmd, 4, 8, 8, char, obj_type[9]);\
24464+ MC_CMD_OP(cmd, 4, 16, 8, char, obj_type[10]);\
24465+ MC_CMD_OP(cmd, 4, 24, 8, char, obj_type[11]);\
24466+ MC_CMD_OP(cmd, 4, 32, 8, char, obj_type[12]);\
24467+ MC_CMD_OP(cmd, 4, 40, 8, char, obj_type[13]);\
24468+ MC_CMD_OP(cmd, 4, 48, 8, char, obj_type[14]);\
24469+ MC_CMD_OP(cmd, 4, 56, 8, char, obj_type[15]);\
24470+} while (0)
24471+
24472+/* param, offset, width, type, arg_name */
24473+#define DPRC_RSP_GET_OBJ_REGION(cmd, region_desc) \
24474+do { \
24475+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, region_desc->base_offset);\
24476+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, region_desc->size); \
24477+ MC_RSP_OP(cmd, 2, 32, 4, enum dprc_region_type, region_desc->type);\
24478+ MC_RSP_OP(cmd, 3, 0, 32, uint32_t, region_desc->flags);\
24479+} while (0)
24480+
24481+/* cmd, param, offset, width, type, arg_name */
24482+#define DPRC_CMD_SET_OBJ_LABEL(cmd, obj_type, obj_id, label) \
24483+do { \
24484+ MC_CMD_OP(cmd, 0, 0, 32, int, obj_id); \
24485+ MC_CMD_OP(cmd, 1, 0, 8, char, label[0]);\
24486+ MC_CMD_OP(cmd, 1, 8, 8, char, label[1]);\
24487+ MC_CMD_OP(cmd, 1, 16, 8, char, label[2]);\
24488+ MC_CMD_OP(cmd, 1, 24, 8, char, label[3]);\
24489+ MC_CMD_OP(cmd, 1, 32, 8, char, label[4]);\
24490+ MC_CMD_OP(cmd, 1, 40, 8, char, label[5]);\
24491+ MC_CMD_OP(cmd, 1, 48, 8, char, label[6]);\
24492+ MC_CMD_OP(cmd, 1, 56, 8, char, label[7]);\
24493+ MC_CMD_OP(cmd, 2, 0, 8, char, label[8]);\
24494+ MC_CMD_OP(cmd, 2, 8, 8, char, label[9]);\
24495+ MC_CMD_OP(cmd, 2, 16, 8, char, label[10]);\
24496+ MC_CMD_OP(cmd, 2, 24, 8, char, label[11]);\
24497+ MC_CMD_OP(cmd, 2, 32, 8, char, label[12]);\
24498+ MC_CMD_OP(cmd, 2, 40, 8, char, label[13]);\
24499+ MC_CMD_OP(cmd, 2, 48, 8, char, label[14]);\
24500+ MC_CMD_OP(cmd, 2, 56, 8, char, label[15]);\
24501+ MC_CMD_OP(cmd, 3, 0, 8, char, obj_type[0]);\
24502+ MC_CMD_OP(cmd, 3, 8, 8, char, obj_type[1]);\
24503+ MC_CMD_OP(cmd, 3, 16, 8, char, obj_type[2]);\
24504+ MC_CMD_OP(cmd, 3, 24, 8, char, obj_type[3]);\
24505+ MC_CMD_OP(cmd, 3, 32, 8, char, obj_type[4]);\
24506+ MC_CMD_OP(cmd, 3, 40, 8, char, obj_type[5]);\
24507+ MC_CMD_OP(cmd, 3, 48, 8, char, obj_type[6]);\
24508+ MC_CMD_OP(cmd, 3, 56, 8, char, obj_type[7]);\
24509+ MC_CMD_OP(cmd, 4, 0, 8, char, obj_type[8]);\
24510+ MC_CMD_OP(cmd, 4, 8, 8, char, obj_type[9]);\
24511+ MC_CMD_OP(cmd, 4, 16, 8, char, obj_type[10]);\
24512+ MC_CMD_OP(cmd, 4, 24, 8, char, obj_type[11]);\
24513+ MC_CMD_OP(cmd, 4, 32, 8, char, obj_type[12]);\
24514+ MC_CMD_OP(cmd, 4, 40, 8, char, obj_type[13]);\
24515+ MC_CMD_OP(cmd, 4, 48, 8, char, obj_type[14]);\
24516+ MC_CMD_OP(cmd, 4, 56, 8, char, obj_type[15]);\
24517+} while (0)
24518+
24519+/* cmd, param, offset, width, type, arg_name */
24520+#define DPRC_CMD_SET_OBJ_IRQ(cmd, obj_type, obj_id, irq_index, irq_cfg) \
24521+do { \
24522+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
24523+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
24524+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
24525+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
24526+ MC_CMD_OP(cmd, 2, 32, 32, int, obj_id); \
24527+ MC_CMD_OP(cmd, 3, 0, 8, char, obj_type[0]);\
24528+ MC_CMD_OP(cmd, 3, 8, 8, char, obj_type[1]);\
24529+ MC_CMD_OP(cmd, 3, 16, 8, char, obj_type[2]);\
24530+ MC_CMD_OP(cmd, 3, 24, 8, char, obj_type[3]);\
24531+ MC_CMD_OP(cmd, 3, 32, 8, char, obj_type[4]);\
24532+ MC_CMD_OP(cmd, 3, 40, 8, char, obj_type[5]);\
24533+ MC_CMD_OP(cmd, 3, 48, 8, char, obj_type[6]);\
24534+ MC_CMD_OP(cmd, 3, 56, 8, char, obj_type[7]);\
24535+ MC_CMD_OP(cmd, 4, 0, 8, char, obj_type[8]);\
24536+ MC_CMD_OP(cmd, 4, 8, 8, char, obj_type[9]);\
24537+ MC_CMD_OP(cmd, 4, 16, 8, char, obj_type[10]);\
24538+ MC_CMD_OP(cmd, 4, 24, 8, char, obj_type[11]);\
24539+ MC_CMD_OP(cmd, 4, 32, 8, char, obj_type[12]);\
24540+ MC_CMD_OP(cmd, 4, 40, 8, char, obj_type[13]);\
24541+ MC_CMD_OP(cmd, 4, 48, 8, char, obj_type[14]);\
24542+ MC_CMD_OP(cmd, 4, 56, 8, char, obj_type[15]);\
24543+} while (0)
24544+
24545+/* cmd, param, offset, width, type, arg_name */
24546+#define DPRC_CMD_GET_OBJ_IRQ(cmd, obj_type, obj_id, irq_index) \
24547+do { \
24548+ MC_CMD_OP(cmd, 0, 0, 32, int, obj_id); \
24549+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
24550+ MC_CMD_OP(cmd, 1, 0, 8, char, obj_type[0]);\
24551+ MC_CMD_OP(cmd, 1, 8, 8, char, obj_type[1]);\
24552+ MC_CMD_OP(cmd, 1, 16, 8, char, obj_type[2]);\
24553+ MC_CMD_OP(cmd, 1, 24, 8, char, obj_type[3]);\
24554+ MC_CMD_OP(cmd, 1, 32, 8, char, obj_type[4]);\
24555+ MC_CMD_OP(cmd, 1, 40, 8, char, obj_type[5]);\
24556+ MC_CMD_OP(cmd, 1, 48, 8, char, obj_type[6]);\
24557+ MC_CMD_OP(cmd, 1, 56, 8, char, obj_type[7]);\
24558+ MC_CMD_OP(cmd, 2, 0, 8, char, obj_type[8]);\
24559+ MC_CMD_OP(cmd, 2, 8, 8, char, obj_type[9]);\
24560+ MC_CMD_OP(cmd, 2, 16, 8, char, obj_type[10]);\
24561+ MC_CMD_OP(cmd, 2, 24, 8, char, obj_type[11]);\
24562+ MC_CMD_OP(cmd, 2, 32, 8, char, obj_type[12]);\
24563+ MC_CMD_OP(cmd, 2, 40, 8, char, obj_type[13]);\
24564+ MC_CMD_OP(cmd, 2, 48, 8, char, obj_type[14]);\
24565+ MC_CMD_OP(cmd, 2, 56, 8, char, obj_type[15]);\
24566+} while (0)
24567+
24568+/* cmd, param, offset, width, type, arg_name */
24569+#define DPRC_RSP_GET_OBJ_IRQ(cmd, type, irq_cfg) \
24570+do { \
24571+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
24572+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
24573+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
24574+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
24575+} while (0)
24576+
24577+/* cmd, param, offset, width, type, arg_name */
24578+#define DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg) \
24579+do { \
24580+ MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \
24581+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint1->if_id); \
24582+ MC_CMD_OP(cmd, 1, 0, 32, int, endpoint2->id); \
24583+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, endpoint2->if_id); \
24584+ MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[0]); \
24585+ MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[1]); \
24586+ MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[2]); \
24587+ MC_CMD_OP(cmd, 2, 24, 8, char, endpoint1->type[3]); \
24588+ MC_CMD_OP(cmd, 2, 32, 8, char, endpoint1->type[4]); \
24589+ MC_CMD_OP(cmd, 2, 40, 8, char, endpoint1->type[5]); \
24590+ MC_CMD_OP(cmd, 2, 48, 8, char, endpoint1->type[6]); \
24591+ MC_CMD_OP(cmd, 2, 56, 8, char, endpoint1->type[7]); \
24592+ MC_CMD_OP(cmd, 3, 0, 8, char, endpoint1->type[8]); \
24593+ MC_CMD_OP(cmd, 3, 8, 8, char, endpoint1->type[9]); \
24594+ MC_CMD_OP(cmd, 3, 16, 8, char, endpoint1->type[10]); \
24595+ MC_CMD_OP(cmd, 3, 24, 8, char, endpoint1->type[11]); \
24596+ MC_CMD_OP(cmd, 3, 32, 8, char, endpoint1->type[12]); \
24597+ MC_CMD_OP(cmd, 3, 40, 8, char, endpoint1->type[13]); \
24598+ MC_CMD_OP(cmd, 3, 48, 8, char, endpoint1->type[14]); \
24599+ MC_CMD_OP(cmd, 3, 56, 8, char, endpoint1->type[15]); \
24600+ MC_CMD_OP(cmd, 4, 0, 32, uint32_t, cfg->max_rate); \
24601+ MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->committed_rate); \
24602+ MC_CMD_OP(cmd, 5, 0, 8, char, endpoint2->type[0]); \
24603+ MC_CMD_OP(cmd, 5, 8, 8, char, endpoint2->type[1]); \
24604+ MC_CMD_OP(cmd, 5, 16, 8, char, endpoint2->type[2]); \
24605+ MC_CMD_OP(cmd, 5, 24, 8, char, endpoint2->type[3]); \
24606+ MC_CMD_OP(cmd, 5, 32, 8, char, endpoint2->type[4]); \
24607+ MC_CMD_OP(cmd, 5, 40, 8, char, endpoint2->type[5]); \
24608+ MC_CMD_OP(cmd, 5, 48, 8, char, endpoint2->type[6]); \
24609+ MC_CMD_OP(cmd, 5, 56, 8, char, endpoint2->type[7]); \
24610+ MC_CMD_OP(cmd, 6, 0, 8, char, endpoint2->type[8]); \
24611+ MC_CMD_OP(cmd, 6, 8, 8, char, endpoint2->type[9]); \
24612+ MC_CMD_OP(cmd, 6, 16, 8, char, endpoint2->type[10]); \
24613+ MC_CMD_OP(cmd, 6, 24, 8, char, endpoint2->type[11]); \
24614+ MC_CMD_OP(cmd, 6, 32, 8, char, endpoint2->type[12]); \
24615+ MC_CMD_OP(cmd, 6, 40, 8, char, endpoint2->type[13]); \
24616+ MC_CMD_OP(cmd, 6, 48, 8, char, endpoint2->type[14]); \
24617+ MC_CMD_OP(cmd, 6, 56, 8, char, endpoint2->type[15]); \
24618+} while (0)
24619+
24620+/* cmd, param, offset, width, type, arg_name */
24621+#define DPRC_CMD_DISCONNECT(cmd, endpoint) \
24622+do { \
24623+ MC_CMD_OP(cmd, 0, 0, 32, int, endpoint->id); \
24624+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint->if_id); \
24625+ MC_CMD_OP(cmd, 1, 0, 8, char, endpoint->type[0]); \
24626+ MC_CMD_OP(cmd, 1, 8, 8, char, endpoint->type[1]); \
24627+ MC_CMD_OP(cmd, 1, 16, 8, char, endpoint->type[2]); \
24628+ MC_CMD_OP(cmd, 1, 24, 8, char, endpoint->type[3]); \
24629+ MC_CMD_OP(cmd, 1, 32, 8, char, endpoint->type[4]); \
24630+ MC_CMD_OP(cmd, 1, 40, 8, char, endpoint->type[5]); \
24631+ MC_CMD_OP(cmd, 1, 48, 8, char, endpoint->type[6]); \
24632+ MC_CMD_OP(cmd, 1, 56, 8, char, endpoint->type[7]); \
24633+ MC_CMD_OP(cmd, 2, 0, 8, char, endpoint->type[8]); \
24634+ MC_CMD_OP(cmd, 2, 8, 8, char, endpoint->type[9]); \
24635+ MC_CMD_OP(cmd, 2, 16, 8, char, endpoint->type[10]); \
24636+ MC_CMD_OP(cmd, 2, 24, 8, char, endpoint->type[11]); \
24637+ MC_CMD_OP(cmd, 2, 32, 8, char, endpoint->type[12]); \
24638+ MC_CMD_OP(cmd, 2, 40, 8, char, endpoint->type[13]); \
24639+ MC_CMD_OP(cmd, 2, 48, 8, char, endpoint->type[14]); \
24640+ MC_CMD_OP(cmd, 2, 56, 8, char, endpoint->type[15]); \
24641+} while (0)
24642+
24643+/* cmd, param, offset, width, type, arg_name */
24644+#define DPRC_CMD_GET_CONNECTION(cmd, endpoint1) \
24645+do { \
24646+ MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \
24647+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint1->if_id); \
24648+ MC_CMD_OP(cmd, 1, 0, 8, char, endpoint1->type[0]); \
24649+ MC_CMD_OP(cmd, 1, 8, 8, char, endpoint1->type[1]); \
24650+ MC_CMD_OP(cmd, 1, 16, 8, char, endpoint1->type[2]); \
24651+ MC_CMD_OP(cmd, 1, 24, 8, char, endpoint1->type[3]); \
24652+ MC_CMD_OP(cmd, 1, 32, 8, char, endpoint1->type[4]); \
24653+ MC_CMD_OP(cmd, 1, 40, 8, char, endpoint1->type[5]); \
24654+ MC_CMD_OP(cmd, 1, 48, 8, char, endpoint1->type[6]); \
24655+ MC_CMD_OP(cmd, 1, 56, 8, char, endpoint1->type[7]); \
24656+ MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[8]); \
24657+ MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[9]); \
24658+ MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[10]); \
24659+ MC_CMD_OP(cmd, 2, 24, 8, char, endpoint1->type[11]); \
24660+ MC_CMD_OP(cmd, 2, 32, 8, char, endpoint1->type[12]); \
24661+ MC_CMD_OP(cmd, 2, 40, 8, char, endpoint1->type[13]); \
24662+ MC_CMD_OP(cmd, 2, 48, 8, char, endpoint1->type[14]); \
24663+ MC_CMD_OP(cmd, 2, 56, 8, char, endpoint1->type[15]); \
24664+} while (0)
24665+
24666+/* cmd, param, offset, width, type, arg_name */
24667+#define DPRC_RSP_GET_CONNECTION(cmd, endpoint2, state) \
24668+do { \
24669+ MC_RSP_OP(cmd, 3, 0, 32, int, endpoint2->id); \
24670+ MC_RSP_OP(cmd, 3, 32, 16, uint16_t, endpoint2->if_id); \
24671+ MC_RSP_OP(cmd, 4, 0, 8, char, endpoint2->type[0]); \
24672+ MC_RSP_OP(cmd, 4, 8, 8, char, endpoint2->type[1]); \
24673+ MC_RSP_OP(cmd, 4, 16, 8, char, endpoint2->type[2]); \
24674+ MC_RSP_OP(cmd, 4, 24, 8, char, endpoint2->type[3]); \
24675+ MC_RSP_OP(cmd, 4, 32, 8, char, endpoint2->type[4]); \
24676+ MC_RSP_OP(cmd, 4, 40, 8, char, endpoint2->type[5]); \
24677+ MC_RSP_OP(cmd, 4, 48, 8, char, endpoint2->type[6]); \
24678+ MC_RSP_OP(cmd, 4, 56, 8, char, endpoint2->type[7]); \
24679+ MC_RSP_OP(cmd, 5, 0, 8, char, endpoint2->type[8]); \
24680+ MC_RSP_OP(cmd, 5, 8, 8, char, endpoint2->type[9]); \
24681+ MC_RSP_OP(cmd, 5, 16, 8, char, endpoint2->type[10]); \
24682+ MC_RSP_OP(cmd, 5, 24, 8, char, endpoint2->type[11]); \
24683+ MC_RSP_OP(cmd, 5, 32, 8, char, endpoint2->type[12]); \
24684+ MC_RSP_OP(cmd, 5, 40, 8, char, endpoint2->type[13]); \
24685+ MC_RSP_OP(cmd, 5, 48, 8, char, endpoint2->type[14]); \
24686+ MC_RSP_OP(cmd, 5, 56, 8, char, endpoint2->type[15]); \
24687+ MC_RSP_OP(cmd, 6, 0, 32, int, state); \
24688+} while (0)
24689+
24690+#endif /* _FSL_DPRC_CMD_H */
24691diff --git a/drivers/net/dpaa2/mc/fsl_dprtc.h b/drivers/net/dpaa2/mc/fsl_dprtc.h
24692new file mode 100644
24693index 0000000..2eb6edc
24694--- /dev/null
24695+++ b/drivers/net/dpaa2/mc/fsl_dprtc.h
24696@@ -0,0 +1,434 @@
24697+/* Copyright 2013-2015 Freescale Semiconductor Inc.
24698+ *
24699+ * Redistribution and use in source and binary forms, with or without
24700+ * modification, are permitted provided that the following conditions are met:
24701+ * * Redistributions of source code must retain the above copyright
24702+ * notice, this list of conditions and the following disclaimer.
24703+ * * Redistributions in binary form must reproduce the above copyright
24704+ * notice, this list of conditions and the following disclaimer in the
24705+ * documentation and/or other materials provided with the distribution.
24706+ * * Neither the name of the above-listed copyright holders nor the
24707+ * names of any contributors may be used to endorse or promote products
24708+ * derived from this software without specific prior written permission.
24709+ *
24710+ *
24711+ * ALTERNATIVELY, this software may be distributed under the terms of the
24712+ * GNU General Public License ("GPL") as published by the Free Software
24713+ * Foundation, either version 2 of that License or (at your option) any
24714+ * later version.
24715+ *
24716+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24717+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24718+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24719+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
24720+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24721+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24722+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24723+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24724+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24725+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24726+ * POSSIBILITY OF SUCH DAMAGE.
24727+ */
24728+#ifndef __FSL_DPRTC_H
24729+#define __FSL_DPRTC_H
24730+
24731+/* Data Path Real Time Counter API
24732+ * Contains initialization APIs and runtime control APIs for RTC
24733+ */
24734+
24735+struct fsl_mc_io;
24736+
24737+/**
24738+ * Number of irq's
24739+ */
24740+#define DPRTC_MAX_IRQ_NUM 1
24741+#define DPRTC_IRQ_INDEX 0
24742+
24743+/**
24744+ * Interrupt event masks:
24745+ */
24746+
24747+/**
24748+ * Interrupt event mask indicating alarm event had occured
24749+ */
24750+#define DPRTC_EVENT_ALARM 0x40000000
24751+/**
24752+ * Interrupt event mask indicating periodic pulse event had occured
24753+ */
24754+#define DPRTC_EVENT_PPS 0x08000000
24755+
24756+/**
24757+ * dprtc_open() - Open a control session for the specified object.
24758+ * @mc_io: Pointer to MC portal's I/O object
24759+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24760+ * @dprtc_id: DPRTC unique ID
24761+ * @token: Returned token; use in subsequent API calls
24762+ *
24763+ * This function can be used to open a control session for an
24764+ * already created object; an object may have been declared in
24765+ * the DPL or by calling the dprtc_create function.
24766+ * This function returns a unique authentication token,
24767+ * associated with the specific object ID and the specific MC
24768+ * portal; this token must be used in all subsequent commands for
24769+ * this specific object
24770+ *
24771+ * Return: '0' on Success; Error code otherwise.
24772+ */
24773+int dprtc_open(struct fsl_mc_io *mc_io,
24774+ uint32_t cmd_flags,
24775+ int dprtc_id,
24776+ uint16_t *token);
24777+
24778+/**
24779+ * dprtc_close() - Close the control session of the object
24780+ * @mc_io: Pointer to MC portal's I/O object
24781+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24782+ * @token: Token of DPRTC object
24783+ *
24784+ * After this function is called, no further operations are
24785+ * allowed on the object without opening a new control session.
24786+ *
24787+ * Return: '0' on Success; Error code otherwise.
24788+ */
24789+int dprtc_close(struct fsl_mc_io *mc_io,
24790+ uint32_t cmd_flags,
24791+ uint16_t token);
24792+
24793+/**
24794+ * struct dprtc_cfg - Structure representing DPRTC configuration
24795+ * @options: place holder
24796+ */
24797+struct dprtc_cfg {
24798+ uint32_t options;
24799+};
24800+
24801+/**
24802+ * dprtc_create() - Create the DPRTC object.
24803+ * @mc_io: Pointer to MC portal's I/O object
24804+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24805+ * @cfg: Configuration structure
24806+ * @token: Returned token; use in subsequent API calls
24807+ *
24808+ * Create the DPRTC object, allocate required resources and
24809+ * perform required initialization.
24810+ *
24811+ * The object can be created either by declaring it in the
24812+ * DPL file, or by calling this function.
24813+ * This function returns a unique authentication token,
24814+ * associated with the specific object ID and the specific MC
24815+ * portal; this token must be used in all subsequent calls to
24816+ * this specific object. For objects that are created using the
24817+ * DPL file, call dprtc_open function to get an authentication
24818+ * token first.
24819+ *
24820+ * Return: '0' on Success; Error code otherwise.
24821+ */
24822+int dprtc_create(struct fsl_mc_io *mc_io,
24823+ uint32_t cmd_flags,
24824+ const struct dprtc_cfg *cfg,
24825+ uint16_t *token);
24826+
24827+/**
24828+ * dprtc_destroy() - Destroy the DPRTC object and release all its resources.
24829+ * @mc_io: Pointer to MC portal's I/O object
24830+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24831+ * @token: Token of DPRTC object
24832+ *
24833+ * Return: '0' on Success; error code otherwise.
24834+ */
24835+int dprtc_destroy(struct fsl_mc_io *mc_io,
24836+ uint32_t cmd_flags,
24837+ uint16_t token);
24838+
24839+/**
24840+ * dprtc_set_clock_offset() - Sets the clock's offset
24841+ * (usually relative to another clock).
24842+ *
24843+ * @mc_io: Pointer to MC portal's I/O object
24844+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24845+ * @token: Token of DPRTC object
24846+ * @offset: New clock offset (in nanoseconds).
24847+ *
24848+ * Return: '0' on Success; Error code otherwise.
24849+ */
24850+int dprtc_set_clock_offset(struct fsl_mc_io *mc_io,
24851+ uint32_t cmd_flags,
24852+ uint16_t token,
24853+ int64_t offset);
24854+
24855+/**
24856+ * dprtc_set_freq_compensation() - Sets a new frequency compensation value.
24857+ *
24858+ * @mc_io: Pointer to MC portal's I/O object
24859+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24860+ * @token: Token of DPRTC object
24861+ * @freq_compensation:
24862+ * The new frequency compensation value to set.
24863+ *
24864+ * Return: '0' on Success; Error code otherwise.
24865+ */
24866+int dprtc_set_freq_compensation(struct fsl_mc_io *mc_io,
24867+ uint32_t cmd_flags,
24868+ uint16_t token,
24869+ uint32_t freq_compensation);
24870+
24871+/**
24872+ * dprtc_get_freq_compensation() - Retrieves the frequency compensation value
24873+ *
24874+ * @mc_io: Pointer to MC portal's I/O object
24875+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24876+ * @token: Token of DPRTC object
24877+ * @freq_compensation:
24878+ * Frequency compensation value
24879+ *
24880+ * Return: '0' on Success; Error code otherwise.
24881+ */
24882+int dprtc_get_freq_compensation(struct fsl_mc_io *mc_io,
24883+ uint32_t cmd_flags,
24884+ uint16_t token,
24885+ uint32_t *freq_compensation);
24886+
24887+/**
24888+ * dprtc_get_time() - Returns the current RTC time.
24889+ *
24890+ * @mc_io: Pointer to MC portal's I/O object
24891+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24892+ * @token: Token of DPRTC object
24893+ * @time: Current RTC time.
24894+ *
24895+ * Return: '0' on Success; Error code otherwise.
24896+ */
24897+int dprtc_get_time(struct fsl_mc_io *mc_io,
24898+ uint32_t cmd_flags,
24899+ uint16_t token,
24900+ uint64_t *time);
24901+
24902+/**
24903+ * dprtc_set_time() - Updates current RTC time.
24904+ *
24905+ * @mc_io: Pointer to MC portal's I/O object
24906+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24907+ * @token: Token of DPRTC object
24908+ * @time: New RTC time.
24909+ *
24910+ * Return: '0' on Success; Error code otherwise.
24911+ */
24912+int dprtc_set_time(struct fsl_mc_io *mc_io,
24913+ uint32_t cmd_flags,
24914+ uint16_t token,
24915+ uint64_t time);
24916+
24917+/**
24918+ * dprtc_set_alarm() - Defines and sets alarm.
24919+ *
24920+ * @mc_io: Pointer to MC portal's I/O object
24921+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24922+ * @token: Token of DPRTC object
24923+ * @time: In nanoseconds, the time when the alarm
24924+ * should go off - must be a multiple of
24925+ * 1 microsecond
24926+ *
24927+ * Return: '0' on Success; Error code otherwise.
24928+ */
24929+int dprtc_set_alarm(struct fsl_mc_io *mc_io,
24930+ uint32_t cmd_flags,
24931+ uint16_t token,
24932+ uint64_t time);
24933+
24934+/**
24935+ * struct dprtc_irq_cfg - IRQ configuration
24936+ * @addr: Address that must be written to signal a message-based interrupt
24937+ * @val: Value to write into irq_addr address
24938+ * @irq_num: A user defined number associated with this IRQ
24939+ */
24940+struct dprtc_irq_cfg {
24941+ uint64_t addr;
24942+ uint32_t val;
24943+ int irq_num;
24944+};
24945+
24946+/**
24947+ * dprtc_set_irq() - Set IRQ information for the DPRTC to trigger an interrupt.
24948+ * @mc_io: Pointer to MC portal's I/O object
24949+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24950+ * @token: Token of DPRTC object
24951+ * @irq_index: Identifies the interrupt index to configure
24952+ * @irq_cfg: IRQ configuration
24953+ *
24954+ * Return: '0' on Success; Error code otherwise.
24955+ */
24956+int dprtc_set_irq(struct fsl_mc_io *mc_io,
24957+ uint32_t cmd_flags,
24958+ uint16_t token,
24959+ uint8_t irq_index,
24960+ struct dprtc_irq_cfg *irq_cfg);
24961+
24962+/**
24963+ * dprtc_get_irq() - Get IRQ information from the DPRTC.
24964+ * @mc_io: Pointer to MC portal's I/O object
24965+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24966+ * @token: Token of DPRTC object
24967+ * @irq_index: The interrupt index to configure
24968+ * @type: Interrupt type: 0 represents message interrupt
24969+ * type (both irq_addr and irq_val are valid)
24970+ * @irq_cfg: IRQ attributes
24971+ *
24972+ * Return: '0' on Success; Error code otherwise.
24973+ */
24974+int dprtc_get_irq(struct fsl_mc_io *mc_io,
24975+ uint32_t cmd_flags,
24976+ uint16_t token,
24977+ uint8_t irq_index,
24978+ int *type,
24979+ struct dprtc_irq_cfg *irq_cfg);
24980+
24981+/**
24982+ * dprtc_set_irq_enable() - Set overall interrupt state.
24983+ * @mc_io: Pointer to MC portal's I/O object
24984+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
24985+ * @token: Token of DPRTC object
24986+ * @irq_index: The interrupt index to configure
24987+ * @en: Interrupt state - enable = 1, disable = 0
24988+ *
24989+ * Allows GPP software to control when interrupts are generated.
24990+ * Each interrupt can have up to 32 causes. The enable/disable control's the
24991+ * overall interrupt state. if the interrupt is disabled no causes will cause
24992+ * an interrupt.
24993+ *
24994+ * Return: '0' on Success; Error code otherwise.
24995+ */
24996+int dprtc_set_irq_enable(struct fsl_mc_io *mc_io,
24997+ uint32_t cmd_flags,
24998+ uint16_t token,
24999+ uint8_t irq_index,
25000+ uint8_t en);
25001+
25002+/**
25003+ * dprtc_get_irq_enable() - Get overall interrupt state
25004+ * @mc_io: Pointer to MC portal's I/O object
25005+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25006+ * @token: Token of DPRTC object
25007+ * @irq_index: The interrupt index to configure
25008+ * @en: Returned interrupt state - enable = 1, disable = 0
25009+ *
25010+ * Return: '0' on Success; Error code otherwise.
25011+ */
25012+int dprtc_get_irq_enable(struct fsl_mc_io *mc_io,
25013+ uint32_t cmd_flags,
25014+ uint16_t token,
25015+ uint8_t irq_index,
25016+ uint8_t *en);
25017+
25018+/**
25019+ * dprtc_set_irq_mask() - Set interrupt mask.
25020+ * @mc_io: Pointer to MC portal's I/O object
25021+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25022+ * @token: Token of DPRTC object
25023+ * @irq_index: The interrupt index to configure
25024+ * @mask: Event mask to trigger interrupt;
25025+ * each bit:
25026+ * 0 = ignore event
25027+ * 1 = consider event for asserting IRQ
25028+ *
25029+ * Every interrupt can have up to 32 causes and the interrupt model supports
25030+ * masking/unmasking each cause independently
25031+ *
25032+ * Return: '0' on Success; Error code otherwise.
25033+ */
25034+int dprtc_set_irq_mask(struct fsl_mc_io *mc_io,
25035+ uint32_t cmd_flags,
25036+ uint16_t token,
25037+ uint8_t irq_index,
25038+ uint32_t mask);
25039+
25040+/**
25041+ * dprtc_get_irq_mask() - Get interrupt mask.
25042+ * @mc_io: Pointer to MC portal's I/O object
25043+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25044+ * @token: Token of DPRTC object
25045+ * @irq_index: The interrupt index to configure
25046+ * @mask: Returned event mask to trigger interrupt
25047+ *
25048+ * Every interrupt can have up to 32 causes and the interrupt model supports
25049+ * masking/unmasking each cause independently
25050+ *
25051+ * Return: '0' on Success; Error code otherwise.
25052+ */
25053+int dprtc_get_irq_mask(struct fsl_mc_io *mc_io,
25054+ uint32_t cmd_flags,
25055+ uint16_t token,
25056+ uint8_t irq_index,
25057+ uint32_t *mask);
25058+
25059+/**
25060+ * dprtc_get_irq_status() - Get the current status of any pending interrupts.
25061+ *
25062+ * @mc_io: Pointer to MC portal's I/O object
25063+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25064+ * @token: Token of DPRTC object
25065+ * @irq_index: The interrupt index to configure
25066+ * @status: Returned interrupts status - one bit per cause:
25067+ * 0 = no interrupt pending
25068+ * 1 = interrupt pending
25069+ *
25070+ * Return: '0' on Success; Error code otherwise.
25071+ */
25072+int dprtc_get_irq_status(struct fsl_mc_io *mc_io,
25073+ uint32_t cmd_flags,
25074+ uint16_t token,
25075+ uint8_t irq_index,
25076+ uint32_t *status);
25077+
25078+/**
25079+ * dprtc_clear_irq_status() - Clear a pending interrupt's status
25080+ *
25081+ * @mc_io: Pointer to MC portal's I/O object
25082+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25083+ * @token: Token of DPRTC object
25084+ * @irq_index: The interrupt index to configure
25085+ * @status: Bits to clear (W1C) - one bit per cause:
25086+ * 0 = don't change
25087+ * 1 = clear status bit
25088+ *
25089+ * Return: '0' on Success; Error code otherwise.
25090+ */
25091+int dprtc_clear_irq_status(struct fsl_mc_io *mc_io,
25092+ uint32_t cmd_flags,
25093+ uint16_t token,
25094+ uint8_t irq_index,
25095+ uint32_t status);
25096+
25097+/**
25098+ * struct dprtc_attr - Structure representing DPRTC attributes
25099+ * @id: DPRTC object ID
25100+ * @version: DPRTC version
25101+ */
25102+struct dprtc_attr {
25103+ int id;
25104+ /**
25105+ * struct version - Structure representing DPRTC version
25106+ * @major: DPRTC major version
25107+ * @minor: DPRTC minor version
25108+ */
25109+ struct {
25110+ uint16_t major;
25111+ uint16_t minor;
25112+ } version;
25113+};
25114+
25115+/**
25116+ * dprtc_get_attributes - Retrieve DPRTC attributes.
25117+ *
25118+ * @mc_io: Pointer to MC portal's I/O object
25119+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25120+ * @token: Token of DPRTC object
25121+ * @attr: Returned object's attributes
25122+ *
25123+ * Return: '0' on Success; Error code otherwise.
25124+ */
25125+int dprtc_get_attributes(struct fsl_mc_io *mc_io,
25126+ uint32_t cmd_flags,
25127+ uint16_t token,
25128+ struct dprtc_attr *attr);
25129+
25130+#endif /* __FSL_DPRTC_H */
25131diff --git a/drivers/net/dpaa2/mc/fsl_dprtc_cmd.h b/drivers/net/dpaa2/mc/fsl_dprtc_cmd.h
25132new file mode 100644
25133index 0000000..aeccece
25134--- /dev/null
25135+++ b/drivers/net/dpaa2/mc/fsl_dprtc_cmd.h
25136@@ -0,0 +1,181 @@
25137+/* Copyright 2013-2015 Freescale Semiconductor Inc.
25138+ *
25139+ * Redistribution and use in source and binary forms, with or without
25140+ * modification, are permitted provided that the following conditions are met:
25141+ * * Redistributions of source code must retain the above copyright
25142+ * notice, this list of conditions and the following disclaimer.
25143+ * * Redistributions in binary form must reproduce the above copyright
25144+ * notice, this list of conditions and the following disclaimer in the
25145+ * documentation and/or other materials provided with the distribution.
25146+ * * Neither the name of the above-listed copyright holders nor the
25147+ * names of any contributors may be used to endorse or promote products
25148+ * derived from this software without specific prior written permission.
25149+ *
25150+ *
25151+ * ALTERNATIVELY, this software may be distributed under the terms of the
25152+ * GNU General Public License ("GPL") as published by the Free Software
25153+ * Foundation, either version 2 of that License or (at your option) any
25154+ * later version.
25155+ *
25156+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25157+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25158+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25159+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
25160+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25161+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25162+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25163+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25164+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25165+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25166+ * POSSIBILITY OF SUCH DAMAGE.
25167+ */
25168+#ifndef _FSL_DPRTC_CMD_H
25169+#define _FSL_DPRTC_CMD_H
25170+
25171+/* DPRTC Version */
25172+#define DPRTC_VER_MAJOR 1
25173+#define DPRTC_VER_MINOR 0
25174+
25175+/* Command IDs */
25176+#define DPRTC_CMDID_CLOSE 0x800
25177+#define DPRTC_CMDID_OPEN 0x810
25178+#define DPRTC_CMDID_CREATE 0x910
25179+#define DPRTC_CMDID_DESTROY 0x900
25180+
25181+#define DPRTC_CMDID_ENABLE 0x002
25182+#define DPRTC_CMDID_DISABLE 0x003
25183+#define DPRTC_CMDID_GET_ATTR 0x004
25184+#define DPRTC_CMDID_RESET 0x005
25185+#define DPRTC_CMDID_IS_ENABLED 0x006
25186+
25187+#define DPRTC_CMDID_SET_IRQ 0x010
25188+#define DPRTC_CMDID_GET_IRQ 0x011
25189+#define DPRTC_CMDID_SET_IRQ_ENABLE 0x012
25190+#define DPRTC_CMDID_GET_IRQ_ENABLE 0x013
25191+#define DPRTC_CMDID_SET_IRQ_MASK 0x014
25192+#define DPRTC_CMDID_GET_IRQ_MASK 0x015
25193+#define DPRTC_CMDID_GET_IRQ_STATUS 0x016
25194+#define DPRTC_CMDID_CLEAR_IRQ_STATUS 0x017
25195+
25196+#define DPRTC_CMDID_SET_CLOCK_OFFSET 0x1d0
25197+#define DPRTC_CMDID_SET_FREQ_COMPENSATION 0x1d1
25198+#define DPRTC_CMDID_GET_FREQ_COMPENSATION 0x1d2
25199+#define DPRTC_CMDID_GET_TIME 0x1d3
25200+#define DPRTC_CMDID_SET_TIME 0x1d4
25201+#define DPRTC_CMDID_SET_ALARM 0x1d5
25202+#define DPRTC_CMDID_SET_PERIODIC_PULSE 0x1d6
25203+#define DPRTC_CMDID_CLEAR_PERIODIC_PULSE 0x1d7
25204+#define DPRTC_CMDID_SET_EXT_TRIGGER 0x1d8
25205+#define DPRTC_CMDID_CLEAR_EXT_TRIGGER 0x1d9
25206+#define DPRTC_CMDID_GET_EXT_TRIGGER_TIMESTAMP 0x1dA
25207+
25208+/* cmd, param, offset, width, type, arg_name */
25209+#define DPRTC_CMD_OPEN(cmd, dpbp_id) \
25210+ MC_CMD_OP(cmd, 0, 0, 32, int, dpbp_id)
25211+
25212+/* cmd, param, offset, width, type, arg_name */
25213+#define DPRTC_RSP_IS_ENABLED(cmd, en) \
25214+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
25215+
25216+/* cmd, param, offset, width, type, arg_name */
25217+#define DPRTC_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
25218+do { \
25219+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
25220+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
25221+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
25222+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
25223+} while (0)
25224+
25225+/* cmd, param, offset, width, type, arg_name */
25226+#define DPRTC_CMD_GET_IRQ(cmd, irq_index) \
25227+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
25228+
25229+/* cmd, param, offset, width, type, arg_name */
25230+#define DPRTC_RSP_GET_IRQ(cmd, type, irq_cfg) \
25231+do { \
25232+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
25233+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \
25234+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
25235+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
25236+} while (0)
25237+
25238+/* cmd, param, offset, width, type, arg_name */
25239+#define DPRTC_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \
25240+do { \
25241+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \
25242+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
25243+} while (0)
25244+
25245+/* cmd, param, offset, width, type, arg_name */
25246+#define DPRTC_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
25247+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
25248+
25249+/* cmd, param, offset, width, type, arg_name */
25250+#define DPRTC_RSP_GET_IRQ_ENABLE(cmd, en) \
25251+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en)
25252+
25253+/* cmd, param, offset, width, type, arg_name */
25254+#define DPRTC_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
25255+do { \
25256+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask);\
25257+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
25258+} while (0)
25259+
25260+/* cmd, param, offset, width, type, arg_name */
25261+#define DPRTC_CMD_GET_IRQ_MASK(cmd, irq_index) \
25262+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
25263+
25264+/* cmd, param, offset, width, type, arg_name */
25265+#define DPRTC_RSP_GET_IRQ_MASK(cmd, mask) \
25266+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
25267+
25268+/* cmd, param, offset, width, type, arg_name */
25269+#define DPRTC_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
25270+do { \
25271+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
25272+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
25273+} while (0)
25274+/* cmd, param, offset, width, type, arg_name */
25275+#define DPRTC_RSP_GET_IRQ_STATUS(cmd, status) \
25276+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
25277+
25278+/* cmd, param, offset, width, type, arg_name */
25279+#define DPRTC_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
25280+do { \
25281+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
25282+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
25283+} while (0)
25284+
25285+/* cmd, param, offset, width, type, arg_name */
25286+#define DPRTC_RSP_GET_ATTRIBUTES(cmd, attr) \
25287+do { \
25288+ MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\
25289+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
25290+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
25291+} while (0)
25292+
25293+/* cmd, param, offset, width, type, arg_name */
25294+#define DPRTC_CMD_SET_CLOCK_OFFSET(cmd, offset) \
25295+ MC_CMD_OP(cmd, 0, 0, 64, int64_t, offset)
25296+
25297+/* cmd, param, offset, width, type, arg_name */
25298+#define DPRTC_CMD_SET_FREQ_COMPENSATION(cmd, freq_compensation) \
25299+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, freq_compensation)
25300+
25301+/* cmd, param, offset, width, type, arg_name */
25302+#define DPRTC_RSP_GET_FREQ_COMPENSATION(cmd, freq_compensation) \
25303+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, freq_compensation)
25304+
25305+/* cmd, param, offset, width, type, arg_name */
25306+#define DPRTC_RSP_GET_TIME(cmd, time) \
25307+ MC_RSP_OP(cmd, 0, 0, 64, uint64_t, time)
25308+
25309+/* cmd, param, offset, width, type, arg_name */
25310+#define DPRTC_CMD_SET_TIME(cmd, time) \
25311+ MC_CMD_OP(cmd, 0, 0, 64, uint64_t, time)
25312+
25313+/* cmd, param, offset, width, type, arg_name */
25314+#define DPRTC_CMD_SET_ALARM(cmd, time) \
25315+ MC_CMD_OP(cmd, 0, 0, 64, uint64_t, time)
25316+
25317+#endif /* _FSL_DPRTC_CMD_H */
25318diff --git a/drivers/net/dpaa2/mc/fsl_dpseci.h b/drivers/net/dpaa2/mc/fsl_dpseci.h
25319new file mode 100644
25320index 0000000..1dd7215
25321--- /dev/null
25322+++ b/drivers/net/dpaa2/mc/fsl_dpseci.h
25323@@ -0,0 +1,647 @@
25324+/* Copyright 2013-2015 Freescale Semiconductor Inc.
25325+ *
25326+ * Redistribution and use in source and binary forms, with or without
25327+ * modification, are permitted provided that the following conditions are met:
25328+ * * Redistributions of source code must retain the above copyright
25329+ * notice, this list of conditions and the following disclaimer.
25330+ * * Redistributions in binary form must reproduce the above copyright
25331+ * notice, this list of conditions and the following disclaimer in the
25332+ * documentation and/or other materials provided with the distribution.
25333+ * * Neither the name of the above-listed copyright holders nor the
25334+ * names of any contributors may be used to endorse or promote products
25335+ * derived from this software without specific prior written permission.
25336+ *
25337+ *
25338+ * ALTERNATIVELY, this software may be distributed under the terms of the
25339+ * GNU General Public License ("GPL") as published by the Free Software
25340+ * Foundation, either version 2 of that License or (at your option) any
25341+ * later version.
25342+ *
25343+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25344+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25345+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25346+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
25347+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25348+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25349+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25350+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25351+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25352+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25353+ * POSSIBILITY OF SUCH DAMAGE.
25354+ */
25355+#ifndef __FSL_DPSECI_H
25356+#define __FSL_DPSECI_H
25357+
25358+/* Data Path SEC Interface API
25359+ * Contains initialization APIs and runtime control APIs for DPSECI
25360+ */
25361+
25362+struct fsl_mc_io;
25363+
25364+/**
25365+ * General DPSECI macros
25366+ */
25367+
25368+/**
25369+ * Maximum number of Tx/Rx priorities per DPSECI object
25370+ */
25371+#define DPSECI_PRIO_NUM 8
25372+
25373+/**
25374+ * All queues considered; see dpseci_set_rx_queue()
25375+ */
25376+#define DPSECI_ALL_QUEUES (uint8_t)(-1)
25377+
25378+/**
25379+ * dpseci_open() - Open a control session for the specified object
25380+ * @mc_io: Pointer to MC portal's I/O object
25381+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25382+ * @dpseci_id: DPSECI unique ID
25383+ * @token: Returned token; use in subsequent API calls
25384+ *
25385+ * This function can be used to open a control session for an
25386+ * already created object; an object may have been declared in
25387+ * the DPL or by calling the dpseci_create() function.
25388+ * This function returns a unique authentication token,
25389+ * associated with the specific object ID and the specific MC
25390+ * portal; this token must be used in all subsequent commands for
25391+ * this specific object.
25392+ *
25393+ * Return: '0' on Success; Error code otherwise.
25394+ */
25395+int dpseci_open(struct fsl_mc_io *mc_io,
25396+ uint32_t cmd_flags,
25397+ int dpseci_id,
25398+ uint16_t *token);
25399+
25400+/**
25401+ * dpseci_close() - Close the control session of the object
25402+ * @mc_io: Pointer to MC portal's I/O object
25403+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25404+ * @token: Token of DPSECI object
25405+ *
25406+ * After this function is called, no further operations are
25407+ * allowed on the object without opening a new control session.
25408+ *
25409+ * Return: '0' on Success; Error code otherwise.
25410+ */
25411+int dpseci_close(struct fsl_mc_io *mc_io,
25412+ uint32_t cmd_flags,
25413+ uint16_t token);
25414+
25415+/**
25416+ * struct dpseci_cfg - Structure representing DPSECI configuration
25417+ * @num_tx_queues: num of queues towards the SEC
25418+ * @num_rx_queues: num of queues back from the SEC
25419+ * @priorities: Priorities for the SEC hardware processing;
25420+ * each place in the array is the priority of the tx queue
25421+ * towards the SEC,
25422+ * valid priorities are configured with values 1-8;
25423+ */
25424+struct dpseci_cfg {
25425+ uint8_t num_tx_queues;
25426+ uint8_t num_rx_queues;
25427+ uint8_t priorities[DPSECI_PRIO_NUM];
25428+};
25429+
25430+/**
25431+ * dpseci_create() - Create the DPSECI object
25432+ * @mc_io: Pointer to MC portal's I/O object
25433+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25434+ * @cfg: Configuration structure
25435+ * @token: Returned token; use in subsequent API calls
25436+ *
25437+ * Create the DPSECI object, allocate required resources and
25438+ * perform required initialization.
25439+ *
25440+ * The object can be created either by declaring it in the
25441+ * DPL file, or by calling this function.
25442+ *
25443+ * This function returns a unique authentication token,
25444+ * associated with the specific object ID and the specific MC
25445+ * portal; this token must be used in all subsequent calls to
25446+ * this specific object. For objects that are created using the
25447+ * DPL file, call dpseci_open() function to get an authentication
25448+ * token first.
25449+ *
25450+ * Return: '0' on Success; Error code otherwise.
25451+ */
25452+int dpseci_create(struct fsl_mc_io *mc_io,
25453+ uint32_t cmd_flags,
25454+ const struct dpseci_cfg *cfg,
25455+ uint16_t *token);
25456+
25457+/**
25458+ * dpseci_destroy() - Destroy the DPSECI object and release all its resources.
25459+ * @mc_io: Pointer to MC portal's I/O object
25460+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25461+ * @token: Token of DPSECI object
25462+ *
25463+ * Return: '0' on Success; error code otherwise.
25464+ */
25465+int dpseci_destroy(struct fsl_mc_io *mc_io,
25466+ uint32_t cmd_flags,
25467+ uint16_t token);
25468+
25469+/**
25470+ * dpseci_enable() - Enable the DPSECI, allow sending and receiving frames.
25471+ * @mc_io: Pointer to MC portal's I/O object
25472+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25473+ * @token: Token of DPSECI object
25474+ *
25475+ * Return: '0' on Success; Error code otherwise.
25476+ */
25477+int dpseci_enable(struct fsl_mc_io *mc_io,
25478+ uint32_t cmd_flags,
25479+ uint16_t token);
25480+
25481+/**
25482+ * dpseci_disable() - Disable the DPSECI, stop sending and receiving frames.
25483+ * @mc_io: Pointer to MC portal's I/O object
25484+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25485+ * @token: Token of DPSECI object
25486+ *
25487+ * Return: '0' on Success; Error code otherwise.
25488+ */
25489+int dpseci_disable(struct fsl_mc_io *mc_io,
25490+ uint32_t cmd_flags,
25491+ uint16_t token);
25492+
25493+/**
25494+ * dpseci_is_enabled() - Check if the DPSECI is enabled.
25495+ * @mc_io: Pointer to MC portal's I/O object
25496+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25497+ * @token: Token of DPSECI object
25498+ * @en: Returns '1' if object is enabled; '0' otherwise
25499+ *
25500+ * Return: '0' on Success; Error code otherwise.
25501+ */
25502+int dpseci_is_enabled(struct fsl_mc_io *mc_io,
25503+ uint32_t cmd_flags,
25504+ uint16_t token,
25505+ int *en);
25506+
25507+/**
25508+ * dpseci_reset() - Reset the DPSECI, returns the object to initial state.
25509+ * @mc_io: Pointer to MC portal's I/O object
25510+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25511+ * @token: Token of DPSECI object
25512+ *
25513+ * Return: '0' on Success; Error code otherwise.
25514+ */
25515+int dpseci_reset(struct fsl_mc_io *mc_io,
25516+ uint32_t cmd_flags,
25517+ uint16_t token);
25518+
25519+/**
25520+ * struct dpseci_irq_cfg - IRQ configuration
25521+ * @addr: Address that must be written to signal a message-based interrupt
25522+ * @val: Value to write into irq_addr address
25523+ * @irq_num: A user defined number associated with this IRQ
25524+ */
25525+struct dpseci_irq_cfg {
25526+ uint64_t addr;
25527+ uint32_t val;
25528+ int irq_num;
25529+};
25530+
25531+/**
25532+ * dpseci_set_irq() - Set IRQ information for the DPSECI to trigger an interrupt
25533+ * @mc_io: Pointer to MC portal's I/O object
25534+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25535+ * @token: Token of DPSECI object
25536+ * @irq_index: Identifies the interrupt index to configure
25537+ * @irq_cfg: IRQ configuration
25538+ *
25539+ * Return: '0' on Success; Error code otherwise.
25540+ */
25541+int dpseci_set_irq(struct fsl_mc_io *mc_io,
25542+ uint32_t cmd_flags,
25543+ uint16_t token,
25544+ uint8_t irq_index,
25545+ struct dpseci_irq_cfg *irq_cfg);
25546+
25547+/**
25548+ * dpseci_get_irq() - Get IRQ information from the DPSECI
25549+ *
25550+ * @mc_io: Pointer to MC portal's I/O object
25551+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25552+ * @token: Token of DPSECI object
25553+ * @irq_index: The interrupt index to configure
25554+ * @type: Interrupt type: 0 represents message interrupt
25555+ * type (both irq_addr and irq_val are valid)
25556+ * @irq_cfg: IRQ attributes
25557+ *
25558+ * Return: '0' on Success; Error code otherwise.
25559+ */
25560+int dpseci_get_irq(struct fsl_mc_io *mc_io,
25561+ uint32_t cmd_flags,
25562+ uint16_t token,
25563+ uint8_t irq_index,
25564+ int *type,
25565+ struct dpseci_irq_cfg *irq_cfg);
25566+
25567+/**
25568+ * dpseci_set_irq_enable() - Set overall interrupt state.
25569+ * @mc_io: Pointer to MC portal's I/O object
25570+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25571+ * @token: Token of DPSECI object
25572+ * @irq_index: The interrupt index to configure
25573+ * @en: Interrupt state - enable = 1, disable = 0
25574+ *
25575+ * Allows GPP software to control when interrupts are generated.
25576+ * Each interrupt can have up to 32 causes. The enable/disable control's the
25577+ * overall interrupt state. if the interrupt is disabled no causes will cause
25578+ * an interrupt
25579+ *
25580+ * Return: '0' on Success; Error code otherwise.
25581+ */
25582+int dpseci_set_irq_enable(struct fsl_mc_io *mc_io,
25583+ uint32_t cmd_flags,
25584+ uint16_t token,
25585+ uint8_t irq_index,
25586+ uint8_t en);
25587+
25588+/**
25589+ * dpseci_get_irq_enable() - Get overall interrupt state
25590+ * @mc_io: Pointer to MC portal's I/O object
25591+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25592+ * @token: Token of DPSECI object
25593+ * @irq_index: The interrupt index to configure
25594+ * @en: Returned Interrupt state - enable = 1, disable = 0
25595+ *
25596+ * Return: '0' on Success; Error code otherwise.
25597+ */
25598+int dpseci_get_irq_enable(struct fsl_mc_io *mc_io,
25599+ uint32_t cmd_flags,
25600+ uint16_t token,
25601+ uint8_t irq_index,
25602+ uint8_t *en);
25603+
25604+/**
25605+ * dpseci_set_irq_mask() - Set interrupt mask.
25606+ * @mc_io: Pointer to MC portal's I/O object
25607+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25608+ * @token: Token of DPSECI object
25609+ * @irq_index: The interrupt index to configure
25610+ * @mask: event mask to trigger interrupt;
25611+ * each bit:
25612+ * 0 = ignore event
25613+ * 1 = consider event for asserting IRQ
25614+ *
25615+ * Every interrupt can have up to 32 causes and the interrupt model supports
25616+ * masking/unmasking each cause independently
25617+ *
25618+ * Return: '0' on Success; Error code otherwise.
25619+ */
25620+int dpseci_set_irq_mask(struct fsl_mc_io *mc_io,
25621+ uint32_t cmd_flags,
25622+ uint16_t token,
25623+ uint8_t irq_index,
25624+ uint32_t mask);
25625+
25626+/**
25627+ * dpseci_get_irq_mask() - Get interrupt mask.
25628+ * @mc_io: Pointer to MC portal's I/O object
25629+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25630+ * @token: Token of DPSECI object
25631+ * @irq_index: The interrupt index to configure
25632+ * @mask: Returned event mask to trigger interrupt
25633+ *
25634+ * Every interrupt can have up to 32 causes and the interrupt model supports
25635+ * masking/unmasking each cause independently
25636+ *
25637+ * Return: '0' on Success; Error code otherwise.
25638+ */
25639+int dpseci_get_irq_mask(struct fsl_mc_io *mc_io,
25640+ uint32_t cmd_flags,
25641+ uint16_t token,
25642+ uint8_t irq_index,
25643+ uint32_t *mask);
25644+
25645+/**
25646+ * dpseci_get_irq_status() - Get the current status of any pending interrupts
25647+ * @mc_io: Pointer to MC portal's I/O object
25648+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25649+ * @token: Token of DPSECI object
25650+ * @irq_index: The interrupt index to configure
25651+ * @status: Returned interrupts status - one bit per cause:
25652+ * 0 = no interrupt pending
25653+ * 1 = interrupt pending
25654+ *
25655+ * Return: '0' on Success; Error code otherwise.
25656+ */
25657+int dpseci_get_irq_status(struct fsl_mc_io *mc_io,
25658+ uint32_t cmd_flags,
25659+ uint16_t token,
25660+ uint8_t irq_index,
25661+ uint32_t *status);
25662+
25663+/**
25664+ * dpseci_clear_irq_status() - Clear a pending interrupt's status
25665+ * @mc_io: Pointer to MC portal's I/O object
25666+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25667+ * @token: Token of DPSECI object
25668+ * @irq_index: The interrupt index to configure
25669+ * @status: bits to clear (W1C) - one bit per cause:
25670+ * 0 = don't change
25671+ * 1 = clear status bit
25672+ *
25673+ * Return: '0' on Success; Error code otherwise.
25674+ */
25675+int dpseci_clear_irq_status(struct fsl_mc_io *mc_io,
25676+ uint32_t cmd_flags,
25677+ uint16_t token,
25678+ uint8_t irq_index,
25679+ uint32_t status);
25680+
25681+/**
25682+ * struct dpseci_attr - Structure representing DPSECI attributes
25683+ * @id: DPSECI object ID
25684+ * @version: DPSECI version
25685+ * @num_tx_queues: number of queues towards the SEC
25686+ * @num_rx_queues: number of queues back from the SEC
25687+ */
25688+struct dpseci_attr {
25689+ int id;
25690+ /**
25691+ * struct version - DPSECI version
25692+ * @major: DPSECI major version
25693+ * @minor: DPSECI minor version
25694+ */
25695+ struct {
25696+ uint16_t major;
25697+ uint16_t minor;
25698+ } version;
25699+ uint8_t num_tx_queues;
25700+ uint8_t num_rx_queues;
25701+};
25702+
25703+/**
25704+ * dpseci_get_attributes() - Retrieve DPSECI attributes.
25705+ * @mc_io: Pointer to MC portal's I/O object
25706+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25707+ * @token: Token of DPSECI object
25708+ * @attr: Returned object's attributes
25709+ *
25710+ * Return: '0' on Success; Error code otherwise.
25711+ */
25712+int dpseci_get_attributes(struct fsl_mc_io *mc_io,
25713+ uint32_t cmd_flags,
25714+ uint16_t token,
25715+ struct dpseci_attr *attr);
25716+
25717+/**
25718+ * enum dpseci_dest - DPSECI destination types
25719+ * @DPSECI_DEST_NONE: Unassigned destination; The queue is set in parked mode
25720+ * and does not generate FQDAN notifications; user is expected to
25721+ * dequeue from the queue based on polling or other user-defined
25722+ * method
25723+ * @DPSECI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN
25724+ * notifications to the specified DPIO; user is expected to dequeue
25725+ * from the queue only after notification is received
25726+ * @DPSECI_DEST_DPCON: The queue is set in schedule mode and does not generate
25727+ * FQDAN notifications, but is connected to the specified DPCON
25728+ * object; user is expected to dequeue from the DPCON channel
25729+ */
25730+enum dpseci_dest {
25731+ DPSECI_DEST_NONE = 0,
25732+ DPSECI_DEST_DPIO = 1,
25733+ DPSECI_DEST_DPCON = 2
25734+};
25735+
25736+/**
25737+ * struct dpseci_dest_cfg - Structure representing DPSECI destination parameters
25738+ * @dest_type: Destination type
25739+ * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type
25740+ * @priority: Priority selection within the DPIO or DPCON channel; valid values
25741+ * are 0-1 or 0-7, depending on the number of priorities in that
25742+ * channel; not relevant for 'DPSECI_DEST_NONE' option
25743+ */
25744+struct dpseci_dest_cfg {
25745+ enum dpseci_dest dest_type;
25746+ int dest_id;
25747+ uint8_t priority;
25748+};
25749+
25750+/**
25751+ * DPSECI queue modification options
25752+ */
25753+
25754+/**
25755+ * Select to modify the user's context associated with the queue
25756+ */
25757+#define DPSECI_QUEUE_OPT_USER_CTX 0x00000001
25758+
25759+/**
25760+ * Select to modify the queue's destination
25761+ */
25762+#define DPSECI_QUEUE_OPT_DEST 0x00000002
25763+
25764+/**
25765+ * Select to modify the queue's order preservation
25766+ */
25767+#define DPSECI_QUEUE_OPT_ORDER_PRESERVATION 0x00000004
25768+
25769+/**
25770+ * struct dpseci_rx_queue_cfg - DPSECI RX queue configuration
25771+ * @options: Flags representing the suggested modifications to the queue;
25772+ * Use any combination of 'DPSECI_QUEUE_OPT_<X>' flags
25773+ * @order_preservation_en: order preservation configuration for the rx queue
25774+ * valid only if 'DPSECI_QUEUE_OPT_ORDER_PRESERVATION' is contained in 'options'
25775+ * @user_ctx: User context value provided in the frame descriptor of each
25776+ * dequeued frame;
25777+ * valid only if 'DPSECI_QUEUE_OPT_USER_CTX' is contained in 'options'
25778+ * @dest_cfg: Queue destination parameters;
25779+ * valid only if 'DPSECI_QUEUE_OPT_DEST' is contained in 'options'
25780+ */
25781+struct dpseci_rx_queue_cfg {
25782+ uint32_t options;
25783+ int order_preservation_en;
25784+ uint64_t user_ctx;
25785+ struct dpseci_dest_cfg dest_cfg;
25786+};
25787+
25788+/**
25789+ * dpseci_set_rx_queue() - Set Rx queue configuration
25790+ * @mc_io: Pointer to MC portal's I/O object
25791+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25792+ * @token: Token of DPSECI object
25793+ * @queue: Select the queue relative to number of
25794+ * priorities configured at DPSECI creation; use
25795+ * DPSECI_ALL_QUEUES to configure all Rx queues identically.
25796+ * @cfg: Rx queue configuration
25797+ *
25798+ * Return: '0' on Success; Error code otherwise.
25799+ */
25800+int dpseci_set_rx_queue(struct fsl_mc_io *mc_io,
25801+ uint32_t cmd_flags,
25802+ uint16_t token,
25803+ uint8_t queue,
25804+ const struct dpseci_rx_queue_cfg *cfg);
25805+
25806+/**
25807+ * struct dpseci_rx_queue_attr - Structure representing attributes of Rx queues
25808+ * @user_ctx: User context value provided in the frame descriptor of each
25809+ * dequeued frame
25810+ * @order_preservation_en: Status of the order preservation configuration
25811+ * on the queue
25812+ * @dest_cfg: Queue destination configuration
25813+ * @fqid: Virtual FQID value to be used for dequeue operations
25814+ */
25815+struct dpseci_rx_queue_attr {
25816+ uint64_t user_ctx;
25817+ int order_preservation_en;
25818+ struct dpseci_dest_cfg dest_cfg;
25819+ uint32_t fqid;
25820+};
25821+
25822+/**
25823+ * dpseci_get_rx_queue() - Retrieve Rx queue attributes.
25824+ * @mc_io: Pointer to MC portal's I/O object
25825+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25826+ * @token: Token of DPSECI object
25827+ * @queue: Select the queue relative to number of
25828+ * priorities configured at DPSECI creation
25829+ * @attr: Returned Rx queue attributes
25830+ *
25831+ * Return: '0' on Success; Error code otherwise.
25832+ */
25833+int dpseci_get_rx_queue(struct fsl_mc_io *mc_io,
25834+ uint32_t cmd_flags,
25835+ uint16_t token,
25836+ uint8_t queue,
25837+ struct dpseci_rx_queue_attr *attr);
25838+
25839+/**
25840+ * struct dpseci_tx_queue_attr - Structure representing attributes of Tx queues
25841+ * @fqid: Virtual FQID to be used for sending frames to SEC hardware
25842+ * @priority: SEC hardware processing priority for the queue
25843+ */
25844+struct dpseci_tx_queue_attr {
25845+ uint32_t fqid;
25846+ uint8_t priority;
25847+};
25848+
25849+/**
25850+ * dpseci_get_tx_queue() - Retrieve Tx queue attributes.
25851+ * @mc_io: Pointer to MC portal's I/O object
25852+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25853+ * @token: Token of DPSECI object
25854+ * @queue: Select the queue relative to number of
25855+ * priorities configured at DPSECI creation
25856+ * @attr: Returned Tx queue attributes
25857+ *
25858+ * Return: '0' on Success; Error code otherwise.
25859+ */
25860+int dpseci_get_tx_queue(struct fsl_mc_io *mc_io,
25861+ uint32_t cmd_flags,
25862+ uint16_t token,
25863+ uint8_t queue,
25864+ struct dpseci_tx_queue_attr *attr);
25865+
25866+/**
25867+ * struct dpseci_sec_attr - Structure representing attributes of the SEC
25868+ * hardware accelerator
25869+ * @ip_id: ID for SEC.
25870+ * @major_rev: Major revision number for SEC.
25871+ * @minor_rev: Minor revision number for SEC.
25872+ * @era: SEC Era.
25873+ * @deco_num: The number of copies of the DECO that are implemented in
25874+ * this version of SEC.
25875+ * @zuc_auth_acc_num: The number of copies of ZUCA that are implemented
25876+ * in this version of SEC.
25877+ * @zuc_enc_acc_num: The number of copies of ZUCE that are implemented
25878+ * in this version of SEC.
25879+ * @snow_f8_acc_num: The number of copies of the SNOW-f8 module that are
25880+ * implemented in this version of SEC.
25881+ * @snow_f9_acc_num: The number of copies of the SNOW-f9 module that are
25882+ * implemented in this version of SEC.
25883+ * @crc_acc_num: The number of copies of the CRC module that are implemented
25884+ * in this version of SEC.
25885+ * @pk_acc_num: The number of copies of the Public Key module that are
25886+ * implemented in this version of SEC.
25887+ * @kasumi_acc_num: The number of copies of the Kasumi module that are
25888+ * implemented in this version of SEC.
25889+ * @rng_acc_num: The number of copies of the Random Number Generator that are
25890+ * implemented in this version of SEC.
25891+ * @md_acc_num: The number of copies of the MDHA (Hashing module) that are
25892+ * implemented in this version of SEC.
25893+ * @arc4_acc_num: The number of copies of the ARC4 module that are implemented
25894+ * in this version of SEC.
25895+ * @des_acc_num: The number of copies of the DES module that are implemented
25896+ * in this version of SEC.
25897+ * @aes_acc_num: The number of copies of the AES module that are implemented
25898+ * in this version of SEC.
25899+ **/
25900+
25901+struct dpseci_sec_attr {
25902+ uint16_t ip_id;
25903+ uint8_t major_rev;
25904+ uint8_t minor_rev;
25905+ uint8_t era;
25906+ uint8_t deco_num;
25907+ uint8_t zuc_auth_acc_num;
25908+ uint8_t zuc_enc_acc_num;
25909+ uint8_t snow_f8_acc_num;
25910+ uint8_t snow_f9_acc_num;
25911+ uint8_t crc_acc_num;
25912+ uint8_t pk_acc_num;
25913+ uint8_t kasumi_acc_num;
25914+ uint8_t rng_acc_num;
25915+ uint8_t md_acc_num;
25916+ uint8_t arc4_acc_num;
25917+ uint8_t des_acc_num;
25918+ uint8_t aes_acc_num;
25919+};
25920+
25921+/**
25922+ * dpseci_get_sec_attr() - Retrieve SEC accelerator attributes.
25923+ * @mc_io: Pointer to MC portal's I/O object
25924+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25925+ * @token: Token of DPSECI object
25926+ * @attr: Returned SEC attributes
25927+ *
25928+ * Return: '0' on Success; Error code otherwise.
25929+ */
25930+int dpseci_get_sec_attr(struct fsl_mc_io *mc_io,
25931+ uint32_t cmd_flags,
25932+ uint16_t token,
25933+ struct dpseci_sec_attr *attr);
25934+
25935+/**
25936+ * struct dpseci_sec_counters - Structure representing global SEC counters and
25937+ * not per dpseci counters
25938+ * @dequeued_requests: Number of Requests Dequeued
25939+ * @ob_enc_requests: Number of Outbound Encrypt Requests
25940+ * @ib_dec_requests: Number of Inbound Decrypt Requests
25941+ * @ob_enc_bytes: Number of Outbound Bytes Encrypted
25942+ * @ob_prot_bytes: Number of Outbound Bytes Protected
25943+ * @ib_dec_bytes: Number of Inbound Bytes Decrypted
25944+ * @ib_valid_bytes: Number of Inbound Bytes Validated
25945+ */
25946+struct dpseci_sec_counters {
25947+ uint64_t dequeued_requests;
25948+ uint64_t ob_enc_requests;
25949+ uint64_t ib_dec_requests;
25950+ uint64_t ob_enc_bytes;
25951+ uint64_t ob_prot_bytes;
25952+ uint64_t ib_dec_bytes;
25953+ uint64_t ib_valid_bytes;
25954+};
25955+
25956+/**
25957+ * dpseci_get_sec_counters() - Retrieve SEC accelerator counters.
25958+ * @mc_io: Pointer to MC portal's I/O object
25959+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
25960+ * @token: Token of DPSECI object
25961+ * @counters: Returned SEC counters
25962+ *
25963+ * Return: '0' on Success; Error code otherwise.
25964+ */
25965+int dpseci_get_sec_counters(struct fsl_mc_io *mc_io,
25966+ uint32_t cmd_flags,
25967+ uint16_t token,
25968+ struct dpseci_sec_counters *counters);
25969+
25970+#endif /* __FSL_DPSECI_H */
25971diff --git a/drivers/net/dpaa2/mc/fsl_dpseci_cmd.h b/drivers/net/dpaa2/mc/fsl_dpseci_cmd.h
25972new file mode 100644
25973index 0000000..6c0b96e
25974--- /dev/null
25975+++ b/drivers/net/dpaa2/mc/fsl_dpseci_cmd.h
25976@@ -0,0 +1,241 @@
25977+/* Copyright 2013-2015 Freescale Semiconductor Inc.
25978+ *
25979+ * Redistribution and use in source and binary forms, with or without
25980+ * modification, are permitted provided that the following conditions are met:
25981+ * * Redistributions of source code must retain the above copyright
25982+ * notice, this list of conditions and the following disclaimer.
25983+ * * Redistributions in binary form must reproduce the above copyright
25984+ * notice, this list of conditions and the following disclaimer in the
25985+ * documentation and/or other materials provided with the distribution.
25986+ * * Neither the name of the above-listed copyright holders nor the
25987+ * names of any contributors may be used to endorse or promote products
25988+ * derived from this software without specific prior written permission.
25989+ *
25990+ *
25991+ * ALTERNATIVELY, this software may be distributed under the terms of the
25992+ * GNU General Public License ("GPL") as published by the Free Software
25993+ * Foundation, either version 2 of that License or (at your option) any
25994+ * later version.
25995+ *
25996+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25997+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25998+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25999+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
26000+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26001+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26002+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26003+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26004+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26005+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26006+ * POSSIBILITY OF SUCH DAMAGE.
26007+ */
26008+#ifndef _FSL_DPSECI_CMD_H
26009+#define _FSL_DPSECI_CMD_H
26010+
26011+/* DPSECI Version */
26012+#define DPSECI_VER_MAJOR 3
26013+#define DPSECI_VER_MINOR 1
26014+
26015+/* Command IDs */
26016+#define DPSECI_CMDID_CLOSE 0x800
26017+#define DPSECI_CMDID_OPEN 0x809
26018+#define DPSECI_CMDID_CREATE 0x909
26019+#define DPSECI_CMDID_DESTROY 0x900
26020+
26021+#define DPSECI_CMDID_ENABLE 0x002
26022+#define DPSECI_CMDID_DISABLE 0x003
26023+#define DPSECI_CMDID_GET_ATTR 0x004
26024+#define DPSECI_CMDID_RESET 0x005
26025+#define DPSECI_CMDID_IS_ENABLED 0x006
26026+
26027+#define DPSECI_CMDID_SET_IRQ 0x010
26028+#define DPSECI_CMDID_GET_IRQ 0x011
26029+#define DPSECI_CMDID_SET_IRQ_ENABLE 0x012
26030+#define DPSECI_CMDID_GET_IRQ_ENABLE 0x013
26031+#define DPSECI_CMDID_SET_IRQ_MASK 0x014
26032+#define DPSECI_CMDID_GET_IRQ_MASK 0x015
26033+#define DPSECI_CMDID_GET_IRQ_STATUS 0x016
26034+#define DPSECI_CMDID_CLEAR_IRQ_STATUS 0x017
26035+
26036+#define DPSECI_CMDID_SET_RX_QUEUE 0x194
26037+#define DPSECI_CMDID_GET_RX_QUEUE 0x196
26038+#define DPSECI_CMDID_GET_TX_QUEUE 0x197
26039+#define DPSECI_CMDID_GET_SEC_ATTR 0x198
26040+#define DPSECI_CMDID_GET_SEC_COUNTERS 0x199
26041+
26042+/* cmd, param, offset, width, type, arg_name */
26043+#define DPSECI_CMD_OPEN(cmd, dpseci_id) \
26044+ MC_CMD_OP(cmd, 0, 0, 32, int, dpseci_id)
26045+
26046+/* cmd, param, offset, width, type, arg_name */
26047+#define DPSECI_CMD_CREATE(cmd, cfg) \
26048+do { \
26049+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->priorities[0]);\
26050+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->priorities[1]);\
26051+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->priorities[2]);\
26052+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->priorities[3]);\
26053+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->priorities[4]);\
26054+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->priorities[5]);\
26055+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->priorities[6]);\
26056+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->priorities[7]);\
26057+ MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->num_tx_queues);\
26058+ MC_CMD_OP(cmd, 1, 8, 8, uint8_t, cfg->num_rx_queues);\
26059+} while (0)
26060+
26061+/* cmd, param, offset, width, type, arg_name */
26062+#define DPSECI_RSP_IS_ENABLED(cmd, en) \
26063+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
26064+
26065+/* cmd, param, offset, width, type, arg_name */
26066+#define DPSECI_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
26067+do { \
26068+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
26069+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
26070+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
26071+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
26072+} while (0)
26073+
26074+/* cmd, param, offset, width, type, arg_name */
26075+#define DPSECI_CMD_GET_IRQ(cmd, irq_index) \
26076+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
26077+
26078+/* cmd, param, offset, width, type, arg_name */
26079+#define DPSECI_RSP_GET_IRQ(cmd, type, irq_cfg) \
26080+do { \
26081+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
26082+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
26083+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
26084+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
26085+} while (0)
26086+
26087+/* cmd, param, offset, width, type, arg_name */
26088+#define DPSECI_CMD_SET_IRQ_ENABLE(cmd, irq_index, enable_state) \
26089+do { \
26090+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, enable_state); \
26091+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
26092+} while (0)
26093+
26094+/* cmd, param, offset, width, type, arg_name */
26095+#define DPSECI_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
26096+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
26097+
26098+/* cmd, param, offset, width, type, arg_name */
26099+#define DPSECI_RSP_GET_IRQ_ENABLE(cmd, enable_state) \
26100+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, enable_state)
26101+
26102+/* cmd, param, offset, width, type, arg_name */
26103+#define DPSECI_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
26104+do { \
26105+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
26106+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
26107+} while (0)
26108+
26109+/* cmd, param, offset, width, type, arg_name */
26110+#define DPSECI_CMD_GET_IRQ_MASK(cmd, irq_index) \
26111+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
26112+
26113+/* cmd, param, offset, width, type, arg_name */
26114+#define DPSECI_RSP_GET_IRQ_MASK(cmd, mask) \
26115+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
26116+
26117+/* cmd, param, offset, width, type, arg_name */
26118+#define DPSECI_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
26119+do { \
26120+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
26121+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
26122+} while (0)
26123+
26124+/* cmd, param, offset, width, type, arg_name */
26125+#define DPSECI_RSP_GET_IRQ_STATUS(cmd, status) \
26126+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
26127+
26128+/* cmd, param, offset, width, type, arg_name */
26129+#define DPSECI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
26130+do { \
26131+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
26132+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
26133+} while (0)
26134+
26135+/* cmd, param, offset, width, type, arg_name */
26136+#define DPSECI_RSP_GET_ATTR(cmd, attr) \
26137+do { \
26138+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id); \
26139+ MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->num_tx_queues); \
26140+ MC_RSP_OP(cmd, 1, 8, 8, uint8_t, attr->num_rx_queues); \
26141+ MC_RSP_OP(cmd, 5, 0, 16, uint16_t, attr->version.major);\
26142+ MC_RSP_OP(cmd, 5, 16, 16, uint16_t, attr->version.minor);\
26143+} while (0)
26144+
26145+/* cmd, param, offset, width, type, arg_name */
26146+#define DPSECI_CMD_SET_RX_QUEUE(cmd, queue, cfg) \
26147+do { \
26148+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \
26149+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority); \
26150+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, queue); \
26151+ MC_CMD_OP(cmd, 0, 48, 4, enum dpseci_dest, cfg->dest_cfg.dest_type); \
26152+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \
26153+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
26154+ MC_CMD_OP(cmd, 2, 32, 1, int, cfg->order_preservation_en);\
26155+} while (0)
26156+
26157+/* cmd, param, offset, width, type, arg_name */
26158+#define DPSECI_CMD_GET_RX_QUEUE(cmd, queue) \
26159+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, queue)
26160+
26161+/* cmd, param, offset, width, type, arg_name */
26162+#define DPSECI_RSP_GET_RX_QUEUE(cmd, attr) \
26163+do { \
26164+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id);\
26165+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
26166+ MC_RSP_OP(cmd, 0, 48, 4, enum dpseci_dest, attr->dest_cfg.dest_type);\
26167+ MC_RSP_OP(cmd, 1, 0, 8, uint64_t, attr->user_ctx);\
26168+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->fqid);\
26169+ MC_RSP_OP(cmd, 2, 32, 1, int, attr->order_preservation_en);\
26170+} while (0)
26171+
26172+/* cmd, param, offset, width, type, arg_name */
26173+#define DPSECI_CMD_GET_TX_QUEUE(cmd, queue) \
26174+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, queue)
26175+
26176+/* cmd, param, offset, width, type, arg_name */
26177+#define DPSECI_RSP_GET_TX_QUEUE(cmd, attr) \
26178+do { \
26179+ MC_RSP_OP(cmd, 0, 32, 32, uint32_t, attr->fqid);\
26180+ MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->priority);\
26181+} while (0)
26182+
26183+/* cmd, param, offset, width, type, arg_name */
26184+#define DPSECI_RSP_GET_SEC_ATTR(cmd, attr) \
26185+do { \
26186+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, attr->ip_id);\
26187+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, attr->major_rev);\
26188+ MC_RSP_OP(cmd, 0, 24, 8, uint8_t, attr->minor_rev);\
26189+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->era);\
26190+ MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->deco_num);\
26191+ MC_RSP_OP(cmd, 1, 8, 8, uint8_t, attr->zuc_auth_acc_num);\
26192+ MC_RSP_OP(cmd, 1, 16, 8, uint8_t, attr->zuc_enc_acc_num);\
26193+ MC_RSP_OP(cmd, 1, 32, 8, uint8_t, attr->snow_f8_acc_num);\
26194+ MC_RSP_OP(cmd, 1, 40, 8, uint8_t, attr->snow_f9_acc_num);\
26195+ MC_RSP_OP(cmd, 1, 48, 8, uint8_t, attr->crc_acc_num);\
26196+ MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->pk_acc_num);\
26197+ MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->kasumi_acc_num);\
26198+ MC_RSP_OP(cmd, 2, 16, 8, uint8_t, attr->rng_acc_num);\
26199+ MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->md_acc_num);\
26200+ MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->arc4_acc_num);\
26201+ MC_RSP_OP(cmd, 2, 48, 8, uint8_t, attr->des_acc_num);\
26202+ MC_RSP_OP(cmd, 2, 56, 8, uint8_t, attr->aes_acc_num);\
26203+} while (0)
26204+
26205+/* cmd, param, offset, width, type, arg_name */
26206+#define DPSECI_RSP_GET_SEC_COUNTERS(cmd, counters) \
26207+do { \
26208+ MC_RSP_OP(cmd, 0, 0, 64, uint64_t, counters->dequeued_requests);\
26209+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counters->ob_enc_requests);\
26210+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, counters->ib_dec_requests);\
26211+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, counters->ob_enc_bytes);\
26212+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, counters->ob_prot_bytes);\
26213+ MC_RSP_OP(cmd, 5, 0, 64, uint64_t, counters->ib_dec_bytes);\
26214+ MC_RSP_OP(cmd, 6, 0, 64, uint64_t, counters->ib_valid_bytes);\
26215+} while (0)
26216+
26217+#endif /* _FSL_DPSECI_CMD_H */
26218diff --git a/drivers/net/dpaa2/mc/fsl_dpsw.h b/drivers/net/dpaa2/mc/fsl_dpsw.h
26219new file mode 100644
26220index 0000000..9c1bd9d
26221--- /dev/null
26222+++ b/drivers/net/dpaa2/mc/fsl_dpsw.h
26223@@ -0,0 +1,2164 @@
26224+/* Copyright 2013-2015 Freescale Semiconductor Inc.
26225+ *
26226+ * Redistribution and use in source and binary forms, with or without
26227+ * modification, are permitted provided that the following conditions are met:
26228+ * * Redistributions of source code must retain the above copyright
26229+ * notice, this list of conditions and the following disclaimer.
26230+ * * Redistributions in binary form must reproduce the above copyright
26231+ * notice, this list of conditions and the following disclaimer in the
26232+ * documentation and/or other materials provided with the distribution.
26233+ * * Neither the name of the above-listed copyright holders nor the
26234+ * names of any contributors may be used to endorse or promote products
26235+ * derived from this software without specific prior written permission.
26236+ *
26237+ *
26238+ * ALTERNATIVELY, this software may be distributed under the terms of the
26239+ * GNU General Public License ("GPL") as published by the Free Software
26240+ * Foundation, either version 2 of that License or (at your option) any
26241+ * later version.
26242+ *
26243+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26244+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26245+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26246+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
26247+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26248+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26249+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26250+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26251+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26252+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26253+ * POSSIBILITY OF SUCH DAMAGE.
26254+ */
26255+#ifndef __FSL_DPSW_H
26256+#define __FSL_DPSW_H
26257+
26258+#include <fsl_net.h>
26259+
26260+/* Data Path L2-Switch API
26261+ * Contains API for handling DPSW topology and functionality
26262+ */
26263+
26264+struct fsl_mc_io;
26265+
26266+/**
26267+ * DPSW general definitions
26268+ */
26269+
26270+/**
26271+ * Maximum number of traffic class priorities
26272+ */
26273+#define DPSW_MAX_PRIORITIES 8
26274+/**
26275+ * Maximum number of interfaces
26276+ */
26277+#define DPSW_MAX_IF 64
26278+
26279+/**
26280+ * dpsw_open() - Open a control session for the specified object
26281+ * @mc_io: Pointer to MC portal's I/O object
26282+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26283+ * @dpsw_id: DPSW unique ID
26284+ * @token: Returned token; use in subsequent API calls
26285+ *
26286+ * This function can be used to open a control session for an
26287+ * already created object; an object may have been declared in
26288+ * the DPL or by calling the dpsw_create() function.
26289+ * This function returns a unique authentication token,
26290+ * associated with the specific object ID and the specific MC
26291+ * portal; this token must be used in all subsequent commands for
26292+ * this specific object
26293+ *
26294+ * Return: '0' on Success; Error code otherwise.
26295+ */
26296+int dpsw_open(struct fsl_mc_io *mc_io,
26297+ uint32_t cmd_flags,
26298+ int dpsw_id,
26299+ uint16_t *token);
26300+
26301+/**
26302+ * dpsw_close() - Close the control session of the object
26303+ * @mc_io: Pointer to MC portal's I/O object
26304+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26305+ * @token: Token of DPSW object
26306+ *
26307+ * After this function is called, no further operations are
26308+ * allowed on the object without opening a new control session.
26309+ *
26310+ * Return: '0' on Success; Error code otherwise.
26311+ */
26312+int dpsw_close(struct fsl_mc_io *mc_io,
26313+ uint32_t cmd_flags,
26314+ uint16_t token);
26315+
26316+/**
26317+ * DPSW options
26318+ */
26319+
26320+/**
26321+ * Disable flooding
26322+ */
26323+#define DPSW_OPT_FLOODING_DIS 0x0000000000000001ULL
26324+/**
26325+ * Disable Multicast
26326+ */
26327+#define DPSW_OPT_MULTICAST_DIS 0x0000000000000004ULL
26328+/**
26329+ * Support control interface
26330+ */
26331+#define DPSW_OPT_CTRL_IF_DIS 0x0000000000000010ULL
26332+/**
26333+ * Disable flooding metering
26334+ */
26335+#define DPSW_OPT_FLOODING_METERING_DIS 0x0000000000000020ULL
26336+/**
26337+ * Enable metering
26338+ */
26339+#define DPSW_OPT_METERING_EN 0x0000000000000040ULL
26340+
26341+/**
26342+ * enum dpsw_component_type - component type of a bridge
26343+ * @DPSW_COMPONENT_TYPE_C_VLAN: A C-VLAN component of an
26344+ * enterprise VLAN bridge or of a Provider Bridge used
26345+ * to process C-tagged frames
26346+ * @DPSW_COMPONENT_TYPE_S_VLAN: An S-VLAN component of a
26347+ * Provider Bridge
26348+ *
26349+ */
26350+enum dpsw_component_type {
26351+ DPSW_COMPONENT_TYPE_C_VLAN = 0,
26352+ DPSW_COMPONENT_TYPE_S_VLAN
26353+};
26354+
26355+/**
26356+ * struct dpsw_cfg - DPSW configuration
26357+ * @num_ifs: Number of external and internal interfaces
26358+ * @adv: Advanced parameters; default is all zeros;
26359+ * use this structure to change default settings
26360+ */
26361+struct dpsw_cfg {
26362+ uint16_t num_ifs;
26363+ /**
26364+ * struct adv - Advanced parameters
26365+ * @options: Enable/Disable DPSW features (bitmap)
26366+ * @max_vlans: Maximum Number of VLAN's; 0 - indicates default 16
26367+ * @max_meters_per_if: Number of meters per interface
26368+ * @max_fdbs: Maximum Number of FDB's; 0 - indicates default 16
26369+ * @max_fdb_entries: Number of FDB entries for default FDB table;
26370+ * 0 - indicates default 1024 entries.
26371+ * @fdb_aging_time: Default FDB aging time for default FDB table;
26372+ * 0 - indicates default 300 seconds
26373+ * @max_fdb_mc_groups: Number of multicast groups in each FDB table;
26374+ * 0 - indicates default 32
26375+ * @component_type: Indicates the component type of this bridge
26376+ */
26377+ struct {
26378+ uint64_t options;
26379+ uint16_t max_vlans;
26380+ uint8_t max_meters_per_if;
26381+ uint8_t max_fdbs;
26382+ uint16_t max_fdb_entries;
26383+ uint16_t fdb_aging_time;
26384+ uint16_t max_fdb_mc_groups;
26385+ enum dpsw_component_type component_type;
26386+ } adv;
26387+};
26388+
26389+/**
26390+ * dpsw_create() - Create the DPSW object.
26391+ * @mc_io: Pointer to MC portal's I/O object
26392+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26393+ * @cfg: Configuration structure
26394+ * @token: Returned token; use in subsequent API calls
26395+ *
26396+ * Create the DPSW object, allocate required resources and
26397+ * perform required initialization.
26398+ *
26399+ * The object can be created either by declaring it in the
26400+ * DPL file, or by calling this function.
26401+ *
26402+ * This function returns a unique authentication token,
26403+ * associated with the specific object ID and the specific MC
26404+ * portal; this token must be used in all subsequent calls to
26405+ * this specific object. For objects that are created using the
26406+ * DPL file, call dpsw_open() function to get an authentication
26407+ * token first
26408+ *
26409+ * Return: '0' on Success; Error code otherwise.
26410+ */
26411+int dpsw_create(struct fsl_mc_io *mc_io,
26412+ uint32_t cmd_flags,
26413+ const struct dpsw_cfg *cfg,
26414+ uint16_t *token);
26415+
26416+/**
26417+ * dpsw_destroy() - Destroy the DPSW object and release all its resources.
26418+ * @mc_io: Pointer to MC portal's I/O object
26419+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26420+ * @token: Token of DPSW object
26421+ *
26422+ * Return: '0' on Success; error code otherwise.
26423+ */
26424+int dpsw_destroy(struct fsl_mc_io *mc_io,
26425+ uint32_t cmd_flags,
26426+ uint16_t token);
26427+
26428+/**
26429+ * dpsw_enable() - Enable DPSW functionality
26430+ * @mc_io: Pointer to MC portal's I/O object
26431+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26432+ * @token: Token of DPSW object
26433+ *
26434+ * Return: Completion status. '0' on Success; Error code otherwise.
26435+ */
26436+int dpsw_enable(struct fsl_mc_io *mc_io,
26437+ uint32_t cmd_flags,
26438+ uint16_t token);
26439+
26440+/**
26441+ * dpsw_disable() - Disable DPSW functionality
26442+ * @mc_io: Pointer to MC portal's I/O object
26443+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26444+ * @token: Token of DPSW object
26445+ *
26446+ * Return: Completion status. '0' on Success; Error code otherwise.
26447+ */
26448+int dpsw_disable(struct fsl_mc_io *mc_io,
26449+ uint32_t cmd_flags,
26450+ uint16_t token);
26451+
26452+/**
26453+ * dpsw_is_enabled() - Check if the DPSW is enabled
26454+ *
26455+ * @mc_io: Pointer to MC portal's I/O object
26456+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26457+ * @token: Token of DPSW object
26458+ * @en: Returns '1' if object is enabled; '0' otherwise
26459+ *
26460+ * Return: '0' on Success; Error code otherwise
26461+ */
26462+int dpsw_is_enabled(struct fsl_mc_io *mc_io,
26463+ uint32_t cmd_flags,
26464+ uint16_t token,
26465+ int *en);
26466+
26467+/**
26468+ * dpsw_reset() - Reset the DPSW, returns the object to initial state.
26469+ * @mc_io: Pointer to MC portal's I/O object
26470+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26471+ * @token: Token of DPSW object
26472+ *
26473+ * Return: '0' on Success; Error code otherwise.
26474+ */
26475+int dpsw_reset(struct fsl_mc_io *mc_io,
26476+ uint32_t cmd_flags,
26477+ uint16_t token);
26478+
26479+/**
26480+ * DPSW IRQ Index and Events
26481+ */
26482+
26483+#define DPSW_IRQ_INDEX_IF 0x0000
26484+#define DPSW_IRQ_INDEX_L2SW 0x0001
26485+
26486+/**
26487+ * IRQ event - Indicates that the link state changed
26488+ */
26489+#define DPSW_IRQ_EVENT_LINK_CHANGED 0x0001
26490+
26491+/**
26492+ * struct dpsw_irq_cfg - IRQ configuration
26493+ * @addr: Address that must be written to signal a message-based interrupt
26494+ * @val: Value to write into irq_addr address
26495+ * @irq_num: A user defined number associated with this IRQ
26496+ */
26497+struct dpsw_irq_cfg {
26498+ uint64_t addr;
26499+ uint32_t val;
26500+ int irq_num;
26501+};
26502+
26503+/**
26504+ * dpsw_set_irq() - Set IRQ information for the DPSW to trigger an interrupt.
26505+ * @mc_io: Pointer to MC portal's I/O object
26506+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26507+ * @token: Token of DPSW object
26508+ * @irq_index: Identifies the interrupt index to configure
26509+ * @irq_cfg: IRQ configuration
26510+ *
26511+ * Return: '0' on Success; Error code otherwise.
26512+ */
26513+int dpsw_set_irq(struct fsl_mc_io *mc_io,
26514+ uint32_t cmd_flags,
26515+ uint16_t token,
26516+ uint8_t irq_index,
26517+ struct dpsw_irq_cfg *irq_cfg);
26518+
26519+/**
26520+ * dpsw_get_irq() - Get IRQ information from the DPSW
26521+ *
26522+ * @mc_io: Pointer to MC portal's I/O object
26523+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26524+ * @token: Token of DPSW object
26525+ * @irq_index: The interrupt index to configure
26526+ * @type: Interrupt type: 0 represents message interrupt
26527+ * type (both irq_addr and irq_val are valid)
26528+ * @irq_cfg: IRQ attributes
26529+ *
26530+ * Return: '0' on Success; Error code otherwise.
26531+ */
26532+int dpsw_get_irq(struct fsl_mc_io *mc_io,
26533+ uint32_t cmd_flags,
26534+ uint16_t token,
26535+ uint8_t irq_index,
26536+ int *type,
26537+ struct dpsw_irq_cfg *irq_cfg);
26538+
26539+/**
26540+ * dpsw_set_irq_enable() - Set overall interrupt state.
26541+ * @mc_io: Pointer to MC portal's I/O object
26542+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26543+ * @token: Token of DPCI object
26544+ * @irq_index: The interrupt index to configure
26545+ * @en: Interrupt state - enable = 1, disable = 0
26546+ *
26547+ * Allows GPP software to control when interrupts are generated.
26548+ * Each interrupt can have up to 32 causes. The enable/disable control's the
26549+ * overall interrupt state. if the interrupt is disabled no causes will cause
26550+ * an interrupt
26551+ *
26552+ * Return: '0' on Success; Error code otherwise.
26553+ */
26554+int dpsw_set_irq_enable(struct fsl_mc_io *mc_io,
26555+ uint32_t cmd_flags,
26556+ uint16_t token,
26557+ uint8_t irq_index,
26558+ uint8_t en);
26559+
26560+/**
26561+ * dpsw_get_irq_enable() - Get overall interrupt state
26562+ * @mc_io: Pointer to MC portal's I/O object
26563+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26564+ * @token: Token of DPSW object
26565+ * @irq_index: The interrupt index to configure
26566+ * @en: Returned Interrupt state - enable = 1, disable = 0
26567+ *
26568+ * Return: '0' on Success; Error code otherwise.
26569+ */
26570+int dpsw_get_irq_enable(struct fsl_mc_io *mc_io,
26571+ uint32_t cmd_flags,
26572+ uint16_t token,
26573+ uint8_t irq_index,
26574+ uint8_t *en);
26575+
26576+/**
26577+ * dpsw_set_irq_mask() - Set interrupt mask.
26578+ * @mc_io: Pointer to MC portal's I/O object
26579+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26580+ * @token: Token of DPCI object
26581+ * @irq_index: The interrupt index to configure
26582+ * @mask: event mask to trigger interrupt;
26583+ * each bit:
26584+ * 0 = ignore event
26585+ * 1 = consider event for asserting IRQ
26586+ *
26587+ * Every interrupt can have up to 32 causes and the interrupt model supports
26588+ * masking/unmasking each cause independently
26589+ *
26590+ * Return: '0' on Success; Error code otherwise.
26591+ */
26592+int dpsw_set_irq_mask(struct fsl_mc_io *mc_io,
26593+ uint32_t cmd_flags,
26594+ uint16_t token,
26595+ uint8_t irq_index,
26596+ uint32_t mask);
26597+
26598+/**
26599+ * dpsw_get_irq_mask() - Get interrupt mask.
26600+ * @mc_io: Pointer to MC portal's I/O object
26601+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26602+ * @token: Token of DPSW object
26603+ * @irq_index: The interrupt index to configure
26604+ * @mask: Returned event mask to trigger interrupt
26605+ *
26606+ * Every interrupt can have up to 32 causes and the interrupt model supports
26607+ * masking/unmasking each cause independently
26608+ *
26609+ * Return: '0' on Success; Error code otherwise.
26610+ */
26611+int dpsw_get_irq_mask(struct fsl_mc_io *mc_io,
26612+ uint32_t cmd_flags,
26613+ uint16_t token,
26614+ uint8_t irq_index,
26615+ uint32_t *mask);
26616+
26617+/**
26618+ * dpsw_get_irq_status() - Get the current status of any pending interrupts
26619+ * @mc_io: Pointer to MC portal's I/O object
26620+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26621+ * @token: Token of DPSW object
26622+ * @irq_index: The interrupt index to configure
26623+ * @status: Returned interrupts status - one bit per cause:
26624+ * 0 = no interrupt pending
26625+ * 1 = interrupt pending
26626+ *
26627+ * Return: '0' on Success; Error code otherwise.
26628+ */
26629+int dpsw_get_irq_status(struct fsl_mc_io *mc_io,
26630+ uint32_t cmd_flags,
26631+ uint16_t token,
26632+ uint8_t irq_index,
26633+ uint32_t *status);
26634+
26635+/**
26636+ * dpsw_clear_irq_status() - Clear a pending interrupt's status
26637+ * @mc_io: Pointer to MC portal's I/O object
26638+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26639+ * @token: Token of DPCI object
26640+ * @irq_index: The interrupt index to configure
26641+ * @status: bits to clear (W1C) - one bit per cause:
26642+ * 0 = don't change
26643+ * 1 = clear status bit
26644+ *
26645+ * Return: '0' on Success; Error code otherwise.
26646+ */
26647+int dpsw_clear_irq_status(struct fsl_mc_io *mc_io,
26648+ uint32_t cmd_flags,
26649+ uint16_t token,
26650+ uint8_t irq_index,
26651+ uint32_t status);
26652+/**
26653+ * struct dpsw_attr - Structure representing DPSW attributes
26654+ * @id: DPSW object ID
26655+ * @version: DPSW version
26656+ * @options: Enable/Disable DPSW features
26657+ * @max_vlans: Maximum Number of VLANs
26658+ * @max_meters_per_if: Number of meters per interface
26659+ * @max_fdbs: Maximum Number of FDBs
26660+ * @max_fdb_entries: Number of FDB entries for default FDB table;
26661+ * 0 - indicates default 1024 entries.
26662+ * @fdb_aging_time: Default FDB aging time for default FDB table;
26663+ * 0 - indicates default 300 seconds
26664+ * @max_fdb_mc_groups: Number of multicast groups in each FDB table;
26665+ * 0 - indicates default 32
26666+ * @mem_size: DPSW frame storage memory size
26667+ * @num_ifs: Number of interfaces
26668+ * @num_vlans: Current number of VLANs
26669+ * @num_fdbs: Current number of FDBs
26670+ * @component_type: Component type of this bridge
26671+ */
26672+struct dpsw_attr {
26673+ int id;
26674+ /**
26675+ * struct version - DPSW version
26676+ * @major: DPSW major version
26677+ * @minor: DPSW minor version
26678+ */
26679+ struct {
26680+ uint16_t major;
26681+ uint16_t minor;
26682+ } version;
26683+ uint64_t options;
26684+ uint16_t max_vlans;
26685+ uint8_t max_meters_per_if;
26686+ uint8_t max_fdbs;
26687+ uint16_t max_fdb_entries;
26688+ uint16_t fdb_aging_time;
26689+ uint16_t max_fdb_mc_groups;
26690+ uint16_t num_ifs;
26691+ uint16_t mem_size;
26692+ uint16_t num_vlans;
26693+ uint8_t num_fdbs;
26694+ enum dpsw_component_type component_type;
26695+};
26696+
26697+/**
26698+ * dpsw_get_attributes() - Retrieve DPSW attributes
26699+ * @mc_io: Pointer to MC portal's I/O object
26700+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26701+ * @token: Token of DPSW object
26702+ * @attr: Returned DPSW attributes
26703+ *
26704+ * Return: Completion status. '0' on Success; Error code otherwise.
26705+ */
26706+int dpsw_get_attributes(struct fsl_mc_io *mc_io,
26707+ uint32_t cmd_flags,
26708+ uint16_t token,
26709+ struct dpsw_attr *attr);
26710+
26711+/**
26712+ * dpsw_set_reflection_if() - Set target interface for reflected interfaces.
26713+ * @mc_io: Pointer to MC portal's I/O object
26714+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26715+ * @token: Token of DPSW object
26716+ * @if_id: Interface Id
26717+ *
26718+ * Only one reflection receive interface is allowed per switch
26719+ *
26720+ * Return: Completion status. '0' on Success; Error code otherwise.
26721+ */
26722+int dpsw_set_reflection_if(struct fsl_mc_io *mc_io,
26723+ uint32_t cmd_flags,
26724+ uint16_t token,
26725+ uint16_t if_id);
26726+
26727+/**
26728+ * enum dpsw_action - Action selection for special/control frames
26729+ * @DPSW_ACTION_DROP: Drop frame
26730+ * @DPSW_ACTION_REDIRECT: Redirect frame to control port
26731+ */
26732+enum dpsw_action {
26733+ DPSW_ACTION_DROP = 0,
26734+ DPSW_ACTION_REDIRECT = 1
26735+};
26736+
26737+/**
26738+ * Enable auto-negotiation
26739+ */
26740+#define DPSW_LINK_OPT_AUTONEG 0x0000000000000001ULL
26741+/**
26742+ * Enable half-duplex mode
26743+ */
26744+#define DPSW_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL
26745+/**
26746+ * Enable pause frames
26747+ */
26748+#define DPSW_LINK_OPT_PAUSE 0x0000000000000004ULL
26749+/**
26750+ * Enable a-symmetric pause frames
26751+ */
26752+#define DPSW_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL
26753+
26754+/**
26755+ * struct dpsw_link_cfg - Structure representing DPSW link configuration
26756+ * @rate: Rate
26757+ * @options: Mask of available options; use 'DPSW_LINK_OPT_<X>' values
26758+ */
26759+struct dpsw_link_cfg {
26760+ uint32_t rate;
26761+ uint64_t options;
26762+};
26763+
26764+/**
26765+ * dpsw_if_set_link_cfg() - set the link configuration.
26766+ * @mc_io: Pointer to MC portal's I/O object
26767+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26768+ * @token: Token of DPSW object
26769+ * @if_id: interface id
26770+ * @cfg: Link configuration
26771+ *
26772+ * Return: '0' on Success; Error code otherwise.
26773+ */
26774+int dpsw_if_set_link_cfg(struct fsl_mc_io *mc_io,
26775+ uint32_t cmd_flags,
26776+ uint16_t token,
26777+ uint16_t if_id,
26778+ struct dpsw_link_cfg *cfg);
26779+/**
26780+ * struct dpsw_link_state - Structure representing DPSW link state
26781+ * @rate: Rate
26782+ * @options: Mask of available options; use 'DPSW_LINK_OPT_<X>' values
26783+ * @up: 0 - covers two cases: down and disconnected, 1 - up
26784+ */
26785+struct dpsw_link_state {
26786+ uint32_t rate;
26787+ uint64_t options;
26788+ int up;
26789+};
26790+
26791+/**
26792+ * dpsw_if_get_link_state - Return the link state
26793+ * @mc_io: Pointer to MC portal's I/O object
26794+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26795+ * @token: Token of DPSW object
26796+ * @if_id: interface id
26797+ * @state: link state 1 - linkup, 0 - link down or disconnected
26798+ *
26799+ * @returns '0' on Success; Error code otherwise.
26800+ */
26801+int dpsw_if_get_link_state(struct fsl_mc_io *mc_io,
26802+ uint32_t cmd_flags,
26803+ uint16_t token,
26804+ uint16_t if_id,
26805+ struct dpsw_link_state *state);
26806+
26807+/**
26808+ * dpsw_if_set_flooding() - Enable Disable flooding for particular interface
26809+ * @mc_io: Pointer to MC portal's I/O object
26810+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26811+ * @token: Token of DPSW object
26812+ * @if_id: Interface Identifier
26813+ * @en: 1 - enable, 0 - disable
26814+ *
26815+ * Return: Completion status. '0' on Success; Error code otherwise.
26816+ */
26817+int dpsw_if_set_flooding(struct fsl_mc_io *mc_io,
26818+ uint32_t cmd_flags,
26819+ uint16_t token,
26820+ uint16_t if_id,
26821+ int en);
26822+
26823+/**
26824+ * dpsw_if_set_broadcast() - Enable/disable broadcast for particular interface
26825+ * @mc_io: Pointer to MC portal's I/O object
26826+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26827+ * @token: Token of DPSW object
26828+ * @if_id: Interface Identifier
26829+ * @en: 1 - enable, 0 - disable
26830+ *
26831+ * Return: Completion status. '0' on Success; Error code otherwise.
26832+ */
26833+int dpsw_if_set_broadcast(struct fsl_mc_io *mc_io,
26834+ uint32_t cmd_flags,
26835+ uint16_t token,
26836+ uint16_t if_id,
26837+ int en);
26838+
26839+/**
26840+ * dpsw_if_set_multicast() - Enable/disable multicast for particular interface
26841+ * @mc_io: Pointer to MC portal's I/O object
26842+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26843+ * @token: Token of DPSW object
26844+ * @if_id: Interface Identifier
26845+ * @en: 1 - enable, 0 - disable
26846+ *
26847+ * Return: Completion status. '0' on Success; Error code otherwise.
26848+ */
26849+int dpsw_if_set_multicast(struct fsl_mc_io *mc_io,
26850+ uint32_t cmd_flags,
26851+ uint16_t token,
26852+ uint16_t if_id,
26853+ int en);
26854+
26855+/**
26856+ * struct dpsw_tci_cfg - Tag Contorl Information (TCI) configuration
26857+ * @pcp: Priority Code Point (PCP): a 3-bit field which refers
26858+ * to the IEEE 802.1p priority
26859+ * @dei: Drop Eligible Indicator (DEI): a 1-bit field. May be used
26860+ * separately or in conjunction with PCP to indicate frames
26861+ * eligible to be dropped in the presence of congestion
26862+ * @vlan_id: VLAN Identifier (VID): a 12-bit field specifying the VLAN
26863+ * to which the frame belongs. The hexadecimal values
26864+ * of 0x000 and 0xFFF are reserved;
26865+ * all other values may be used as VLAN identifiers,
26866+ * allowing up to 4,094 VLANs
26867+ */
26868+struct dpsw_tci_cfg {
26869+ uint8_t pcp;
26870+ uint8_t dei;
26871+ uint16_t vlan_id;
26872+};
26873+
26874+/**
26875+ * dpsw_if_set_tci() - Set default VLAN Tag Control Information (TCI)
26876+ * @mc_io: Pointer to MC portal's I/O object
26877+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26878+ * @token: Token of DPSW object
26879+ * @if_id: Interface Identifier
26880+ * @cfg: Tag Control Information Configuration
26881+ *
26882+ * Return: Completion status. '0' on Success; Error code otherwise.
26883+ */
26884+int dpsw_if_set_tci(struct fsl_mc_io *mc_io,
26885+ uint32_t cmd_flags,
26886+ uint16_t token,
26887+ uint16_t if_id,
26888+ const struct dpsw_tci_cfg *cfg);
26889+
26890+/**
26891+ * dpsw_if_get_tci() - Get default VLAN Tag Control Information (TCI)
26892+ * @mc_io: Pointer to MC portal's I/O object
26893+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26894+ * @token: Token of DPSW object
26895+ * @if_id: Interface Identifier
26896+ * @cfg: Tag Control Information Configuration
26897+ *
26898+ * Return: Completion status. '0' on Success; Error code otherwise.
26899+ */
26900+int dpsw_if_get_tci(struct fsl_mc_io *mc_io,
26901+ uint32_t cmd_flags,
26902+ uint16_t token,
26903+ uint16_t if_id,
26904+ struct dpsw_tci_cfg *cfg);
26905+
26906+/**
26907+ * enum dpsw_stp_state - Spanning Tree Protocol (STP) states
26908+ * @DPSW_STP_STATE_BLOCKING: Blocking state
26909+ * @DPSW_STP_STATE_LISTENING: Listening state
26910+ * @DPSW_STP_STATE_LEARNING: Learning state
26911+ * @DPSW_STP_STATE_FORWARDING: Forwarding state
26912+ *
26913+ */
26914+enum dpsw_stp_state {
26915+ DPSW_STP_STATE_BLOCKING = 0,
26916+ DPSW_STP_STATE_LISTENING = 1,
26917+ DPSW_STP_STATE_LEARNING = 2,
26918+ DPSW_STP_STATE_FORWARDING = 3
26919+};
26920+
26921+/**
26922+ * struct dpsw_stp_cfg - Spanning Tree Protocol (STP) Configuration
26923+ * @vlan_id: VLAN ID STP state
26924+ * @state: STP state
26925+ */
26926+struct dpsw_stp_cfg {
26927+ uint16_t vlan_id;
26928+ enum dpsw_stp_state state;
26929+};
26930+
26931+/**
26932+ * dpsw_if_set_stp() - Function sets Spanning Tree Protocol (STP) state.
26933+ * @mc_io: Pointer to MC portal's I/O object
26934+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26935+ * @token: Token of DPSW object
26936+ * @if_id: Interface Identifier
26937+ * @cfg: STP State configuration parameters
26938+ *
26939+ * The following STP states are supported -
26940+ * blocking, listening, learning, forwarding and disabled.
26941+ *
26942+ * Return: Completion status. '0' on Success; Error code otherwise.
26943+ */
26944+int dpsw_if_set_stp(struct fsl_mc_io *mc_io,
26945+ uint32_t cmd_flags,
26946+ uint16_t token,
26947+ uint16_t if_id,
26948+ const struct dpsw_stp_cfg *cfg);
26949+
26950+/**
26951+ * enum dpsw_accepted_frames - Types of frames to accept
26952+ * @DPSW_ADMIT_ALL: The device accepts VLAN tagged, untagged and
26953+ * priority tagged frames
26954+ * @DPSW_ADMIT_ONLY_VLAN_TAGGED: The device discards untagged frames or
26955+ * Priority-Tagged frames received on this interface.
26956+ *
26957+ */
26958+enum dpsw_accepted_frames {
26959+ DPSW_ADMIT_ALL = 1,
26960+ DPSW_ADMIT_ONLY_VLAN_TAGGED = 3
26961+};
26962+
26963+/**
26964+ * struct dpsw_accepted_frames_cfg - Types of frames to accept configuration
26965+ * @type: Defines ingress accepted frames
26966+ * @unaccept_act: When a frame is not accepted, it may be discarded or
26967+ * redirected to control interface depending on this mode
26968+ */
26969+struct dpsw_accepted_frames_cfg {
26970+ enum dpsw_accepted_frames type;
26971+ enum dpsw_action unaccept_act;
26972+};
26973+
26974+/**
26975+ * dpsw_if_set_accepted_frames()
26976+ * @mc_io: Pointer to MC portal's I/O object
26977+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
26978+ * @token: Token of DPSW object
26979+ * @if_id: Interface Identifier
26980+ * @cfg: Frame types configuration
26981+ *
26982+ * When is admit_only_vlan_tagged- the device will discard untagged
26983+ * frames or Priority-Tagged frames received on this interface.
26984+ * When admit_only_untagged- untagged frames or Priority-Tagged
26985+ * frames received on this interface will be accepted and assigned
26986+ * to a VID based on the PVID and VID Set for this interface.
26987+ * When admit_all - the device will accept VLAN tagged, untagged
26988+ * and priority tagged frames.
26989+ * The default is admit_all
26990+ *
26991+ * Return: Completion status. '0' on Success; Error code otherwise.
26992+ */
26993+int dpsw_if_set_accepted_frames(struct fsl_mc_io *mc_io,
26994+ uint32_t cmd_flags,
26995+ uint16_t token,
26996+ uint16_t if_id,
26997+ const struct dpsw_accepted_frames_cfg *cfg);
26998+
26999+/**
27000+ * dpsw_if_set_accept_all_vlan()
27001+ * @mc_io: Pointer to MC portal's I/O object
27002+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27003+ * @token: Token of DPSW object
27004+ * @if_id: Interface Identifier
27005+ * @accept_all: Accept or drop frames having different VLAN
27006+ *
27007+ * When this is accept (FALSE), the device will discard incoming
27008+ * frames for VLANs that do not include this interface in its
27009+ * Member set. When accept (TRUE), the interface will accept all incoming frames
27010+ *
27011+ * Return: Completion status. '0' on Success; Error code otherwise.
27012+ */
27013+int dpsw_if_set_accept_all_vlan(struct fsl_mc_io *mc_io,
27014+ uint32_t cmd_flags,
27015+ uint16_t token,
27016+ uint16_t if_id,
27017+ int accept_all);
27018+
27019+/**
27020+ * enum dpsw_counter - Counters types
27021+ * @DPSW_CNT_ING_FRAME: Counts ingress frames
27022+ * @DPSW_CNT_ING_BYTE: Counts ingress bytes
27023+ * @DPSW_CNT_ING_FLTR_FRAME: Counts filtered ingress frames
27024+ * @DPSW_CNT_ING_FRAME_DISCARD: Counts discarded ingress frame
27025+ * @DPSW_CNT_ING_MCAST_FRAME: Counts ingress multicast frames
27026+ * @DPSW_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes
27027+ * @DPSW_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames
27028+ * @DPSW_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes
27029+ * @DPSW_CNT_EGR_FRAME: Counts egress frames
27030+ * @DPSW_CNT_EGR_BYTE: Counts eEgress bytes
27031+ * @DPSW_CNT_EGR_FRAME_DISCARD: Counts discarded egress frames
27032+ * @DPSW_CNT_EGR_STP_FRAME_DISCARD: Counts egress STP discarded frames
27033+ */
27034+enum dpsw_counter {
27035+ DPSW_CNT_ING_FRAME = 0x0,
27036+ DPSW_CNT_ING_BYTE = 0x1,
27037+ DPSW_CNT_ING_FLTR_FRAME = 0x2,
27038+ DPSW_CNT_ING_FRAME_DISCARD = 0x3,
27039+ DPSW_CNT_ING_MCAST_FRAME = 0x4,
27040+ DPSW_CNT_ING_MCAST_BYTE = 0x5,
27041+ DPSW_CNT_ING_BCAST_FRAME = 0x6,
27042+ DPSW_CNT_ING_BCAST_BYTES = 0x7,
27043+ DPSW_CNT_EGR_FRAME = 0x8,
27044+ DPSW_CNT_EGR_BYTE = 0x9,
27045+ DPSW_CNT_EGR_FRAME_DISCARD = 0xa,
27046+ DPSW_CNT_EGR_STP_FRAME_DISCARD = 0xb
27047+};
27048+
27049+/**
27050+ * dpsw_if_get_counter() - Get specific counter of particular interface
27051+ * @mc_io: Pointer to MC portal's I/O object
27052+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27053+ * @token: Token of DPSW object
27054+ * @if_id: Interface Identifier
27055+ * @type: Counter type
27056+ * @counter: return value
27057+ *
27058+ * Return: Completion status. '0' on Success; Error code otherwise.
27059+ */
27060+int dpsw_if_get_counter(struct fsl_mc_io *mc_io,
27061+ uint32_t cmd_flags,
27062+ uint16_t token,
27063+ uint16_t if_id,
27064+ enum dpsw_counter type,
27065+ uint64_t *counter);
27066+
27067+/**
27068+ * dpsw_if_set_counter() - Set specific counter of particular interface
27069+ * @mc_io: Pointer to MC portal's I/O object
27070+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27071+ * @token: Token of DPSW object
27072+ * @if_id: Interface Identifier
27073+ * @type: Counter type
27074+ * @counter: New counter value
27075+ *
27076+ * Return: Completion status. '0' on Success; Error code otherwise.
27077+ */
27078+int dpsw_if_set_counter(struct fsl_mc_io *mc_io,
27079+ uint32_t cmd_flags,
27080+ uint16_t token,
27081+ uint16_t if_id,
27082+ enum dpsw_counter type,
27083+ uint64_t counter);
27084+
27085+/**
27086+ * Maximum number of TC
27087+ */
27088+#define DPSW_MAX_TC 8
27089+
27090+/**
27091+ * enum dpsw_priority_selector - User priority
27092+ * @DPSW_UP_PCP: Priority Code Point (PCP): a 3-bit field which
27093+ * refers to the IEEE 802.1p priority.
27094+ * @DPSW_UP_DSCP: Differentiated services Code Point (DSCP): 6 bit
27095+ * field from IP header
27096+ *
27097+ */
27098+enum dpsw_priority_selector {
27099+ DPSW_UP_PCP = 0,
27100+ DPSW_UP_DSCP = 1
27101+};
27102+
27103+/**
27104+ * enum dpsw_schedule_mode - Traffic classes scheduling
27105+ * @DPSW_SCHED_STRICT_PRIORITY: schedule strict priority
27106+ * @DPSW_SCHED_WEIGHTED: schedule based on token bucket created algorithm
27107+ */
27108+enum dpsw_schedule_mode {
27109+ DPSW_SCHED_STRICT_PRIORITY,
27110+ DPSW_SCHED_WEIGHTED
27111+};
27112+
27113+/**
27114+ * struct dpsw_tx_schedule_cfg - traffic class configuration
27115+ * @mode: Strict or weight-based scheduling
27116+ * @delta_bandwidth: weighted Bandwidth in range from 100 to 10000
27117+ */
27118+struct dpsw_tx_schedule_cfg {
27119+ enum dpsw_schedule_mode mode;
27120+ uint16_t delta_bandwidth;
27121+};
27122+
27123+/**
27124+ * struct dpsw_tx_selection_cfg - Mapping user priority into traffic
27125+ * class configuration
27126+ * @priority_selector: Source for user priority regeneration
27127+ * @tc_id: The Regenerated User priority that the incoming
27128+ * User Priority is mapped to for this interface
27129+ * @tc_sched: Traffic classes configuration
27130+ */
27131+struct dpsw_tx_selection_cfg {
27132+ enum dpsw_priority_selector priority_selector;
27133+ uint8_t tc_id[DPSW_MAX_PRIORITIES];
27134+ struct dpsw_tx_schedule_cfg tc_sched[DPSW_MAX_TC];
27135+};
27136+
27137+/**
27138+ * dpsw_if_set_tx_selection() - Function is used for mapping variety
27139+ * of frame fields
27140+ * @mc_io: Pointer to MC portal's I/O object
27141+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27142+ * @token: Token of DPSW object
27143+ * @if_id: Interface Identifier
27144+ * @cfg: Traffic class mapping configuration
27145+ *
27146+ * Function is used for mapping variety of frame fields (DSCP, PCP)
27147+ * to Traffic Class. Traffic class is a number
27148+ * in the range from 0 to 7
27149+ *
27150+ * Return: Completion status. '0' on Success; Error code otherwise.
27151+ */
27152+int dpsw_if_set_tx_selection(struct fsl_mc_io *mc_io,
27153+ uint32_t cmd_flags,
27154+ uint16_t token,
27155+ uint16_t if_id,
27156+ const struct dpsw_tx_selection_cfg *cfg);
27157+
27158+/**
27159+ * enum dpsw_reflection_filter - Filter type for frames to reflect
27160+ * @DPSW_REFLECTION_FILTER_INGRESS_ALL: Reflect all frames
27161+ * @DPSW_REFLECTION_FILTER_INGRESS_VLAN: Reflect only frames belong to
27162+ * particular VLAN defined by vid parameter
27163+ *
27164+ */
27165+enum dpsw_reflection_filter {
27166+ DPSW_REFLECTION_FILTER_INGRESS_ALL = 0,
27167+ DPSW_REFLECTION_FILTER_INGRESS_VLAN = 1
27168+};
27169+
27170+/**
27171+ * struct dpsw_reflection_cfg - Structure representing reflection information
27172+ * @filter: Filter type for frames to reflect
27173+ * @vlan_id: Vlan Id to reflect; valid only when filter type is
27174+ * DPSW_INGRESS_VLAN
27175+ */
27176+struct dpsw_reflection_cfg {
27177+ enum dpsw_reflection_filter filter;
27178+ uint16_t vlan_id;
27179+};
27180+
27181+/**
27182+ * dpsw_if_add_reflection() - Identify interface to be reflected or mirrored
27183+ * @mc_io: Pointer to MC portal's I/O object
27184+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27185+ * @token: Token of DPSW object
27186+ * @if_id: Interface Identifier
27187+ * @cfg: Reflection configuration
27188+ *
27189+ * Return: Completion status. '0' on Success; Error code otherwise.
27190+ */
27191+int dpsw_if_add_reflection(struct fsl_mc_io *mc_io,
27192+ uint32_t cmd_flags,
27193+ uint16_t token,
27194+ uint16_t if_id,
27195+ const struct dpsw_reflection_cfg *cfg);
27196+
27197+/**
27198+ * dpsw_if_remove_reflection() - Remove interface to be reflected or mirrored
27199+ * @mc_io: Pointer to MC portal's I/O object
27200+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27201+ * @token: Token of DPSW object
27202+ * @if_id: Interface Identifier
27203+ * @cfg: Reflection configuration
27204+ *
27205+ * Return: Completion status. '0' on Success; Error code otherwise.
27206+ */
27207+int dpsw_if_remove_reflection(struct fsl_mc_io *mc_io,
27208+ uint32_t cmd_flags,
27209+ uint16_t token,
27210+ uint16_t if_id,
27211+ const struct dpsw_reflection_cfg *cfg);
27212+
27213+/**
27214+ * enum dpsw_metering_mode - Metering modes
27215+ * @DPSW_METERING_MODE_NONE: metering disabled
27216+ * @DPSW_METERING_MODE_RFC2698: RFC 2698
27217+ * @DPSW_METERING_MODE_RFC4115: RFC 4115
27218+ */
27219+enum dpsw_metering_mode {
27220+ DPSW_METERING_MODE_NONE = 0,
27221+ DPSW_METERING_MODE_RFC2698,
27222+ DPSW_METERING_MODE_RFC4115
27223+};
27224+
27225+/**
27226+ * enum dpsw_metering_unit - Metering count
27227+ * @DPSW_METERING_UNIT_BYTES: count bytes
27228+ * @DPSW_METERING_UNIT_FRAMES: count frames
27229+ */
27230+enum dpsw_metering_unit {
27231+ DPSW_METERING_UNIT_BYTES = 0,
27232+ DPSW_METERING_UNIT_FRAMES
27233+};
27234+
27235+/**
27236+ * struct dpsw_metering_cfg - Metering configuration
27237+ * @mode: metering modes
27238+ * @units: Bytes or frame units
27239+ * @cir: Committed information rate (CIR) in Kbits/s
27240+ * @eir: Peak information rate (PIR) Kbit/s rfc2698
27241+ * Excess information rate (EIR) Kbit/s rfc4115
27242+ * @cbs: Committed burst size (CBS) in bytes
27243+ * @ebs: Peak burst size (PBS) in bytes for rfc2698
27244+ * Excess bust size (EBS) in bytes rfc4115
27245+ *
27246+ */
27247+struct dpsw_metering_cfg {
27248+ enum dpsw_metering_mode mode;
27249+ enum dpsw_metering_unit units;
27250+ uint32_t cir;
27251+ uint32_t eir;
27252+ uint32_t cbs;
27253+ uint32_t ebs;
27254+};
27255+
27256+/**
27257+ * dpsw_if_set_flooding_metering() - Set flooding metering
27258+ * @mc_io: Pointer to MC portal's I/O object
27259+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27260+ * @token: Token of DPSW object
27261+ * @if_id: Interface Identifier
27262+ * @cfg: Metering parameters
27263+ *
27264+ * Return: Completion status. '0' on Success; Error code otherwise.
27265+ */
27266+int dpsw_if_set_flooding_metering(struct fsl_mc_io *mc_io,
27267+ uint32_t cmd_flags,
27268+ uint16_t token,
27269+ uint16_t if_id,
27270+ const struct dpsw_metering_cfg *cfg);
27271+
27272+/**
27273+ * dpsw_if_set_metering() - Set interface metering for flooding
27274+ * @mc_io: Pointer to MC portal's I/O object
27275+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27276+ * @token: Token of DPSW object
27277+ * @if_id: Interface Identifier
27278+ * @tc_id: Traffic class ID
27279+ * @cfg: Metering parameters
27280+ *
27281+ * Return: Completion status. '0' on Success; Error code otherwise.
27282+ */
27283+int dpsw_if_set_metering(struct fsl_mc_io *mc_io,
27284+ uint32_t cmd_flags,
27285+ uint16_t token,
27286+ uint16_t if_id,
27287+ uint8_t tc_id,
27288+ const struct dpsw_metering_cfg *cfg);
27289+
27290+/**
27291+ * enum dpsw_early_drop_unit - DPSW early drop unit
27292+ * @DPSW_EARLY_DROP_UNIT_BYTE: count bytes
27293+ * @DPSW_EARLY_DROP_UNIT_FRAMES: count frames
27294+ */
27295+enum dpsw_early_drop_unit {
27296+ DPSW_EARLY_DROP_UNIT_BYTE = 0,
27297+ DPSW_EARLY_DROP_UNIT_FRAMES
27298+};
27299+
27300+/**
27301+ * enum dpsw_early_drop_mode - DPSW early drop mode
27302+ * @DPSW_EARLY_DROP_MODE_NONE: early drop is disabled
27303+ * @DPSW_EARLY_DROP_MODE_TAIL: early drop in taildrop mode
27304+ * @DPSW_EARLY_DROP_MODE_WRED: early drop in WRED mode
27305+ */
27306+enum dpsw_early_drop_mode {
27307+ DPSW_EARLY_DROP_MODE_NONE = 0,
27308+ DPSW_EARLY_DROP_MODE_TAIL,
27309+ DPSW_EARLY_DROP_MODE_WRED
27310+};
27311+
27312+/**
27313+ * struct dpsw_wred_cfg - WRED configuration
27314+ * @max_threshold: maximum threshold that packets may be discarded. Above this
27315+ * threshold all packets are discarded; must be less than 2^39;
27316+ * approximated to be expressed as (x+256)*2^(y-1) due to HW
27317+ * implementation.
27318+ * @min_threshold: minimum threshold that packets may be discarded at
27319+ * @drop_probability: probability that a packet will be discarded (1-100,
27320+ * associated with the maximum threshold)
27321+ */
27322+struct dpsw_wred_cfg {
27323+ uint64_t min_threshold;
27324+ uint64_t max_threshold;
27325+ uint8_t drop_probability;
27326+};
27327+
27328+/**
27329+ * struct dpsw_early_drop_cfg - early-drop configuration
27330+ * @drop_mode: drop mode
27331+ * @units: count units
27332+ * @yellow: WRED - 'yellow' configuration
27333+ * @green: WRED - 'green' configuration
27334+ * @tail_drop_threshold: tail drop threshold
27335+ */
27336+struct dpsw_early_drop_cfg {
27337+ enum dpsw_early_drop_mode drop_mode;
27338+ enum dpsw_early_drop_unit units;
27339+ struct dpsw_wred_cfg yellow;
27340+ struct dpsw_wred_cfg green;
27341+ uint32_t tail_drop_threshold;
27342+};
27343+
27344+/**
27345+ * dpsw_prepare_early_drop() - Prepare an early drop for setting in to interface
27346+ * @cfg: Early-drop configuration
27347+ * @early_drop_buf: Zeroed 256 bytes of memory before mapping it to DMA
27348+ *
27349+ * This function has to be called before dpsw_if_tc_set_early_drop
27350+ *
27351+ */
27352+void dpsw_prepare_early_drop(const struct dpsw_early_drop_cfg *cfg,
27353+ uint8_t *early_drop_buf);
27354+
27355+/**
27356+ * dpsw_if_set_early_drop() - Set interface traffic class early-drop
27357+ * configuration
27358+ * @mc_io: Pointer to MC portal's I/O object
27359+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27360+ * @token: Token of DPSW object
27361+ * @if_id: Interface Identifier
27362+ * @tc_id: Traffic class selection (0-7)
27363+ * @early_drop_iova: I/O virtual address of 64 bytes;
27364+ * Must be cacheline-aligned and DMA-able memory
27365+ *
27366+ * warning: Before calling this function, call dpsw_prepare_if_tc_early_drop()
27367+ * to prepare the early_drop_iova parameter
27368+ *
27369+ * Return: '0' on Success; error code otherwise.
27370+ */
27371+int dpsw_if_set_early_drop(struct fsl_mc_io *mc_io,
27372+ uint32_t cmd_flags,
27373+ uint16_t token,
27374+ uint16_t if_id,
27375+ uint8_t tc_id,
27376+ uint64_t early_drop_iova);
27377+
27378+/**
27379+ * struct dpsw_custom_tpid_cfg - Structure representing tag Protocol identifier
27380+ * @tpid: An additional tag protocol identifier
27381+ */
27382+struct dpsw_custom_tpid_cfg {
27383+ uint16_t tpid;
27384+};
27385+
27386+/**
27387+ * dpsw_add_custom_tpid() - API Configures a distinct Ethernet type value
27388+ * @mc_io: Pointer to MC portal's I/O object
27389+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27390+ * @token: Token of DPSW object
27391+ * @cfg: Tag Protocol identifier
27392+ *
27393+ * API Configures a distinct Ethernet type value (or TPID value)
27394+ * to indicate a VLAN tag in addition to the common
27395+ * TPID values 0x8100 and 0x88A8.
27396+ * Two additional TPID's are supported
27397+ *
27398+ * Return: Completion status. '0' on Success; Error code otherwise.
27399+ */
27400+int dpsw_add_custom_tpid(struct fsl_mc_io *mc_io,
27401+ uint32_t cmd_flags,
27402+ uint16_t token,
27403+ const struct dpsw_custom_tpid_cfg *cfg);
27404+
27405+/**
27406+ * dpsw_remove_custom_tpid - API removes a distinct Ethernet type value
27407+ * @mc_io: Pointer to MC portal's I/O object
27408+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27409+ * @token: Token of DPSW object
27410+ * @cfg: Tag Protocol identifier
27411+ *
27412+ * Return: Completion status. '0' on Success; Error code otherwise.
27413+ */
27414+int dpsw_remove_custom_tpid(struct fsl_mc_io *mc_io,
27415+ uint32_t cmd_flags,
27416+ uint16_t token,
27417+ const struct dpsw_custom_tpid_cfg *cfg);
27418+
27419+/**
27420+ * dpsw_if_enable() - Enable Interface
27421+ * @mc_io: Pointer to MC portal's I/O object
27422+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27423+ * @token: Token of DPSW object
27424+ * @if_id: Interface Identifier
27425+ *
27426+ * Return: Completion status. '0' on Success; Error code otherwise.
27427+ */
27428+int dpsw_if_enable(struct fsl_mc_io *mc_io,
27429+ uint32_t cmd_flags,
27430+ uint16_t token,
27431+ uint16_t if_id);
27432+
27433+/**
27434+ * dpsw_if_disable() - Disable Interface
27435+ * @mc_io: Pointer to MC portal's I/O object
27436+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27437+ * @token: Token of DPSW object
27438+ * @if_id: Interface Identifier
27439+ *
27440+ * Return: Completion status. '0' on Success; Error code otherwise.
27441+ */
27442+int dpsw_if_disable(struct fsl_mc_io *mc_io,
27443+ uint32_t cmd_flags,
27444+ uint16_t token,
27445+ uint16_t if_id);
27446+
27447+/**
27448+ * struct dpsw_if_attr - Structure representing DPSW interface attributes
27449+ * @num_tcs: Number of traffic classes
27450+ * @rate: Transmit rate in bits per second
27451+ * @options: Interface configuration options (bitmap)
27452+ * @enabled: Indicates if interface is enabled
27453+ * @accept_all_vlan: The device discards/accepts incoming frames
27454+ * for VLANs that do not include this interface
27455+ * @admit_untagged: When set to 'DPSW_ADMIT_ONLY_VLAN_TAGGED', the device
27456+ * discards untagged frames or priority-tagged frames received on
27457+ * this interface;
27458+ * When set to 'DPSW_ADMIT_ALL', untagged frames or priority-
27459+ * tagged frames received on this interface are accepted
27460+ * @qdid: control frames transmit qdid
27461+ */
27462+struct dpsw_if_attr {
27463+ uint8_t num_tcs;
27464+ uint32_t rate;
27465+ uint32_t options;
27466+ int enabled;
27467+ int accept_all_vlan;
27468+ enum dpsw_accepted_frames admit_untagged;
27469+ uint16_t qdid;
27470+};
27471+
27472+/**
27473+ * dpsw_if_get_attributes() - Function obtains attributes of interface
27474+ * @mc_io: Pointer to MC portal's I/O object
27475+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27476+ * @token: Token of DPSW object
27477+ * @if_id: Interface Identifier
27478+ * @attr: Returned interface attributes
27479+ *
27480+ * Return: Completion status. '0' on Success; Error code otherwise.
27481+ */
27482+int dpsw_if_get_attributes(struct fsl_mc_io *mc_io,
27483+ uint32_t cmd_flags,
27484+ uint16_t token,
27485+ uint16_t if_id,
27486+ struct dpsw_if_attr *attr);
27487+
27488+/**
27489+ * dpsw_if_set_max_frame_length() - Set Maximum Receive frame length.
27490+ * @mc_io: Pointer to MC portal's I/O object
27491+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27492+ * @token: Token of DPSW object
27493+ * @if_id: Interface Identifier
27494+ * @frame_length: Maximum Frame Length
27495+ *
27496+ * Return: Completion status. '0' on Success; Error code otherwise.
27497+ */
27498+int dpsw_if_set_max_frame_length(struct fsl_mc_io *mc_io,
27499+ uint32_t cmd_flags,
27500+ uint16_t token,
27501+ uint16_t if_id,
27502+ uint16_t frame_length);
27503+
27504+/**
27505+ * dpsw_if_get_max_frame_length() - Get Maximum Receive frame length.
27506+ * @mc_io: Pointer to MC portal's I/O object
27507+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27508+ * @token: Token of DPSW object
27509+ * @if_id: Interface Identifier
27510+ * @frame_length: Returned maximum Frame Length
27511+ *
27512+ * Return: Completion status. '0' on Success; Error code otherwise.
27513+ */
27514+int dpsw_if_get_max_frame_length(struct fsl_mc_io *mc_io,
27515+ uint32_t cmd_flags,
27516+ uint16_t token,
27517+ uint16_t if_id,
27518+ uint16_t *frame_length);
27519+
27520+/**
27521+ * struct dpsw_vlan_cfg - VLAN Configuration
27522+ * @fdb_id: Forwarding Data Base
27523+ */
27524+struct dpsw_vlan_cfg {
27525+ uint16_t fdb_id;
27526+};
27527+
27528+/**
27529+ * dpsw_vlan_add() - Adding new VLAN to DPSW.
27530+ * @mc_io: Pointer to MC portal's I/O object
27531+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27532+ * @token: Token of DPSW object
27533+ * @vlan_id: VLAN Identifier
27534+ * @cfg: VLAN configuration
27535+ *
27536+ * Only VLAN ID and FDB ID are required parameters here.
27537+ * 12 bit VLAN ID is defined in IEEE802.1Q.
27538+ * Adding a duplicate VLAN ID is not allowed.
27539+ * FDB ID can be shared across multiple VLANs. Shared learning
27540+ * is obtained by calling dpsw_vlan_add for multiple VLAN IDs
27541+ * with same fdb_id
27542+ *
27543+ * Return: Completion status. '0' on Success; Error code otherwise.
27544+ */
27545+int dpsw_vlan_add(struct fsl_mc_io *mc_io,
27546+ uint32_t cmd_flags,
27547+ uint16_t token,
27548+ uint16_t vlan_id,
27549+ const struct dpsw_vlan_cfg *cfg);
27550+
27551+/**
27552+ * struct dpsw_vlan_if_cfg - Set of VLAN Interfaces
27553+ * @num_ifs: The number of interfaces that are assigned to the egress
27554+ * list for this VLAN
27555+ * @if_id: The set of interfaces that are
27556+ * assigned to the egress list for this VLAN
27557+ */
27558+struct dpsw_vlan_if_cfg {
27559+ uint16_t num_ifs;
27560+ uint16_t if_id[DPSW_MAX_IF];
27561+};
27562+
27563+/**
27564+ * dpsw_vlan_add_if() - Adding a set of interfaces to an existing VLAN.
27565+ * @mc_io: Pointer to MC portal's I/O object
27566+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27567+ * @token: Token of DPSW object
27568+ * @vlan_id: VLAN Identifier
27569+ * @cfg: Set of interfaces to add
27570+ *
27571+ * It adds only interfaces not belonging to this VLAN yet,
27572+ * otherwise an error is generated and an entire command is
27573+ * ignored. This function can be called numerous times always
27574+ * providing required interfaces delta.
27575+ *
27576+ * Return: Completion status. '0' on Success; Error code otherwise.
27577+ */
27578+int dpsw_vlan_add_if(struct fsl_mc_io *mc_io,
27579+ uint32_t cmd_flags,
27580+ uint16_t token,
27581+ uint16_t vlan_id,
27582+ const struct dpsw_vlan_if_cfg *cfg);
27583+
27584+/**
27585+ * dpsw_vlan_add_if_untagged() - Defining a set of interfaces that should be
27586+ * transmitted as untagged.
27587+ * @mc_io: Pointer to MC portal's I/O object
27588+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27589+ * @token: Token of DPSW object
27590+ * @vlan_id: VLAN Identifier
27591+ * @cfg: set of interfaces that should be transmitted as untagged
27592+ *
27593+ * These interfaces should already belong to this VLAN.
27594+ * By default all interfaces are transmitted as tagged.
27595+ * Providing un-existing interface or untagged interface that is
27596+ * configured untagged already generates an error and the entire
27597+ * command is ignored.
27598+ *
27599+ * Return: Completion status. '0' on Success; Error code otherwise.
27600+ */
27601+int dpsw_vlan_add_if_untagged(struct fsl_mc_io *mc_io,
27602+ uint32_t cmd_flags,
27603+ uint16_t token,
27604+ uint16_t vlan_id,
27605+ const struct dpsw_vlan_if_cfg *cfg);
27606+
27607+/**
27608+ * dpsw_vlan_add_if_flooding() - Define a set of interfaces that should be
27609+ * included in flooding when frame with unknown destination
27610+ * unicast MAC arrived.
27611+ * @mc_io: Pointer to MC portal's I/O object
27612+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27613+ * @token: Token of DPSW object
27614+ * @vlan_id: VLAN Identifier
27615+ * @cfg: Set of interfaces that should be used for flooding
27616+ *
27617+ * These interfaces should belong to this VLAN. By default all
27618+ * interfaces are included into flooding list. Providing
27619+ * un-existing interface or an interface that already in the
27620+ * flooding list generates an error and the entire command is
27621+ * ignored.
27622+ *
27623+ * Return: Completion status. '0' on Success; Error code otherwise.
27624+ */
27625+int dpsw_vlan_add_if_flooding(struct fsl_mc_io *mc_io,
27626+ uint32_t cmd_flags,
27627+ uint16_t token,
27628+ uint16_t vlan_id,
27629+ const struct dpsw_vlan_if_cfg *cfg);
27630+
27631+/**
27632+ * dpsw_vlan_remove_if() - Remove interfaces from an existing VLAN.
27633+ * @mc_io: Pointer to MC portal's I/O object
27634+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27635+ * @token: Token of DPSW object
27636+ * @vlan_id: VLAN Identifier
27637+ * @cfg: Set of interfaces that should be removed
27638+ *
27639+ * Interfaces must belong to this VLAN, otherwise an error
27640+ * is returned and an the command is ignored
27641+ *
27642+ * Return: Completion status. '0' on Success; Error code otherwise.
27643+ */
27644+int dpsw_vlan_remove_if(struct fsl_mc_io *mc_io,
27645+ uint32_t cmd_flags,
27646+ uint16_t token,
27647+ uint16_t vlan_id,
27648+ const struct dpsw_vlan_if_cfg *cfg);
27649+
27650+/**
27651+ * dpsw_vlan_remove_if_untagged() - Define a set of interfaces that should be
27652+ * converted from transmitted as untagged to transmit as tagged.
27653+ * @mc_io: Pointer to MC portal's I/O object
27654+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27655+ * @token: Token of DPSW object
27656+ * @vlan_id: VLAN Identifier
27657+ * @cfg: set of interfaces that should be removed
27658+ *
27659+ * Interfaces provided by API have to belong to this VLAN and
27660+ * configured untagged, otherwise an error is returned and the
27661+ * command is ignored
27662+ *
27663+ * Return: Completion status. '0' on Success; Error code otherwise.
27664+ */
27665+int dpsw_vlan_remove_if_untagged(struct fsl_mc_io *mc_io,
27666+ uint32_t cmd_flags,
27667+ uint16_t token,
27668+ uint16_t vlan_id,
27669+ const struct dpsw_vlan_if_cfg *cfg);
27670+
27671+/**
27672+ * dpsw_vlan_remove_if_flooding() - Define a set of interfaces that should be
27673+ * removed from the flooding list.
27674+ * @mc_io: Pointer to MC portal's I/O object
27675+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27676+ * @token: Token of DPSW object
27677+ * @vlan_id: VLAN Identifier
27678+ * @cfg: set of interfaces used for flooding
27679+ *
27680+ * Return: Completion status. '0' on Success; Error code otherwise.
27681+ */
27682+int dpsw_vlan_remove_if_flooding(struct fsl_mc_io *mc_io,
27683+ uint32_t cmd_flags,
27684+ uint16_t token,
27685+ uint16_t vlan_id,
27686+ const struct dpsw_vlan_if_cfg *cfg);
27687+
27688+/**
27689+ * dpsw_vlan_remove() - Remove an entire VLAN
27690+ * @mc_io: Pointer to MC portal's I/O object
27691+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27692+ * @token: Token of DPSW object
27693+ * @vlan_id: VLAN Identifier
27694+ *
27695+ * Return: Completion status. '0' on Success; Error code otherwise.
27696+ */
27697+int dpsw_vlan_remove(struct fsl_mc_io *mc_io,
27698+ uint32_t cmd_flags,
27699+ uint16_t token,
27700+ uint16_t vlan_id);
27701+
27702+/**
27703+ * struct dpsw_vlan_attr - VLAN attributes
27704+ * @fdb_id: Associated FDB ID
27705+ * @num_ifs: Number of interfaces
27706+ * @num_untagged_ifs: Number of untagged interfaces
27707+ * @num_flooding_ifs: Number of flooding interfaces
27708+ */
27709+struct dpsw_vlan_attr {
27710+ uint16_t fdb_id;
27711+ uint16_t num_ifs;
27712+ uint16_t num_untagged_ifs;
27713+ uint16_t num_flooding_ifs;
27714+};
27715+
27716+/**
27717+ * dpsw_vlan_get_attributes() - Get VLAN attributes
27718+ * @mc_io: Pointer to MC portal's I/O object
27719+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27720+ * @token: Token of DPSW object
27721+ * @vlan_id: VLAN Identifier
27722+ * @attr: Returned DPSW attributes
27723+ *
27724+ * Return: Completion status. '0' on Success; Error code otherwise.
27725+ */
27726+int dpsw_vlan_get_attributes(struct fsl_mc_io *mc_io,
27727+ uint32_t cmd_flags,
27728+ uint16_t token,
27729+ uint16_t vlan_id,
27730+ struct dpsw_vlan_attr *attr);
27731+
27732+/**
27733+ * dpsw_vlan_get_if() - Get interfaces belong to this VLAN
27734+ * @mc_io: Pointer to MC portal's I/O object
27735+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27736+ * @token: Token of DPSW object
27737+ * @vlan_id: VLAN Identifier
27738+ * @cfg: Returned set of interfaces belong to this VLAN
27739+ *
27740+ * Return: Completion status. '0' on Success; Error code otherwise.
27741+ */
27742+int dpsw_vlan_get_if(struct fsl_mc_io *mc_io,
27743+ uint32_t cmd_flags,
27744+ uint16_t token,
27745+ uint16_t vlan_id,
27746+ struct dpsw_vlan_if_cfg *cfg);
27747+
27748+/**
27749+ * dpsw_vlan_get_if_flooding() - Get interfaces used in flooding for this VLAN
27750+ * @mc_io: Pointer to MC portal's I/O object
27751+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27752+ * @token: Token of DPSW object
27753+ * @vlan_id: VLAN Identifier
27754+ * @cfg: Returned set of flooding interfaces
27755+ *
27756+ * Return: Completion status. '0' on Success; Error code otherwise.
27757+ */
27758+int dpsw_vlan_get_if_flooding(struct fsl_mc_io *mc_io,
27759+ uint32_t cmd_flags,
27760+ uint16_t token,
27761+ uint16_t vlan_id,
27762+ struct dpsw_vlan_if_cfg *cfg);
27763+
27764+/**
27765+ * dpsw_vlan_get_if_untagged() - Get interfaces that should be transmitted as
27766+ * untagged
27767+ * @mc_io: Pointer to MC portal's I/O object
27768+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27769+ * @token: Token of DPSW object
27770+ * @vlan_id: VLAN Identifier
27771+ * @cfg: Returned set of untagged interfaces
27772+ *
27773+ * Return: Completion status. '0' on Success; Error code otherwise.
27774+ */
27775+int dpsw_vlan_get_if_untagged(struct fsl_mc_io *mc_io,
27776+ uint32_t cmd_flags,
27777+ uint16_t token,
27778+ uint16_t vlan_id,
27779+ struct dpsw_vlan_if_cfg *cfg);
27780+
27781+/**
27782+ * struct dpsw_fdb_cfg - FDB Configuration
27783+ * @num_fdb_entries: Number of FDB entries
27784+ * @fdb_aging_time: Aging time in seconds
27785+ */
27786+struct dpsw_fdb_cfg {
27787+ uint16_t num_fdb_entries;
27788+ uint16_t fdb_aging_time;
27789+};
27790+
27791+/**
27792+ * dpsw_fdb_add() - Add FDB to switch and Returns handle to FDB table for
27793+ * the reference
27794+ * @mc_io: Pointer to MC portal's I/O object
27795+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27796+ * @token: Token of DPSW object
27797+ * @fdb_id: Returned Forwarding Database Identifier
27798+ * @cfg: FDB Configuration
27799+ *
27800+ * Return: Completion status. '0' on Success; Error code otherwise.
27801+ */
27802+int dpsw_fdb_add(struct fsl_mc_io *mc_io,
27803+ uint32_t cmd_flags,
27804+ uint16_t token,
27805+ uint16_t *fdb_id,
27806+ const struct dpsw_fdb_cfg *cfg);
27807+
27808+/**
27809+ * dpsw_fdb_remove() - Remove FDB from switch
27810+ * @mc_io: Pointer to MC portal's I/O object
27811+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27812+ * @token: Token of DPSW object
27813+ * @fdb_id: Forwarding Database Identifier
27814+ *
27815+ * Return: Completion status. '0' on Success; Error code otherwise.
27816+ */
27817+int dpsw_fdb_remove(struct fsl_mc_io *mc_io,
27818+ uint32_t cmd_flags,
27819+ uint16_t token,
27820+ uint16_t fdb_id);
27821+
27822+/**
27823+ * enum dpsw_fdb_entry_type - FDB Entry type - Static/Dynamic
27824+ * @DPSW_FDB_ENTRY_STATIC: Static entry
27825+ * @DPSW_FDB_ENTRY_DINAMIC: Dynamic entry
27826+ */
27827+enum dpsw_fdb_entry_type {
27828+ DPSW_FDB_ENTRY_STATIC = 0,
27829+ DPSW_FDB_ENTRY_DINAMIC = 1
27830+};
27831+
27832+/**
27833+ * struct dpsw_fdb_unicast_cfg - Unicast entry configuration
27834+ * @type: Select static or dynamic entry
27835+ * @mac_addr: MAC address
27836+ * @if_egress: Egress interface ID
27837+ */
27838+struct dpsw_fdb_unicast_cfg {
27839+ enum dpsw_fdb_entry_type type;
27840+ uint8_t mac_addr[6];
27841+ uint16_t if_egress;
27842+};
27843+
27844+/**
27845+ * dpsw_fdb_add_unicast() - Function adds an unicast entry into MAC lookup table
27846+ * @mc_io: Pointer to MC portal's I/O object
27847+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27848+ * @token: Token of DPSW object
27849+ * @fdb_id: Forwarding Database Identifier
27850+ * @cfg: Unicast entry configuration
27851+ *
27852+ * Return: Completion status. '0' on Success; Error code otherwise.
27853+ */
27854+int dpsw_fdb_add_unicast(struct fsl_mc_io *mc_io,
27855+ uint32_t cmd_flags,
27856+ uint16_t token,
27857+ uint16_t fdb_id,
27858+ const struct dpsw_fdb_unicast_cfg *cfg);
27859+
27860+/**
27861+ * dpsw_fdb_get_unicast() - Get unicast entry from MAC lookup table by
27862+ * unicast Ethernet address
27863+ * @mc_io: Pointer to MC portal's I/O object
27864+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27865+ * @token: Token of DPSW object
27866+ * @fdb_id: Forwarding Database Identifier
27867+ * @cfg: Returned unicast entry configuration
27868+ *
27869+ * Return: Completion status. '0' on Success; Error code otherwise.
27870+ */
27871+int dpsw_fdb_get_unicast(struct fsl_mc_io *mc_io,
27872+ uint32_t cmd_flags,
27873+ uint16_t token,
27874+ uint16_t fdb_id,
27875+ struct dpsw_fdb_unicast_cfg *cfg);
27876+
27877+/**
27878+ * dpsw_fdb_remove_unicast() - removes an entry from MAC lookup table
27879+ * @mc_io: Pointer to MC portal's I/O object
27880+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27881+ * @token: Token of DPSW object
27882+ * @fdb_id: Forwarding Database Identifier
27883+ * @cfg: Unicast entry configuration
27884+ *
27885+ * Return: Completion status. '0' on Success; Error code otherwise.
27886+ */
27887+int dpsw_fdb_remove_unicast(struct fsl_mc_io *mc_io,
27888+ uint32_t cmd_flags,
27889+ uint16_t token,
27890+ uint16_t fdb_id,
27891+ const struct dpsw_fdb_unicast_cfg *cfg);
27892+
27893+/**
27894+ * struct dpsw_fdb_multicast_cfg - Multi-cast entry configuration
27895+ * @type: Select static or dynamic entry
27896+ * @mac_addr: MAC address
27897+ * @num_ifs: Number of external and internal interfaces
27898+ * @if_id: Egress interface IDs
27899+ */
27900+struct dpsw_fdb_multicast_cfg {
27901+ enum dpsw_fdb_entry_type type;
27902+ uint8_t mac_addr[6];
27903+ uint16_t num_ifs;
27904+ uint16_t if_id[DPSW_MAX_IF];
27905+};
27906+
27907+/**
27908+ * dpsw_fdb_add_multicast() - Add a set of egress interfaces to multi-cast group
27909+ * @mc_io: Pointer to MC portal's I/O object
27910+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27911+ * @token: Token of DPSW object
27912+ * @fdb_id: Forwarding Database Identifier
27913+ * @cfg: Multicast entry configuration
27914+ *
27915+ * If group doesn't exist, it will be created.
27916+ * It adds only interfaces not belonging to this multicast group
27917+ * yet, otherwise error will be generated and the command is
27918+ * ignored.
27919+ * This function may be called numerous times always providing
27920+ * required interfaces delta.
27921+ *
27922+ * Return: Completion status. '0' on Success; Error code otherwise.
27923+ */
27924+int dpsw_fdb_add_multicast(struct fsl_mc_io *mc_io,
27925+ uint32_t cmd_flags,
27926+ uint16_t token,
27927+ uint16_t fdb_id,
27928+ const struct dpsw_fdb_multicast_cfg *cfg);
27929+
27930+/**
27931+ * dpsw_fdb_get_multicast() - Reading multi-cast group by multi-cast Ethernet
27932+ * address.
27933+ * @mc_io: Pointer to MC portal's I/O object
27934+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27935+ * @token: Token of DPSW object
27936+ * @fdb_id: Forwarding Database Identifier
27937+ * @cfg: Returned multicast entry configuration
27938+ *
27939+ * Return: Completion status. '0' on Success; Error code otherwise.
27940+ */
27941+int dpsw_fdb_get_multicast(struct fsl_mc_io *mc_io,
27942+ uint32_t cmd_flags,
27943+ uint16_t token,
27944+ uint16_t fdb_id,
27945+ struct dpsw_fdb_multicast_cfg *cfg);
27946+
27947+/**
27948+ * dpsw_fdb_remove_multicast() - Removing interfaces from an existing multicast
27949+ * group.
27950+ * @mc_io: Pointer to MC portal's I/O object
27951+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
27952+ * @token: Token of DPSW object
27953+ * @fdb_id: Forwarding Database Identifier
27954+ * @cfg: Multicast entry configuration
27955+ *
27956+ * Interfaces provided by this API have to exist in the group,
27957+ * otherwise an error will be returned and an entire command
27958+ * ignored. If there is no interface left in the group,
27959+ * an entire group is deleted
27960+ *
27961+ * Return: Completion status. '0' on Success; Error code otherwise.
27962+ */
27963+int dpsw_fdb_remove_multicast(struct fsl_mc_io *mc_io,
27964+ uint32_t cmd_flags,
27965+ uint16_t token,
27966+ uint16_t fdb_id,
27967+ const struct dpsw_fdb_multicast_cfg *cfg);
27968+
27969+/**
27970+ * enum dpsw_fdb_learning_mode - Auto-learning modes
27971+ * @DPSW_FDB_LEARNING_MODE_DIS: Disable Auto-learning
27972+ * @DPSW_FDB_LEARNING_MODE_HW: Enable HW auto-Learning
27973+ * @DPSW_FDB_LEARNING_MODE_NON_SECURE: Enable None secure learning by CPU
27974+ * @DPSW_FDB_LEARNING_MODE_SECURE: Enable secure learning by CPU
27975+ *
27976+ * NONE - SECURE LEARNING
27977+ * SMAC found DMAC found CTLU Action
27978+ * v v Forward frame to
27979+ * 1. DMAC destination
27980+ * - v Forward frame to
27981+ * 1. DMAC destination
27982+ * 2. Control interface
27983+ * v - Forward frame to
27984+ * 1. Flooding list of interfaces
27985+ * - - Forward frame to
27986+ * 1. Flooding list of interfaces
27987+ * 2. Control interface
27988+ * SECURE LEARING
27989+ * SMAC found DMAC found CTLU Action
27990+ * v v Forward frame to
27991+ * 1. DMAC destination
27992+ * - v Forward frame to
27993+ * 1. Control interface
27994+ * v - Forward frame to
27995+ * 1. Flooding list of interfaces
27996+ * - - Forward frame to
27997+ * 1. Control interface
27998+ */
27999+enum dpsw_fdb_learning_mode {
28000+ DPSW_FDB_LEARNING_MODE_DIS = 0,
28001+ DPSW_FDB_LEARNING_MODE_HW = 1,
28002+ DPSW_FDB_LEARNING_MODE_NON_SECURE = 2,
28003+ DPSW_FDB_LEARNING_MODE_SECURE = 3
28004+};
28005+
28006+/**
28007+ * dpsw_fdb_set_learning_mode() - Define FDB learning mode
28008+ * @mc_io: Pointer to MC portal's I/O object
28009+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28010+ * @token: Token of DPSW object
28011+ * @fdb_id: Forwarding Database Identifier
28012+ * @mode: learning mode
28013+ *
28014+ * Return: Completion status. '0' on Success; Error code otherwise.
28015+ */
28016+int dpsw_fdb_set_learning_mode(struct fsl_mc_io *mc_io,
28017+ uint32_t cmd_flags,
28018+ uint16_t token,
28019+ uint16_t fdb_id,
28020+ enum dpsw_fdb_learning_mode mode);
28021+
28022+/**
28023+ * struct dpsw_fdb_attr - FDB Attributes
28024+ * @max_fdb_entries: Number of FDB entries
28025+ * @fdb_aging_time: Aging time in seconds
28026+ * @learning_mode: Learning mode
28027+ * @num_fdb_mc_groups: Current number of multicast groups
28028+ * @max_fdb_mc_groups: Maximum number of multicast groups
28029+ */
28030+struct dpsw_fdb_attr {
28031+ uint16_t max_fdb_entries;
28032+ uint16_t fdb_aging_time;
28033+ enum dpsw_fdb_learning_mode learning_mode;
28034+ uint16_t num_fdb_mc_groups;
28035+ uint16_t max_fdb_mc_groups;
28036+};
28037+
28038+/**
28039+ * dpsw_fdb_get_attributes() - Get FDB attributes
28040+ * @mc_io: Pointer to MC portal's I/O object
28041+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28042+ * @token: Token of DPSW object
28043+ * @fdb_id: Forwarding Database Identifier
28044+ * @attr: Returned FDB attributes
28045+ *
28046+ * Return: Completion status. '0' on Success; Error code otherwise.
28047+ */
28048+int dpsw_fdb_get_attributes(struct fsl_mc_io *mc_io,
28049+ uint32_t cmd_flags,
28050+ uint16_t token,
28051+ uint16_t fdb_id,
28052+ struct dpsw_fdb_attr *attr);
28053+
28054+/**
28055+ * struct dpsw_acl_cfg - ACL Configuration
28056+ * @max_entries: Number of FDB entries
28057+ */
28058+struct dpsw_acl_cfg {
28059+ uint16_t max_entries;
28060+};
28061+
28062+/**
28063+ * struct dpsw_acl_fields - ACL fields.
28064+ * @l2_dest_mac: Destination MAC address: BPDU, Multicast, Broadcast, Unicast,
28065+ * slow protocols, MVRP, STP
28066+ * @l2_source_mac: Source MAC address
28067+ * @l2_tpid: Layer 2 (Ethernet) protocol type, used to identify the following
28068+ * protocols: MPLS, PTP, PFC, ARP, Jumbo frames, LLDP, IEEE802.1ae,
28069+ * Q-in-Q, IPv4, IPv6, PPPoE
28070+ * @l2_pcp_dei: indicate which protocol is encapsulated in the payload
28071+ * @l2_vlan_id: layer 2 VLAN ID
28072+ * @l2_ether_type: layer 2 Ethernet type
28073+ * @l3_dscp: Layer 3 differentiated services code point
28074+ * @l3_protocol: Tells the Network layer at the destination host, to which
28075+ * Protocol this packet belongs to. The following protocol are
28076+ * supported: ICMP, IGMP, IPv4 (encapsulation), TCP, IPv6
28077+ * (encapsulation), GRE, PTP
28078+ * @l3_source_ip: Source IPv4 IP
28079+ * @l3_dest_ip: Destination IPv4 IP
28080+ * @l4_source_port: Source TCP/UDP Port
28081+ * @l4_dest_port: Destination TCP/UDP Port
28082+ */
28083+struct dpsw_acl_fields {
28084+ uint8_t l2_dest_mac[6];
28085+ uint8_t l2_source_mac[6];
28086+ uint16_t l2_tpid;
28087+ uint8_t l2_pcp_dei;
28088+ uint16_t l2_vlan_id;
28089+ uint16_t l2_ether_type;
28090+ uint8_t l3_dscp;
28091+ uint8_t l3_protocol;
28092+ uint32_t l3_source_ip;
28093+ uint32_t l3_dest_ip;
28094+ uint16_t l4_source_port;
28095+ uint16_t l4_dest_port;
28096+};
28097+
28098+/**
28099+ * struct dpsw_acl_key - ACL key
28100+ * @match: Match fields
28101+ * @mask: Mask: b'1 - valid, b'0 don't care
28102+ */
28103+struct dpsw_acl_key {
28104+ struct dpsw_acl_fields match;
28105+ struct dpsw_acl_fields mask;
28106+};
28107+
28108+/**
28109+ * enum dpsw_acl_action
28110+ * @DPSW_ACL_ACTION_DROP: Drop frame
28111+ * @DPSW_ACL_ACTION_REDIRECT: Redirect to certain port
28112+ * @DPSW_ACL_ACTION_ACCEPT: Accept frame
28113+ * @DPSW_ACL_ACTION_REDIRECT_TO_CTRL_IF: Redirect to control interface
28114+ */
28115+enum dpsw_acl_action {
28116+ DPSW_ACL_ACTION_DROP,
28117+ DPSW_ACL_ACTION_REDIRECT,
28118+ DPSW_ACL_ACTION_ACCEPT,
28119+ DPSW_ACL_ACTION_REDIRECT_TO_CTRL_IF
28120+};
28121+
28122+/**
28123+ * struct dpsw_acl_result - ACL action
28124+ * @action: Action should be taken when ACL entry hit
28125+ * @if_id: Interface IDs to redirect frame. Valid only if redirect selected for
28126+ * action
28127+ */
28128+struct dpsw_acl_result {
28129+ enum dpsw_acl_action action;
28130+ uint16_t if_id;
28131+};
28132+
28133+/**
28134+ * struct dpsw_acl_entry_cfg - ACL entry
28135+ * @key_iova: I/O virtual address of DMA-able memory filled with key after call
28136+ * to dpsw_acl_prepare_entry_cfg()
28137+ * @result: Required action when entry hit occurs
28138+ * @precedence: Precedence inside ACL 0 is lowest; This priority can not change
28139+ * during the lifetime of a Policy. It is user responsibility to
28140+ * space the priorities according to consequent rule additions.
28141+ */
28142+struct dpsw_acl_entry_cfg {
28143+ uint64_t key_iova;
28144+ struct dpsw_acl_result result;
28145+ int precedence;
28146+};
28147+
28148+/**
28149+ * dpsw_acl_add() - Adds ACL to L2 switch.
28150+ * @mc_io: Pointer to MC portal's I/O object
28151+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28152+ * @token: Token of DPSW object
28153+ * @acl_id: Returned ACL ID, for the future reference
28154+ * @cfg: ACL configuration
28155+ *
28156+ * Create Access Control List. Multiple ACLs can be created and
28157+ * co-exist in L2 switch
28158+ *
28159+ * Return: '0' on Success; Error code otherwise.
28160+ */
28161+int dpsw_acl_add(struct fsl_mc_io *mc_io,
28162+ uint32_t cmd_flags,
28163+ uint16_t token,
28164+ uint16_t *acl_id,
28165+ const struct dpsw_acl_cfg *cfg);
28166+
28167+/**
28168+ * dpsw_acl_remove() - Removes ACL from L2 switch.
28169+ * @mc_io: Pointer to MC portal's I/O object
28170+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28171+ * @token: Token of DPSW object
28172+ * @acl_id: ACL ID
28173+ *
28174+ * Return: '0' on Success; Error code otherwise.
28175+ */
28176+int dpsw_acl_remove(struct fsl_mc_io *mc_io,
28177+ uint32_t cmd_flags,
28178+ uint16_t token,
28179+ uint16_t acl_id);
28180+
28181+/**
28182+ * dpsw_acl_prepare_entry_cfg() - Set an entry to ACL.
28183+ * @key: key
28184+ * @entry_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA
28185+ *
28186+ * This function has to be called before adding or removing acl_entry
28187+ *
28188+ */
28189+void dpsw_acl_prepare_entry_cfg(const struct dpsw_acl_key *key,
28190+ uint8_t *entry_cfg_buf);
28191+
28192+/**
28193+ * dpsw_acl_add_entry() - Adds an entry to ACL.
28194+ * @mc_io: Pointer to MC portal's I/O object
28195+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28196+ * @token: Token of DPSW object
28197+ * @acl_id: ACL ID
28198+ * @cfg: entry configuration
28199+ *
28200+ * warning: This function has to be called after dpsw_acl_set_entry_cfg()
28201+ *
28202+ * Return: '0' on Success; Error code otherwise.
28203+ */
28204+int dpsw_acl_add_entry(struct fsl_mc_io *mc_io,
28205+ uint32_t cmd_flags,
28206+ uint16_t token,
28207+ uint16_t acl_id,
28208+ const struct dpsw_acl_entry_cfg *cfg);
28209+
28210+/**
28211+ * dpsw_acl_remove_entry() - Removes an entry from ACL.
28212+ * @mc_io: Pointer to MC portal's I/O object
28213+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28214+ * @token: Token of DPSW object
28215+ * @acl_id: ACL ID
28216+ * @cfg: entry configuration
28217+ *
28218+ * warning: This function has to be called after dpsw_acl_set_entry_cfg()
28219+ *
28220+ * Return: '0' on Success; Error code otherwise.
28221+ */
28222+int dpsw_acl_remove_entry(struct fsl_mc_io *mc_io,
28223+ uint32_t cmd_flags,
28224+ uint16_t token,
28225+ uint16_t acl_id,
28226+ const struct dpsw_acl_entry_cfg *cfg);
28227+
28228+/**
28229+ * struct dpsw_acl_if_cfg - List of interfaces to Associate with ACL
28230+ * @num_ifs: Number of interfaces
28231+ * @if_id: List of interfaces
28232+ */
28233+struct dpsw_acl_if_cfg {
28234+ uint16_t num_ifs;
28235+ uint16_t if_id[DPSW_MAX_IF];
28236+};
28237+
28238+/**
28239+ * dpsw_acl_add_if() - Associate interface/interfaces with ACL.
28240+ * @mc_io: Pointer to MC portal's I/O object
28241+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28242+ * @token: Token of DPSW object
28243+ * @acl_id: ACL ID
28244+ * @cfg: interfaces list
28245+ *
28246+ * Return: '0' on Success; Error code otherwise.
28247+ */
28248+int dpsw_acl_add_if(struct fsl_mc_io *mc_io,
28249+ uint32_t cmd_flags,
28250+ uint16_t token,
28251+ uint16_t acl_id,
28252+ const struct dpsw_acl_if_cfg *cfg);
28253+
28254+/**
28255+ * dpsw_acl_remove_if() - De-associate interface/interfaces from ACL.
28256+ * @mc_io: Pointer to MC portal's I/O object
28257+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28258+ * @token: Token of DPSW object
28259+ * @acl_id: ACL ID
28260+ * @cfg: interfaces list
28261+ *
28262+ * Return: '0' on Success; Error code otherwise.
28263+ */
28264+int dpsw_acl_remove_if(struct fsl_mc_io *mc_io,
28265+ uint32_t cmd_flags,
28266+ uint16_t token,
28267+ uint16_t acl_id,
28268+ const struct dpsw_acl_if_cfg *cfg);
28269+
28270+/**
28271+ * struct dpsw_acl_attr - ACL Attributes
28272+ * @max_entries: Max number of ACL entries
28273+ * @num_entries: Number of used ACL entries
28274+ * @num_ifs: Number of interfaces associated with ACL
28275+ */
28276+struct dpsw_acl_attr {
28277+ uint16_t max_entries;
28278+ uint16_t num_entries;
28279+ uint16_t num_ifs;
28280+};
28281+
28282+/**
28283+* dpsw_acl_get_attributes() - Get specific counter of particular interface
28284+* @mc_io: Pointer to MC portal's I/O object
28285+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28286+* @token: Token of DPSW object
28287+* @acl_id: ACL Identifier
28288+* @attr: Returned ACL attributes
28289+*
28290+* Return: '0' on Success; Error code otherwise.
28291+*/
28292+int dpsw_acl_get_attributes(struct fsl_mc_io *mc_io,
28293+ uint32_t cmd_flags,
28294+ uint16_t token,
28295+ uint16_t acl_id,
28296+ struct dpsw_acl_attr *attr);
28297+/**
28298+* struct dpsw_ctrl_if_attr - Control interface attributes
28299+* @rx_fqid: Receive FQID
28300+* @rx_err_fqid: Receive error FQID
28301+* @tx_err_conf_fqid: Transmit error and confirmation FQID
28302+*/
28303+struct dpsw_ctrl_if_attr {
28304+ uint32_t rx_fqid;
28305+ uint32_t rx_err_fqid;
28306+ uint32_t tx_err_conf_fqid;
28307+};
28308+
28309+/**
28310+* dpsw_ctrl_if_get_attributes() - Obtain control interface attributes
28311+* @mc_io: Pointer to MC portal's I/O object
28312+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28313+* @token: Token of DPSW object
28314+* @attr: Returned control interface attributes
28315+*
28316+* Return: '0' on Success; Error code otherwise.
28317+*/
28318+int dpsw_ctrl_if_get_attributes(struct fsl_mc_io *mc_io,
28319+ uint32_t cmd_flags,
28320+ uint16_t token,
28321+ struct dpsw_ctrl_if_attr *attr);
28322+
28323+/**
28324+ * Maximum number of DPBP
28325+ */
28326+#define DPSW_MAX_DPBP 8
28327+
28328+/**
28329+ * struct dpsw_ctrl_if_pools_cfg - Control interface buffer pools configuration
28330+ * @num_dpbp: Number of DPBPs
28331+ * @pools: Array of buffer pools parameters; The number of valid entries
28332+ * must match 'num_dpbp' value
28333+ */
28334+struct dpsw_ctrl_if_pools_cfg {
28335+ uint8_t num_dpbp;
28336+ /**
28337+ * struct pools - Buffer pools parameters
28338+ * @dpbp_id: DPBP object ID
28339+ * @buffer_size: Buffer size
28340+ * @backup_pool: Backup pool
28341+ */
28342+ struct {
28343+ int dpbp_id;
28344+ uint16_t buffer_size;
28345+ int backup_pool;
28346+ } pools[DPSW_MAX_DPBP];
28347+};
28348+
28349+/**
28350+* dpsw_ctrl_if_set_pools() - Set control interface buffer pools
28351+* @mc_io: Pointer to MC portal's I/O object
28352+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28353+* @token: Token of DPSW object
28354+* @cfg: buffer pools configuration
28355+*
28356+* Return: '0' on Success; Error code otherwise.
28357+*/
28358+int dpsw_ctrl_if_set_pools(struct fsl_mc_io *mc_io,
28359+ uint32_t cmd_flags,
28360+ uint16_t token,
28361+ const struct dpsw_ctrl_if_pools_cfg *cfg);
28362+
28363+/**
28364+* dpsw_ctrl_if_enable() - Enable control interface
28365+* @mc_io: Pointer to MC portal's I/O object
28366+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28367+* @token: Token of DPSW object
28368+*
28369+* Return: '0' on Success; Error code otherwise.
28370+*/
28371+int dpsw_ctrl_if_enable(struct fsl_mc_io *mc_io,
28372+ uint32_t cmd_flags,
28373+ uint16_t token);
28374+
28375+/**
28376+* dpsw_ctrl_if_disable() - Function disables control interface
28377+* @mc_io: Pointer to MC portal's I/O object
28378+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
28379+* @token: Token of DPSW object
28380+*
28381+* Return: '0' on Success; Error code otherwise.
28382+*/
28383+int dpsw_ctrl_if_disable(struct fsl_mc_io *mc_io,
28384+ uint32_t cmd_flags,
28385+ uint16_t token);
28386+
28387+#endif /* __FSL_DPSW_H */
28388diff --git a/drivers/net/dpaa2/mc/fsl_dpsw_cmd.h b/drivers/net/dpaa2/mc/fsl_dpsw_cmd.h
28389new file mode 100644
28390index 0000000..c65fe38
28391--- /dev/null
28392+++ b/drivers/net/dpaa2/mc/fsl_dpsw_cmd.h
28393@@ -0,0 +1,916 @@
28394+/* Copyright 2013-2015 Freescale Semiconductor Inc.
28395+ *
28396+ * Redistribution and use in source and binary forms, with or without
28397+ * modification, are permitted provided that the following conditions are met:
28398+ * * Redistributions of source code must retain the above copyright
28399+ * notice, this list of conditions and the following disclaimer.
28400+ * * Redistributions in binary form must reproduce the above copyright
28401+ * notice, this list of conditions and the following disclaimer in the
28402+ * documentation and/or other materials provided with the distribution.
28403+ * * Neither the name of the above-listed copyright holders nor the
28404+ * names of any contributors may be used to endorse or promote products
28405+ * derived from this software without specific prior written permission.
28406+ *
28407+ *
28408+ * ALTERNATIVELY, this software may be distributed under the terms of the
28409+ * GNU General Public License ("GPL") as published by the Free Software
28410+ * Foundation, either version 2 of that License or (at your option) any
28411+ * later version.
28412+ *
28413+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28414+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28415+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28416+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
28417+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28418+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28419+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28420+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28421+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28422+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28423+ * POSSIBILITY OF SUCH DAMAGE.
28424+ */
28425+#ifndef __FSL_DPSW_CMD_H
28426+#define __FSL_DPSW_CMD_H
28427+
28428+/* DPSW Version */
28429+#define DPSW_VER_MAJOR 7
28430+#define DPSW_VER_MINOR 0
28431+
28432+/* Command IDs */
28433+#define DPSW_CMDID_CLOSE 0x800
28434+#define DPSW_CMDID_OPEN 0x802
28435+#define DPSW_CMDID_CREATE 0x902
28436+#define DPSW_CMDID_DESTROY 0x900
28437+
28438+#define DPSW_CMDID_ENABLE 0x002
28439+#define DPSW_CMDID_DISABLE 0x003
28440+#define DPSW_CMDID_GET_ATTR 0x004
28441+#define DPSW_CMDID_RESET 0x005
28442+#define DPSW_CMDID_IS_ENABLED 0x006
28443+
28444+#define DPSW_CMDID_SET_IRQ 0x010
28445+#define DPSW_CMDID_GET_IRQ 0x011
28446+#define DPSW_CMDID_SET_IRQ_ENABLE 0x012
28447+#define DPSW_CMDID_GET_IRQ_ENABLE 0x013
28448+#define DPSW_CMDID_SET_IRQ_MASK 0x014
28449+#define DPSW_CMDID_GET_IRQ_MASK 0x015
28450+#define DPSW_CMDID_GET_IRQ_STATUS 0x016
28451+#define DPSW_CMDID_CLEAR_IRQ_STATUS 0x017
28452+
28453+#define DPSW_CMDID_SET_REFLECTION_IF 0x022
28454+
28455+#define DPSW_CMDID_ADD_CUSTOM_TPID 0x024
28456+
28457+#define DPSW_CMDID_REMOVE_CUSTOM_TPID 0x026
28458+
28459+#define DPSW_CMDID_IF_SET_TCI 0x030
28460+#define DPSW_CMDID_IF_SET_STP 0x031
28461+#define DPSW_CMDID_IF_SET_ACCEPTED_FRAMES 0x032
28462+#define DPSW_CMDID_SET_IF_ACCEPT_ALL_VLAN 0x033
28463+#define DPSW_CMDID_IF_GET_COUNTER 0x034
28464+#define DPSW_CMDID_IF_SET_COUNTER 0x035
28465+#define DPSW_CMDID_IF_SET_TX_SELECTION 0x036
28466+#define DPSW_CMDID_IF_ADD_REFLECTION 0x037
28467+#define DPSW_CMDID_IF_REMOVE_REFLECTION 0x038
28468+#define DPSW_CMDID_IF_SET_FLOODING_METERING 0x039
28469+#define DPSW_CMDID_IF_SET_METERING 0x03A
28470+#define DPSW_CMDID_IF_SET_EARLY_DROP 0x03B
28471+
28472+#define DPSW_CMDID_IF_ENABLE 0x03D
28473+#define DPSW_CMDID_IF_DISABLE 0x03E
28474+
28475+#define DPSW_CMDID_IF_GET_ATTR 0x042
28476+
28477+#define DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH 0x044
28478+#define DPSW_CMDID_IF_GET_MAX_FRAME_LENGTH 0x045
28479+#define DPSW_CMDID_IF_GET_LINK_STATE 0x046
28480+#define DPSW_CMDID_IF_SET_FLOODING 0x047
28481+#define DPSW_CMDID_IF_SET_BROADCAST 0x048
28482+#define DPSW_CMDID_IF_SET_MULTICAST 0x049
28483+#define DPSW_CMDID_IF_GET_TCI 0x04A
28484+
28485+#define DPSW_CMDID_IF_SET_LINK_CFG 0x04C
28486+
28487+#define DPSW_CMDID_VLAN_ADD 0x060
28488+#define DPSW_CMDID_VLAN_ADD_IF 0x061
28489+#define DPSW_CMDID_VLAN_ADD_IF_UNTAGGED 0x062
28490+#define DPSW_CMDID_VLAN_ADD_IF_FLOODING 0x063
28491+#define DPSW_CMDID_VLAN_REMOVE_IF 0x064
28492+#define DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED 0x065
28493+#define DPSW_CMDID_VLAN_REMOVE_IF_FLOODING 0x066
28494+#define DPSW_CMDID_VLAN_REMOVE 0x067
28495+#define DPSW_CMDID_VLAN_GET_IF 0x068
28496+#define DPSW_CMDID_VLAN_GET_IF_FLOODING 0x069
28497+#define DPSW_CMDID_VLAN_GET_IF_UNTAGGED 0x06A
28498+#define DPSW_CMDID_VLAN_GET_ATTRIBUTES 0x06B
28499+
28500+#define DPSW_CMDID_FDB_GET_MULTICAST 0x080
28501+#define DPSW_CMDID_FDB_GET_UNICAST 0x081
28502+#define DPSW_CMDID_FDB_ADD 0x082
28503+#define DPSW_CMDID_FDB_REMOVE 0x083
28504+#define DPSW_CMDID_FDB_ADD_UNICAST 0x084
28505+#define DPSW_CMDID_FDB_REMOVE_UNICAST 0x085
28506+#define DPSW_CMDID_FDB_ADD_MULTICAST 0x086
28507+#define DPSW_CMDID_FDB_REMOVE_MULTICAST 0x087
28508+#define DPSW_CMDID_FDB_SET_LEARNING_MODE 0x088
28509+#define DPSW_CMDID_FDB_GET_ATTR 0x089
28510+
28511+#define DPSW_CMDID_ACL_ADD 0x090
28512+#define DPSW_CMDID_ACL_REMOVE 0x091
28513+#define DPSW_CMDID_ACL_ADD_ENTRY 0x092
28514+#define DPSW_CMDID_ACL_REMOVE_ENTRY 0x093
28515+#define DPSW_CMDID_ACL_ADD_IF 0x094
28516+#define DPSW_CMDID_ACL_REMOVE_IF 0x095
28517+#define DPSW_CMDID_ACL_GET_ATTR 0x096
28518+
28519+#define DPSW_CMDID_CTRL_IF_GET_ATTR 0x0A0
28520+#define DPSW_CMDID_CTRL_IF_SET_POOLS 0x0A1
28521+#define DPSW_CMDID_CTRL_IF_ENABLE 0x0A2
28522+#define DPSW_CMDID_CTRL_IF_DISABLE 0x0A3
28523+
28524+/* cmd, param, offset, width, type, arg_name */
28525+#define DPSW_CMD_OPEN(cmd, dpsw_id) \
28526+ MC_CMD_OP(cmd, 0, 0, 32, int, dpsw_id)
28527+
28528+/* cmd, param, offset, width, type, arg_name */
28529+#define DPSW_CMD_CREATE(cmd, cfg) \
28530+do { \
28531+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->num_ifs);\
28532+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->adv.max_fdbs);\
28533+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->adv.max_meters_per_if);\
28534+ MC_CMD_OP(cmd, 0, 32, 4, enum dpsw_component_type, \
28535+ cfg->adv.component_type);\
28536+ MC_CMD_OP(cmd, 1, 0, 16, uint16_t, cfg->adv.max_vlans);\
28537+ MC_CMD_OP(cmd, 1, 16, 16, uint16_t, cfg->adv.max_fdb_entries);\
28538+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, cfg->adv.fdb_aging_time);\
28539+ MC_CMD_OP(cmd, 1, 48, 16, uint16_t, cfg->adv.max_fdb_mc_groups);\
28540+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->adv.options);\
28541+} while (0)
28542+
28543+/* cmd, param, offset, width, type, arg_name */
28544+#define DPSW_RSP_IS_ENABLED(cmd, en) \
28545+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
28546+
28547+/* cmd, param, offset, width, type, arg_name */
28548+#define DPSW_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
28549+do { \
28550+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
28551+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
28552+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
28553+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
28554+} while (0)
28555+
28556+/* cmd, param, offset, width, type, arg_name */
28557+#define DPSW_CMD_GET_IRQ(cmd, irq_index) \
28558+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
28559+
28560+/* cmd, param, offset, width, type, arg_name */
28561+#define DPSW_RSP_GET_IRQ(cmd, type, irq_cfg) \
28562+do { \
28563+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
28564+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
28565+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
28566+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \
28567+} while (0)
28568+
28569+/* cmd, param, offset, width, type, arg_name */
28570+#define DPSW_CMD_SET_IRQ_ENABLE(cmd, irq_index, enable_state) \
28571+do { \
28572+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, enable_state); \
28573+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
28574+} while (0)
28575+
28576+/* cmd, param, offset, width, type, arg_name */
28577+#define DPSW_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
28578+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
28579+
28580+/* cmd, param, offset, width, type, arg_name */
28581+#define DPSW_RSP_GET_IRQ_ENABLE(cmd, enable_state) \
28582+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, enable_state)
28583+
28584+/* cmd, param, offset, width, type, arg_name */
28585+#define DPSW_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
28586+do { \
28587+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
28588+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
28589+} while (0)
28590+
28591+/* cmd, param, offset, width, type, arg_name */
28592+#define DPSW_CMD_GET_IRQ_MASK(cmd, irq_index) \
28593+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
28594+
28595+/* cmd, param, offset, width, type, arg_name */
28596+#define DPSW_RSP_GET_IRQ_MASK(cmd, mask) \
28597+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
28598+
28599+/* cmd, param, offset, width, type, arg_name */
28600+#define DPSW_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
28601+do { \
28602+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
28603+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
28604+} while (0)
28605+
28606+/* cmd, param, offset, width, type, arg_name */
28607+#define DPSW_RSP_GET_IRQ_STATUS(cmd, status) \
28608+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
28609+
28610+/* cmd, param, offset, width, type, arg_name */
28611+#define DPSW_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
28612+do { \
28613+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
28614+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
28615+} while (0)
28616+
28617+/* cmd, param, offset, width, type, arg_name */
28618+#define DPSW_RSP_GET_ATTR(cmd, attr) \
28619+do { \
28620+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, attr->num_ifs);\
28621+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, attr->max_fdbs);\
28622+ MC_RSP_OP(cmd, 0, 24, 8, uint8_t, attr->num_fdbs);\
28623+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->max_vlans);\
28624+ MC_RSP_OP(cmd, 0, 48, 16, uint16_t, attr->num_vlans);\
28625+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
28626+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
28627+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, attr->max_fdb_entries);\
28628+ MC_RSP_OP(cmd, 1, 48, 16, uint16_t, attr->fdb_aging_time);\
28629+ MC_RSP_OP(cmd, 2, 0, 32, int, attr->id);\
28630+ MC_RSP_OP(cmd, 2, 32, 16, uint16_t, attr->mem_size);\
28631+ MC_RSP_OP(cmd, 2, 48, 16, uint16_t, attr->max_fdb_mc_groups);\
28632+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, attr->options);\
28633+ MC_RSP_OP(cmd, 4, 0, 8, uint8_t, attr->max_meters_per_if);\
28634+ MC_RSP_OP(cmd, 4, 8, 4, enum dpsw_component_type, \
28635+ attr->component_type);\
28636+} while (0)
28637+
28638+/* cmd, param, offset, width, type, arg_name */
28639+#define DPSW_CMD_SET_REFLECTION_IF(cmd, if_id) \
28640+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id)
28641+
28642+/* cmd, param, offset, width, type, arg_name */
28643+#define DPSW_CMD_IF_SET_FLOODING(cmd, if_id, en) \
28644+do { \
28645+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28646+ MC_CMD_OP(cmd, 0, 16, 1, int, en);\
28647+} while (0)
28648+
28649+/* cmd, param, offset, width, type, arg_name */
28650+#define DPSW_CMD_IF_SET_BROADCAST(cmd, if_id, en) \
28651+do { \
28652+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28653+ MC_CMD_OP(cmd, 0, 16, 1, int, en);\
28654+} while (0)
28655+
28656+/* cmd, param, offset, width, type, arg_name */
28657+#define DPSW_CMD_IF_SET_MULTICAST(cmd, if_id, en) \
28658+do { \
28659+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28660+ MC_CMD_OP(cmd, 0, 16, 1, int, en);\
28661+} while (0)
28662+
28663+/* cmd, param, offset, width, type, arg_name */
28664+#define DPSW_CMD_IF_SET_TCI(cmd, if_id, cfg) \
28665+do { \
28666+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28667+ MC_CMD_OP(cmd, 0, 16, 12, uint16_t, cfg->vlan_id);\
28668+ MC_CMD_OP(cmd, 0, 28, 1, uint8_t, cfg->dei);\
28669+ MC_CMD_OP(cmd, 0, 29, 3, uint8_t, cfg->pcp);\
28670+} while (0)
28671+
28672+/* cmd, param, offset, width, type, arg_name */
28673+#define DPSW_CMD_IF_GET_TCI(cmd, if_id) \
28674+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id)
28675+
28676+/* cmd, param, offset, width, type, arg_name */
28677+#define DPSW_RSP_IF_GET_TCI(cmd, cfg) \
28678+do { \
28679+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, cfg->vlan_id);\
28680+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, cfg->dei);\
28681+ MC_RSP_OP(cmd, 0, 40, 8, uint8_t, cfg->pcp);\
28682+} while (0)
28683+
28684+/* cmd, param, offset, width, type, arg_name */
28685+#define DPSW_CMD_IF_SET_STP(cmd, if_id, cfg) \
28686+do { \
28687+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28688+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->vlan_id);\
28689+ MC_CMD_OP(cmd, 0, 32, 4, enum dpsw_stp_state, cfg->state);\
28690+} while (0)
28691+
28692+/* cmd, param, offset, width, type, arg_name */
28693+#define DPSW_CMD_IF_SET_ACCEPTED_FRAMES(cmd, if_id, cfg) \
28694+do { \
28695+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28696+ MC_CMD_OP(cmd, 0, 16, 4, enum dpsw_accepted_frames, cfg->type);\
28697+ MC_CMD_OP(cmd, 0, 20, 4, enum dpsw_action, cfg->unaccept_act);\
28698+} while (0)
28699+
28700+/* cmd, param, offset, width, type, arg_name */
28701+#define DPSW_CMD_IF_SET_ACCEPT_ALL_VLAN(cmd, if_id, accept_all) \
28702+do { \
28703+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28704+ MC_CMD_OP(cmd, 0, 16, 1, int, accept_all);\
28705+} while (0)
28706+
28707+/* cmd, param, offset, width, type, arg_name */
28708+#define DPSW_CMD_IF_GET_COUNTER(cmd, if_id, type) \
28709+do { \
28710+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28711+ MC_CMD_OP(cmd, 0, 16, 5, enum dpsw_counter, type);\
28712+} while (0)
28713+
28714+/* cmd, param, offset, width, type, arg_name */
28715+#define DPSW_RSP_IF_GET_COUNTER(cmd, counter) \
28716+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter)
28717+
28718+/* cmd, param, offset, width, type, arg_name */
28719+#define DPSW_CMD_IF_SET_COUNTER(cmd, if_id, type, counter) \
28720+do { \
28721+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28722+ MC_CMD_OP(cmd, 0, 16, 5, enum dpsw_counter, type);\
28723+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, counter);\
28724+} while (0)
28725+
28726+/* cmd, param, offset, width, type, arg_name */
28727+#define DPSW_CMD_IF_SET_TX_SELECTION(cmd, if_id, cfg) \
28728+do { \
28729+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28730+ MC_CMD_OP(cmd, 0, 16, 3, enum dpsw_priority_selector, \
28731+ cfg->priority_selector);\
28732+ MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->tc_id[0]);\
28733+ MC_CMD_OP(cmd, 1, 8, 8, uint8_t, cfg->tc_id[1]);\
28734+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->tc_id[2]);\
28735+ MC_CMD_OP(cmd, 1, 24, 8, uint8_t, cfg->tc_id[3]);\
28736+ MC_CMD_OP(cmd, 1, 32, 8, uint8_t, cfg->tc_id[4]);\
28737+ MC_CMD_OP(cmd, 1, 40, 8, uint8_t, cfg->tc_id[5]);\
28738+ MC_CMD_OP(cmd, 1, 48, 8, uint8_t, cfg->tc_id[6]);\
28739+ MC_CMD_OP(cmd, 1, 56, 8, uint8_t, cfg->tc_id[7]);\
28740+ MC_CMD_OP(cmd, 2, 0, 16, uint16_t, cfg->tc_sched[0].delta_bandwidth);\
28741+ MC_CMD_OP(cmd, 2, 16, 4, enum dpsw_schedule_mode, \
28742+ cfg->tc_sched[0].mode);\
28743+ MC_CMD_OP(cmd, 2, 32, 16, uint16_t, cfg->tc_sched[1].delta_bandwidth);\
28744+ MC_CMD_OP(cmd, 2, 48, 4, enum dpsw_schedule_mode, \
28745+ cfg->tc_sched[1].mode);\
28746+ MC_CMD_OP(cmd, 3, 0, 16, uint16_t, cfg->tc_sched[2].delta_bandwidth);\
28747+ MC_CMD_OP(cmd, 3, 16, 4, enum dpsw_schedule_mode, \
28748+ cfg->tc_sched[2].mode);\
28749+ MC_CMD_OP(cmd, 3, 32, 16, uint16_t, cfg->tc_sched[3].delta_bandwidth);\
28750+ MC_CMD_OP(cmd, 3, 48, 4, enum dpsw_schedule_mode, \
28751+ cfg->tc_sched[3].mode);\
28752+ MC_CMD_OP(cmd, 4, 0, 16, uint16_t, cfg->tc_sched[4].delta_bandwidth);\
28753+ MC_CMD_OP(cmd, 4, 16, 4, enum dpsw_schedule_mode, \
28754+ cfg->tc_sched[4].mode);\
28755+ MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->tc_sched[5].delta_bandwidth);\
28756+ MC_CMD_OP(cmd, 4, 48, 4, enum dpsw_schedule_mode, \
28757+ cfg->tc_sched[5].mode);\
28758+ MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->tc_sched[6].delta_bandwidth);\
28759+ MC_CMD_OP(cmd, 5, 16, 4, enum dpsw_schedule_mode, \
28760+ cfg->tc_sched[6].mode);\
28761+ MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->tc_sched[7].delta_bandwidth);\
28762+ MC_CMD_OP(cmd, 5, 48, 4, enum dpsw_schedule_mode, \
28763+ cfg->tc_sched[7].mode);\
28764+} while (0)
28765+
28766+/* cmd, param, offset, width, type, arg_name */
28767+#define DPSW_CMD_IF_ADD_REFLECTION(cmd, if_id, cfg) \
28768+do { \
28769+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28770+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->vlan_id);\
28771+ MC_CMD_OP(cmd, 0, 32, 2, enum dpsw_reflection_filter, cfg->filter);\
28772+} while (0)
28773+
28774+/* cmd, param, offset, width, type, arg_name */
28775+#define DPSW_CMD_IF_REMOVE_REFLECTION(cmd, if_id, cfg) \
28776+do { \
28777+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28778+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->vlan_id);\
28779+ MC_CMD_OP(cmd, 0, 32, 2, enum dpsw_reflection_filter, cfg->filter);\
28780+} while (0)
28781+
28782+/* cmd, param, offset, width, type, arg_name */
28783+#define DPSW_CMD_IF_SET_FLOODING_METERING(cmd, if_id, cfg) \
28784+do { \
28785+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28786+ MC_CMD_OP(cmd, 0, 24, 4, enum dpsw_metering_mode, cfg->mode);\
28787+ MC_CMD_OP(cmd, 0, 28, 4, enum dpsw_metering_unit, cfg->units);\
28788+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, cfg->cir);\
28789+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->eir);\
28790+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->cbs);\
28791+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->ebs);\
28792+} while (0)
28793+
28794+/* cmd, param, offset, width, type, arg_name */
28795+#define DPSW_CMD_IF_SET_METERING(cmd, if_id, tc_id, cfg) \
28796+do { \
28797+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28798+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id);\
28799+ MC_CMD_OP(cmd, 0, 24, 4, enum dpsw_metering_mode, cfg->mode);\
28800+ MC_CMD_OP(cmd, 0, 28, 4, enum dpsw_metering_unit, cfg->units);\
28801+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, cfg->cir);\
28802+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->eir);\
28803+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->cbs);\
28804+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->ebs);\
28805+} while (0)
28806+
28807+/* cmd, param, offset, width, type, arg_name */
28808+#define DPSW_PREP_EARLY_DROP(ext, cfg) \
28809+do { \
28810+ MC_PREP_OP(ext, 0, 0, 2, enum dpsw_early_drop_mode, cfg->drop_mode); \
28811+ MC_PREP_OP(ext, 0, 2, 2, \
28812+ enum dpsw_early_drop_unit, cfg->units); \
28813+ MC_PREP_OP(ext, 0, 32, 32, uint32_t, cfg->tail_drop_threshold); \
28814+ MC_PREP_OP(ext, 1, 0, 8, uint8_t, cfg->green.drop_probability); \
28815+ MC_PREP_OP(ext, 2, 0, 64, uint64_t, cfg->green.max_threshold); \
28816+ MC_PREP_OP(ext, 3, 0, 64, uint64_t, cfg->green.min_threshold); \
28817+ MC_PREP_OP(ext, 5, 0, 8, uint8_t, cfg->yellow.drop_probability);\
28818+ MC_PREP_OP(ext, 6, 0, 64, uint64_t, cfg->yellow.max_threshold); \
28819+ MC_PREP_OP(ext, 7, 0, 64, uint64_t, cfg->yellow.min_threshold); \
28820+} while (0)
28821+
28822+/* cmd, param, offset, width, type, arg_name */
28823+#define DPSW_EXT_EARLY_DROP(ext, cfg) \
28824+do { \
28825+ MC_EXT_OP(ext, 0, 0, 2, enum dpsw_early_drop_mode, cfg->drop_mode); \
28826+ MC_EXT_OP(ext, 0, 2, 2, \
28827+ enum dpsw_early_drop_unit, cfg->units); \
28828+ MC_EXT_OP(ext, 0, 32, 32, uint32_t, cfg->tail_drop_threshold); \
28829+ MC_EXT_OP(ext, 1, 0, 8, uint8_t, cfg->green.drop_probability); \
28830+ MC_EXT_OP(ext, 2, 0, 64, uint64_t, cfg->green.max_threshold); \
28831+ MC_EXT_OP(ext, 3, 0, 64, uint64_t, cfg->green.min_threshold); \
28832+ MC_EXT_OP(ext, 5, 0, 8, uint8_t, cfg->yellow.drop_probability);\
28833+ MC_EXT_OP(ext, 6, 0, 64, uint64_t, cfg->yellow.max_threshold); \
28834+ MC_EXT_OP(ext, 7, 0, 64, uint64_t, cfg->yellow.min_threshold); \
28835+} while (0)
28836+
28837+/* cmd, param, offset, width, type, arg_name */
28838+#define DPSW_CMD_IF_SET_EARLY_DROP(cmd, if_id, tc_id, early_drop_iova) \
28839+do { \
28840+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \
28841+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, if_id); \
28842+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, early_drop_iova); \
28843+} while (0)
28844+
28845+/* cmd, param, offset, width, type, arg_name */
28846+#define DPSW_CMD_ADD_CUSTOM_TPID(cmd, cfg) \
28847+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->tpid)
28848+
28849+/* cmd, param, offset, width, type, arg_name */
28850+#define DPSW_CMD_REMOVE_CUSTOM_TPID(cmd, cfg) \
28851+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->tpid)
28852+
28853+/* cmd, param, offset, width, type, arg_name */
28854+#define DPSW_CMD_IF_ENABLE(cmd, if_id) \
28855+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id)
28856+
28857+/* cmd, param, offset, width, type, arg_name */
28858+#define DPSW_CMD_IF_DISABLE(cmd, if_id) \
28859+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id)
28860+
28861+/* cmd, param, offset, width, type, arg_name */
28862+#define DPSW_CMD_IF_GET_ATTR(cmd, if_id) \
28863+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id)
28864+
28865+/* cmd, param, offset, width, type, arg_name */
28866+#define DPSW_RSP_IF_GET_ATTR(cmd, attr) \
28867+do { \
28868+ MC_RSP_OP(cmd, 0, 0, 4, enum dpsw_accepted_frames, \
28869+ attr->admit_untagged);\
28870+ MC_RSP_OP(cmd, 0, 5, 1, int, attr->enabled);\
28871+ MC_RSP_OP(cmd, 0, 6, 1, int, attr->accept_all_vlan);\
28872+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, attr->num_tcs);\
28873+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qdid);\
28874+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options);\
28875+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->rate);\
28876+} while (0)
28877+
28878+/* cmd, param, offset, width, type, arg_name */
28879+#define DPSW_CMD_IF_SET_MAX_FRAME_LENGTH(cmd, if_id, frame_length) \
28880+do { \
28881+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28882+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, frame_length);\
28883+} while (0)
28884+
28885+/* cmd, param, offset, width, type, arg_name */
28886+#define DPSW_CMD_IF_GET_MAX_FRAME_LENGTH(cmd, if_id) \
28887+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id)
28888+
28889+/* cmd, param, offset, width, type, arg_name */
28890+#define DPSW_RSP_IF_GET_MAX_FRAME_LENGTH(cmd, frame_length) \
28891+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, frame_length)
28892+
28893+/* cmd, param, offset, width, type, arg_name */
28894+#define DPSW_CMD_IF_SET_LINK_CFG(cmd, if_id, cfg) \
28895+do { \
28896+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\
28897+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate);\
28898+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options);\
28899+} while (0)
28900+
28901+/* cmd, param, offset, width, type, arg_name */
28902+#define DPSW_CMD_IF_GET_LINK_STATE(cmd, if_id) \
28903+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id)
28904+
28905+/* cmd, param, offset, width, type, arg_name */
28906+#define DPSW_RSP_IF_GET_LINK_STATE(cmd, state) \
28907+do { \
28908+ MC_RSP_OP(cmd, 0, 32, 1, int, state->up);\
28909+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, state->rate);\
28910+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\
28911+} while (0)
28912+
28913+/* cmd, param, offset, width, type, arg_name */
28914+#define DPSW_CMD_VLAN_ADD(cmd, vlan_id, cfg) \
28915+do { \
28916+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->fdb_id);\
28917+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id);\
28918+} while (0)
28919+
28920+/* cmd, param, offset, width, type, arg_name */
28921+#define DPSW_CMD_VLAN_ADD_IF(cmd, vlan_id) \
28922+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id)
28923+
28924+/* cmd, param, offset, width, type, arg_name */
28925+#define DPSW_CMD_VLAN_ADD_IF_UNTAGGED(cmd, vlan_id) \
28926+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id)
28927+
28928+/* cmd, param, offset, width, type, arg_name */
28929+#define DPSW_CMD_VLAN_ADD_IF_FLOODING(cmd, vlan_id) \
28930+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id)
28931+
28932+#define DPSW_CMD_VLAN_REMOVE_IF(cmd, vlan_id) \
28933+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id)
28934+
28935+/* cmd, param, offset, width, type, arg_name */
28936+#define DPSW_CMD_VLAN_REMOVE_IF_UNTAGGED(cmd, vlan_id) \
28937+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id)
28938+
28939+/* cmd, param, offset, width, type, arg_name */
28940+#define DPSW_CMD_VLAN_REMOVE_IF_FLOODING(cmd, vlan_id) \
28941+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id)
28942+
28943+/* cmd, param, offset, width, type, arg_name */
28944+#define DPSW_CMD_VLAN_REMOVE(cmd, vlan_id) \
28945+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id)
28946+
28947+/* cmd, param, offset, width, type, arg_name */
28948+#define DPSW_CMD_VLAN_GET_ATTR(cmd, vlan_id) \
28949+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, vlan_id)
28950+
28951+/* cmd, param, offset, width, type, arg_name */
28952+#define DPSW_RSP_VLAN_GET_ATTR(cmd, attr) \
28953+do { \
28954+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->fdb_id); \
28955+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->num_ifs); \
28956+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, attr->num_untagged_ifs); \
28957+ MC_RSP_OP(cmd, 1, 48, 16, uint16_t, attr->num_flooding_ifs); \
28958+} while (0)
28959+
28960+/* cmd, param, offset, width, type, arg_name */
28961+#define DPSW_CMD_VLAN_GET_IF(cmd, vlan_id) \
28962+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, vlan_id)
28963+
28964+/* cmd, param, offset, width, type, arg_name */
28965+#define DPSW_RSP_VLAN_GET_IF(cmd, cfg) \
28966+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs)
28967+
28968+/* cmd, param, offset, width, type, arg_name */
28969+#define DPSW_CMD_VLAN_GET_IF_FLOODING(cmd, vlan_id) \
28970+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, vlan_id)
28971+
28972+/* cmd, param, offset, width, type, arg_name */
28973+#define DPSW_RSP_VLAN_GET_IF_FLOODING(cmd, cfg) \
28974+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs)
28975+
28976+/* cmd, param, offset, width, type, arg_name */
28977+#define DPSW_CMD_VLAN_GET_IF_UNTAGGED(cmd, vlan_id) \
28978+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, vlan_id)
28979+
28980+/* cmd, param, offset, width, type, arg_name */
28981+#define DPSW_RSP_VLAN_GET_IF_UNTAGGED(cmd, cfg) \
28982+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs)
28983+
28984+/* param, offset, width, type, arg_name */
28985+#define DPSW_CMD_FDB_ADD(cmd, cfg) \
28986+do { \
28987+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->fdb_aging_time);\
28988+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, cfg->num_fdb_entries);\
28989+} while (0)
28990+
28991+/* cmd, param, offset, width, type, arg_name */
28992+#define DPSW_RSP_FDB_ADD(cmd, fdb_id) \
28993+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, fdb_id)
28994+
28995+/* cmd, param, offset, width, type, arg_name */
28996+#define DPSW_CMD_FDB_REMOVE(cmd, fdb_id) \
28997+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id)
28998+
28999+/* cmd, param, offset, width, type, arg_name */
29000+#define DPSW_CMD_FDB_ADD_UNICAST(cmd, fdb_id, cfg) \
29001+do { \
29002+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\
29003+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]);\
29004+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]);\
29005+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]);\
29006+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]);\
29007+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]);\
29008+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]);\
29009+ MC_CMD_OP(cmd, 1, 0, 8, uint16_t, cfg->if_egress);\
29010+ MC_CMD_OP(cmd, 1, 16, 4, enum dpsw_fdb_entry_type, cfg->type);\
29011+} while (0)
29012+
29013+/* cmd, param, offset, width, type, arg_name */
29014+#define DPSW_CMD_FDB_GET_UNICAST(cmd, fdb_id) \
29015+do { \
29016+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\
29017+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]);\
29018+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]);\
29019+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]);\
29020+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]);\
29021+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]);\
29022+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]);\
29023+} while (0)
29024+
29025+/* cmd, param, offset, width, type, arg_name */
29026+#define DPSW_RSP_FDB_GET_UNICAST(cmd, cfg) \
29027+do { \
29028+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, cfg->if_egress);\
29029+ MC_RSP_OP(cmd, 1, 16, 4, enum dpsw_fdb_entry_type, cfg->type);\
29030+} while (0)
29031+
29032+/* cmd, param, offset, width, type, arg_name */
29033+#define DPSW_CMD_FDB_REMOVE_UNICAST(cmd, fdb_id, cfg) \
29034+do { \
29035+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\
29036+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]);\
29037+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]);\
29038+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]);\
29039+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]);\
29040+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]);\
29041+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]);\
29042+ MC_CMD_OP(cmd, 1, 0, 16, uint16_t, cfg->if_egress);\
29043+ MC_CMD_OP(cmd, 1, 16, 4, enum dpsw_fdb_entry_type, cfg->type);\
29044+} while (0)
29045+
29046+/* cmd, param, offset, width, type, arg_name */
29047+#define DPSW_CMD_FDB_ADD_MULTICAST(cmd, fdb_id, cfg) \
29048+do { \
29049+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\
29050+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs);\
29051+ MC_CMD_OP(cmd, 0, 32, 4, enum dpsw_fdb_entry_type, cfg->type);\
29052+ MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->mac_addr[5]);\
29053+ MC_CMD_OP(cmd, 1, 8, 8, uint8_t, cfg->mac_addr[4]);\
29054+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->mac_addr[3]);\
29055+ MC_CMD_OP(cmd, 1, 24, 8, uint8_t, cfg->mac_addr[2]);\
29056+ MC_CMD_OP(cmd, 1, 32, 8, uint8_t, cfg->mac_addr[1]);\
29057+ MC_CMD_OP(cmd, 1, 40, 8, uint8_t, cfg->mac_addr[0]);\
29058+} while (0)
29059+
29060+/* cmd, param, offset, width, type, arg_name */
29061+#define DPSW_CMD_FDB_GET_MULTICAST(cmd, fdb_id) \
29062+do { \
29063+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\
29064+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]);\
29065+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]);\
29066+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]);\
29067+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]);\
29068+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]);\
29069+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]);\
29070+} while (0)
29071+
29072+/* cmd, param, offset, width, type, arg_name */
29073+#define DPSW_RSP_FDB_GET_MULTICAST(cmd, cfg) \
29074+do { \
29075+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, cfg->num_ifs);\
29076+ MC_RSP_OP(cmd, 1, 16, 4, enum dpsw_fdb_entry_type, cfg->type);\
29077+} while (0)
29078+
29079+/* cmd, param, offset, width, type, arg_name */
29080+#define DPSW_CMD_FDB_REMOVE_MULTICAST(cmd, fdb_id, cfg) \
29081+do { \
29082+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\
29083+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs);\
29084+ MC_CMD_OP(cmd, 0, 32, 4, enum dpsw_fdb_entry_type, cfg->type);\
29085+ MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->mac_addr[5]);\
29086+ MC_CMD_OP(cmd, 1, 8, 8, uint8_t, cfg->mac_addr[4]);\
29087+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->mac_addr[3]);\
29088+ MC_CMD_OP(cmd, 1, 24, 8, uint8_t, cfg->mac_addr[2]);\
29089+ MC_CMD_OP(cmd, 1, 32, 8, uint8_t, cfg->mac_addr[1]);\
29090+ MC_CMD_OP(cmd, 1, 40, 8, uint8_t, cfg->mac_addr[0]);\
29091+} while (0)
29092+
29093+/* cmd, param, offset, width, type, arg_name */
29094+#define DPSW_CMD_FDB_SET_LEARNING_MODE(cmd, fdb_id, mode) \
29095+do { \
29096+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\
29097+ MC_CMD_OP(cmd, 0, 16, 4, enum dpsw_fdb_learning_mode, mode);\
29098+} while (0)
29099+
29100+/* cmd, param, offset, width, type, arg_name */
29101+#define DPSW_CMD_FDB_GET_ATTR(cmd, fdb_id) \
29102+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id)
29103+
29104+/* cmd, param, offset, width, type, arg_name */
29105+#define DPSW_RSP_FDB_GET_ATTR(cmd, attr) \
29106+do { \
29107+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->max_fdb_entries);\
29108+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->fdb_aging_time);\
29109+ MC_RSP_OP(cmd, 0, 48, 16, uint16_t, attr->num_fdb_mc_groups);\
29110+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->max_fdb_mc_groups);\
29111+ MC_RSP_OP(cmd, 1, 16, 4, enum dpsw_fdb_learning_mode, \
29112+ attr->learning_mode);\
29113+} while (0)
29114+
29115+/* cmd, param, offset, width, type, arg_name */
29116+#define DPSW_CMD_ACL_ADD(cmd, cfg) \
29117+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->max_entries)
29118+
29119+/* cmd, param, offset, width, type, arg_name */
29120+#define DPSW_RSP_ACL_ADD(cmd, acl_id) \
29121+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, acl_id)
29122+
29123+/* cmd, param, offset, width, type, arg_name */
29124+#define DPSW_CMD_ACL_REMOVE(cmd, acl_id) \
29125+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, acl_id)
29126+
29127+/* cmd, param, offset, width, type, arg_name */
29128+#define DPSW_PREP_ACL_ENTRY(ext, key) \
29129+do { \
29130+ MC_PREP_OP(ext, 0, 0, 8, uint8_t, key->match.l2_dest_mac[5]);\
29131+ MC_PREP_OP(ext, 0, 8, 8, uint8_t, key->match.l2_dest_mac[4]);\
29132+ MC_PREP_OP(ext, 0, 16, 8, uint8_t, key->match.l2_dest_mac[3]);\
29133+ MC_PREP_OP(ext, 0, 24, 8, uint8_t, key->match.l2_dest_mac[2]);\
29134+ MC_PREP_OP(ext, 0, 32, 8, uint8_t, key->match.l2_dest_mac[1]);\
29135+ MC_PREP_OP(ext, 0, 40, 8, uint8_t, key->match.l2_dest_mac[0]);\
29136+ MC_PREP_OP(ext, 0, 48, 16, uint16_t, key->match.l2_tpid);\
29137+ MC_PREP_OP(ext, 1, 0, 8, uint8_t, key->match.l2_source_mac[5]);\
29138+ MC_PREP_OP(ext, 1, 8, 8, uint8_t, key->match.l2_source_mac[4]);\
29139+ MC_PREP_OP(ext, 1, 16, 8, uint8_t, key->match.l2_source_mac[3]);\
29140+ MC_PREP_OP(ext, 1, 24, 8, uint8_t, key->match.l2_source_mac[2]);\
29141+ MC_PREP_OP(ext, 1, 32, 8, uint8_t, key->match.l2_source_mac[1]);\
29142+ MC_PREP_OP(ext, 1, 40, 8, uint8_t, key->match.l2_source_mac[0]);\
29143+ MC_PREP_OP(ext, 1, 48, 16, uint16_t, key->match.l2_vlan_id);\
29144+ MC_PREP_OP(ext, 2, 0, 32, uint32_t, key->match.l3_dest_ip);\
29145+ MC_PREP_OP(ext, 2, 32, 32, uint32_t, key->match.l3_source_ip);\
29146+ MC_PREP_OP(ext, 3, 0, 16, uint16_t, key->match.l4_dest_port);\
29147+ MC_PREP_OP(ext, 3, 16, 16, uint16_t, key->match.l4_source_port);\
29148+ MC_PREP_OP(ext, 3, 32, 16, uint16_t, key->match.l2_ether_type);\
29149+ MC_PREP_OP(ext, 3, 48, 8, uint8_t, key->match.l2_pcp_dei);\
29150+ MC_PREP_OP(ext, 3, 56, 8, uint8_t, key->match.l3_dscp);\
29151+ MC_PREP_OP(ext, 4, 0, 8, uint8_t, key->mask.l2_dest_mac[5]);\
29152+ MC_PREP_OP(ext, 4, 8, 8, uint8_t, key->mask.l2_dest_mac[4]);\
29153+ MC_PREP_OP(ext, 4, 16, 8, uint8_t, key->mask.l2_dest_mac[3]);\
29154+ MC_PREP_OP(ext, 4, 24, 8, uint8_t, key->mask.l2_dest_mac[2]);\
29155+ MC_PREP_OP(ext, 4, 32, 8, uint8_t, key->mask.l2_dest_mac[1]);\
29156+ MC_PREP_OP(ext, 4, 40, 8, uint8_t, key->mask.l2_dest_mac[0]);\
29157+ MC_PREP_OP(ext, 4, 48, 16, uint16_t, key->mask.l2_tpid);\
29158+ MC_PREP_OP(ext, 5, 0, 8, uint8_t, key->mask.l2_source_mac[5]);\
29159+ MC_PREP_OP(ext, 5, 8, 8, uint8_t, key->mask.l2_source_mac[4]);\
29160+ MC_PREP_OP(ext, 5, 16, 8, uint8_t, key->mask.l2_source_mac[3]);\
29161+ MC_PREP_OP(ext, 5, 24, 8, uint8_t, key->mask.l2_source_mac[2]);\
29162+ MC_PREP_OP(ext, 5, 32, 8, uint8_t, key->mask.l2_source_mac[1]);\
29163+ MC_PREP_OP(ext, 5, 40, 8, uint8_t, key->mask.l2_source_mac[0]);\
29164+ MC_PREP_OP(ext, 5, 48, 16, uint16_t, key->mask.l2_vlan_id);\
29165+ MC_PREP_OP(ext, 6, 0, 32, uint32_t, key->mask.l3_dest_ip);\
29166+ MC_PREP_OP(ext, 6, 32, 32, uint32_t, key->mask.l3_source_ip);\
29167+ MC_PREP_OP(ext, 7, 0, 16, uint16_t, key->mask.l4_dest_port);\
29168+ MC_PREP_OP(ext, 7, 16, 16, uint16_t, key->mask.l4_source_port);\
29169+ MC_PREP_OP(ext, 7, 32, 16, uint16_t, key->mask.l2_ether_type);\
29170+ MC_PREP_OP(ext, 7, 48, 8, uint8_t, key->mask.l2_pcp_dei);\
29171+ MC_PREP_OP(ext, 7, 56, 8, uint8_t, key->mask.l3_dscp);\
29172+ MC_PREP_OP(ext, 8, 0, 8, uint8_t, key->match.l3_protocol);\
29173+ MC_PREP_OP(ext, 8, 8, 8, uint8_t, key->mask.l3_protocol);\
29174+} while (0)
29175+
29176+/* cmd, param, offset, width, type, arg_name */
29177+#define DPSW_EXT_ACL_ENTRY(ext, key) \
29178+do { \
29179+ MC_EXT_OP(ext, 0, 0, 8, uint8_t, key->match.l2_dest_mac[5]);\
29180+ MC_EXT_OP(ext, 0, 8, 8, uint8_t, key->match.l2_dest_mac[4]);\
29181+ MC_EXT_OP(ext, 0, 16, 8, uint8_t, key->match.l2_dest_mac[3]);\
29182+ MC_EXT_OP(ext, 0, 24, 8, uint8_t, key->match.l2_dest_mac[2]);\
29183+ MC_EXT_OP(ext, 0, 32, 8, uint8_t, key->match.l2_dest_mac[1]);\
29184+ MC_EXT_OP(ext, 0, 40, 8, uint8_t, key->match.l2_dest_mac[0]);\
29185+ MC_EXT_OP(ext, 0, 48, 16, uint16_t, key->match.l2_tpid);\
29186+ MC_EXT_OP(ext, 1, 0, 8, uint8_t, key->match.l2_source_mac[5]);\
29187+ MC_EXT_OP(ext, 1, 8, 8, uint8_t, key->match.l2_source_mac[4]);\
29188+ MC_EXT_OP(ext, 1, 16, 8, uint8_t, key->match.l2_source_mac[3]);\
29189+ MC_EXT_OP(ext, 1, 24, 8, uint8_t, key->match.l2_source_mac[2]);\
29190+ MC_EXT_OP(ext, 1, 32, 8, uint8_t, key->match.l2_source_mac[1]);\
29191+ MC_EXT_OP(ext, 1, 40, 8, uint8_t, key->match.l2_source_mac[0]);\
29192+ MC_EXT_OP(ext, 1, 48, 16, uint16_t, key->match.l2_vlan_id);\
29193+ MC_EXT_OP(ext, 2, 0, 32, uint32_t, key->match.l3_dest_ip);\
29194+ MC_EXT_OP(ext, 2, 32, 32, uint32_t, key->match.l3_source_ip);\
29195+ MC_EXT_OP(ext, 3, 0, 16, uint16_t, key->match.l4_dest_port);\
29196+ MC_EXT_OP(ext, 3, 16, 16, uint16_t, key->match.l4_source_port);\
29197+ MC_EXT_OP(ext, 3, 32, 16, uint16_t, key->match.l2_ether_type);\
29198+ MC_EXT_OP(ext, 3, 48, 8, uint8_t, key->match.l2_pcp_dei);\
29199+ MC_EXT_OP(ext, 3, 56, 8, uint8_t, key->match.l3_dscp);\
29200+ MC_EXT_OP(ext, 4, 0, 8, uint8_t, key->mask.l2_dest_mac[5]);\
29201+ MC_EXT_OP(ext, 4, 8, 8, uint8_t, key->mask.l2_dest_mac[4]);\
29202+ MC_EXT_OP(ext, 4, 16, 8, uint8_t, key->mask.l2_dest_mac[3]);\
29203+ MC_EXT_OP(ext, 4, 24, 8, uint8_t, key->mask.l2_dest_mac[2]);\
29204+ MC_EXT_OP(ext, 4, 32, 8, uint8_t, key->mask.l2_dest_mac[1]);\
29205+ MC_EXT_OP(ext, 4, 40, 8, uint8_t, key->mask.l2_dest_mac[0]);\
29206+ MC_EXT_OP(ext, 4, 48, 16, uint16_t, key->mask.l2_tpid);\
29207+ MC_EXT_OP(ext, 5, 0, 8, uint8_t, key->mask.l2_source_mac[5]);\
29208+ MC_EXT_OP(ext, 5, 8, 8, uint8_t, key->mask.l2_source_mac[4]);\
29209+ MC_EXT_OP(ext, 5, 16, 8, uint8_t, key->mask.l2_source_mac[3]);\
29210+ MC_EXT_OP(ext, 5, 24, 8, uint8_t, key->mask.l2_source_mac[2]);\
29211+ MC_EXT_OP(ext, 5, 32, 8, uint8_t, key->mask.l2_source_mac[1]);\
29212+ MC_EXT_OP(ext, 5, 40, 8, uint8_t, key->mask.l2_source_mac[0]);\
29213+ MC_EXT_OP(ext, 5, 48, 16, uint16_t, key->mask.l2_vlan_id);\
29214+ MC_EXT_OP(ext, 6, 0, 32, uint32_t, key->mask.l3_dest_ip);\
29215+ MC_EXT_OP(ext, 6, 32, 32, uint32_t, key->mask.l3_source_ip);\
29216+ MC_EXT_OP(ext, 7, 0, 16, uint16_t, key->mask.l4_dest_port);\
29217+ MC_EXT_OP(ext, 7, 16, 16, uint16_t, key->mask.l4_source_port);\
29218+ MC_EXT_OP(ext, 7, 32, 16, uint16_t, key->mask.l2_ether_type);\
29219+ MC_EXT_OP(ext, 7, 48, 8, uint8_t, key->mask.l2_pcp_dei);\
29220+ MC_EXT_OP(ext, 7, 56, 8, uint8_t, key->mask.l3_dscp);\
29221+ MC_EXT_OP(ext, 8, 0, 8, uint8_t, key->match.l3_protocol);\
29222+ MC_EXT_OP(ext, 8, 8, 8, uint8_t, key->mask.l3_protocol);\
29223+} while (0)
29224+
29225+/* cmd, param, offset, width, type, arg_name */
29226+#define DPSW_CMD_ACL_ADD_ENTRY(cmd, acl_id, cfg) \
29227+do { \
29228+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, acl_id);\
29229+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->result.if_id);\
29230+ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->precedence);\
29231+ MC_CMD_OP(cmd, 1, 0, 4, enum dpsw_acl_action, cfg->result.action);\
29232+ MC_CMD_OP(cmd, 6, 0, 64, uint64_t, cfg->key_iova); \
29233+} while (0)
29234+
29235+/* cmd, param, offset, width, type, arg_name */
29236+#define DPSW_CMD_ACL_REMOVE_ENTRY(cmd, acl_id, cfg) \
29237+do { \
29238+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, acl_id);\
29239+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->result.if_id);\
29240+ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->precedence);\
29241+ MC_CMD_OP(cmd, 1, 0, 4, enum dpsw_acl_action, cfg->result.action);\
29242+ MC_CMD_OP(cmd, 6, 0, 64, uint64_t, cfg->key_iova); \
29243+} while (0)
29244+
29245+/* cmd, param, offset, width, type, arg_name */
29246+#define DPSW_CMD_ACL_ADD_IF(cmd, acl_id, cfg) \
29247+do { \
29248+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, acl_id);\
29249+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs); \
29250+} while (0)
29251+
29252+/* cmd, param, offset, width, type, arg_name */
29253+#define DPSW_CMD_ACL_REMOVE_IF(cmd, acl_id, cfg) \
29254+do { \
29255+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, acl_id);\
29256+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs); \
29257+} while (0)
29258+
29259+/* cmd, param, offset, width, type, arg_name */
29260+#define DPSW_CMD_ACL_GET_ATTR(cmd, acl_id) \
29261+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, acl_id)
29262+
29263+/* cmd, param, offset, width, type, arg_name */
29264+#define DPSW_RSP_ACL_GET_ATTR(cmd, attr) \
29265+do { \
29266+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->max_entries);\
29267+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->num_entries);\
29268+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, attr->num_ifs);\
29269+} while (0)
29270+
29271+/* cmd, param, offset, width, type, arg_name */
29272+#define DPSW_RSP_CTRL_IF_GET_ATTR(cmd, attr) \
29273+do { \
29274+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->rx_fqid);\
29275+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, attr->rx_err_fqid);\
29276+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tx_err_conf_fqid);\
29277+} while (0)
29278+
29279+/* cmd, param, offset, width, type, arg_name */
29280+#define DPSW_CMD_CTRL_IF_SET_POOLS(cmd, cfg) \
29281+do { \
29282+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \
29283+ MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \
29284+ MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \
29285+ MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \
29286+ MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \
29287+ MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \
29288+ MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \
29289+ MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \
29290+ MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \
29291+ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \
29292+ MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\
29293+ MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \
29294+ MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\
29295+ MC_CMD_OP(cmd, 1, 32, 32, int, cfg->pools[2].dpbp_id); \
29296+ MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->pools[2].buffer_size);\
29297+ MC_CMD_OP(cmd, 2, 0, 32, int, cfg->pools[3].dpbp_id); \
29298+ MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\
29299+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->pools[4].dpbp_id); \
29300+ MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\
29301+ MC_CMD_OP(cmd, 3, 0, 32, int, cfg->pools[5].dpbp_id); \
29302+ MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\
29303+ MC_CMD_OP(cmd, 3, 32, 32, int, cfg->pools[6].dpbp_id); \
29304+ MC_CMD_OP(cmd, 6, 0, 16, uint16_t, cfg->pools[6].buffer_size);\
29305+ MC_CMD_OP(cmd, 4, 0, 32, int, cfg->pools[7].dpbp_id); \
29306+ MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\
29307+} while (0)
29308+
29309+#endif /* __FSL_DPSW_CMD_H */
29310diff --git a/drivers/net/dpaa2/mc/fsl_mc_cmd.h b/drivers/net/dpaa2/mc/fsl_mc_cmd.h
29311new file mode 100644
29312index 0000000..ac4f2b4
29313--- /dev/null
29314+++ b/drivers/net/dpaa2/mc/fsl_mc_cmd.h
29315@@ -0,0 +1,221 @@
29316+/* Copyright 2013-2015 Freescale Semiconductor Inc.
29317+ *
29318+ * Redistribution and use in source and binary forms, with or without
29319+ * modification, are permitted provided that the following conditions are met:
29320+ * * Redistributions of source code must retain the above copyright
29321+ * notice, this list of conditions and the following disclaimer.
29322+ * * Redistributions in binary form must reproduce the above copyright
29323+ * notice, this list of conditions and the following disclaimer in the
29324+ * documentation and/or other materials provided with the distribution.
29325+ * * Neither the name of the above-listed copyright holders nor the
29326+ * names of any contributors may be used to endorse or promote products
29327+ * derived from this software without specific prior written permission.
29328+ *
29329+ *
29330+ * ALTERNATIVELY, this software may be distributed under the terms of the
29331+ * GNU General Public License ("GPL") as published by the Free Software
29332+ * Foundation, either version 2 of that License or (at your option) any
29333+ * later version.
29334+ *
29335+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29336+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29337+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29338+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
29339+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29340+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29341+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29342+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29343+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29344+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29345+ * POSSIBILITY OF SUCH DAMAGE.
29346+ */
29347+#ifndef __FSL_MC_CMD_H
29348+#define __FSL_MC_CMD_H
29349+
29350+#define MC_CMD_NUM_OF_PARAMS 7
29351+
29352+#define MAKE_UMASK64(_width) \
29353+ ((uint64_t)((_width) < 64 ? ((uint64_t)1 << (_width)) - 1 :\
29354+ (uint64_t)-1))
29355+static inline uint64_t mc_enc(int lsoffset, int width, uint64_t val)
29356+{
29357+ return (uint64_t)(((uint64_t)val & MAKE_UMASK64(width)) << lsoffset);
29358+}
29359+
29360+static inline uint64_t mc_dec(uint64_t val, int lsoffset, int width)
29361+{
29362+ return (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width));
29363+}
29364+
29365+struct mc_command {
29366+ uint64_t header;
29367+ uint64_t params[MC_CMD_NUM_OF_PARAMS];
29368+};
29369+
29370+/**
29371+ * enum mc_cmd_status - indicates MC status at command response
29372+ * @MC_CMD_STATUS_OK: Completed successfully
29373+ * @MC_CMD_STATUS_READY: Ready to be processed
29374+ * @MC_CMD_STATUS_AUTH_ERR: Authentication error
29375+ * @MC_CMD_STATUS_NO_PRIVILEGE: No privilege
29376+ * @MC_CMD_STATUS_DMA_ERR: DMA or I/O error
29377+ * @MC_CMD_STATUS_CONFIG_ERR: Configuration error
29378+ * @MC_CMD_STATUS_TIMEOUT: Operation timed out
29379+ * @MC_CMD_STATUS_NO_RESOURCE: No resources
29380+ * @MC_CMD_STATUS_NO_MEMORY: No memory available
29381+ * @MC_CMD_STATUS_BUSY: Device is busy
29382+ * @MC_CMD_STATUS_UNSUPPORTED_OP: Unsupported operation
29383+ * @MC_CMD_STATUS_INVALID_STATE: Invalid state
29384+ */
29385+enum mc_cmd_status {
29386+ MC_CMD_STATUS_OK = 0x0,
29387+ MC_CMD_STATUS_READY = 0x1,
29388+ MC_CMD_STATUS_AUTH_ERR = 0x3,
29389+ MC_CMD_STATUS_NO_PRIVILEGE = 0x4,
29390+ MC_CMD_STATUS_DMA_ERR = 0x5,
29391+ MC_CMD_STATUS_CONFIG_ERR = 0x6,
29392+ MC_CMD_STATUS_TIMEOUT = 0x7,
29393+ MC_CMD_STATUS_NO_RESOURCE = 0x8,
29394+ MC_CMD_STATUS_NO_MEMORY = 0x9,
29395+ MC_CMD_STATUS_BUSY = 0xA,
29396+ MC_CMD_STATUS_UNSUPPORTED_OP = 0xB,
29397+ MC_CMD_STATUS_INVALID_STATE = 0xC
29398+};
29399+
29400+/* MC command flags */
29401+
29402+/**
29403+ * High priority flag
29404+ */
29405+#define MC_CMD_FLAG_PRI 0x00008000
29406+/**
29407+ * Command completion flag
29408+ */
29409+#define MC_CMD_FLAG_INTR_DIS 0x01000000
29410+
29411+/**
29412+ * Command ID field offset
29413+ */
29414+#define MC_CMD_HDR_CMDID_O 52
29415+/**
29416+ * Command ID field size
29417+ */
29418+#define MC_CMD_HDR_CMDID_S 12
29419+/**
29420+ * Token field offset
29421+ */
29422+#define MC_CMD_HDR_TOKEN_O 38
29423+/**
29424+ * Token field size
29425+ */
29426+#define MC_CMD_HDR_TOKEN_S 10
29427+/**
29428+ * Status field offset
29429+ */
29430+#define MC_CMD_HDR_STATUS_O 16
29431+/**
29432+ * Status field size
29433+ */
29434+#define MC_CMD_HDR_STATUS_S 8
29435+/**
29436+ * Flags field offset
29437+ */
29438+#define MC_CMD_HDR_FLAGS_O 0
29439+/**
29440+ * Flags field size
29441+ */
29442+#define MC_CMD_HDR_FLAGS_S 32
29443+/**
29444+ * Command flags mask
29445+ */
29446+#define MC_CMD_HDR_FLAGS_MASK 0xFF00FF00
29447+
29448+#define MC_CMD_HDR_READ_STATUS(_hdr) \
29449+ ((enum mc_cmd_status)mc_dec((_hdr), \
29450+ MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S))
29451+
29452+#define MC_CMD_HDR_READ_TOKEN(_hdr) \
29453+ ((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S))
29454+
29455+#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \
29456+ ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg)))
29457+
29458+#define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \
29459+ (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width)))
29460+
29461+#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \
29462+ ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
29463+
29464+#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \
29465+ (_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width)))
29466+
29467+static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id,
29468+ uint32_t cmd_flags,
29469+ uint16_t token)
29470+{
29471+ uint64_t hdr;
29472+
29473+ hdr = mc_enc(MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S, cmd_id);
29474+ hdr |= mc_enc(MC_CMD_HDR_FLAGS_O, MC_CMD_HDR_FLAGS_S,
29475+ (cmd_flags & MC_CMD_HDR_FLAGS_MASK));
29476+ hdr |= mc_enc(MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S, token);
29477+ hdr |= mc_enc(MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S,
29478+ MC_CMD_STATUS_READY);
29479+
29480+ return hdr;
29481+}
29482+
29483+/**
29484+ * mc_write_command - writes a command to a Management Complex (MC) portal
29485+ *
29486+ * @portal: pointer to an MC portal
29487+ * @cmd: pointer to a filled command
29488+ */
29489+static inline void mc_write_command(struct mc_command __iomem *portal,
29490+ struct mc_command *cmd)
29491+{
29492+ int i;
29493+ uint32_t word;
29494+
29495+ /* copy command parameters into the portal */
29496+ for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
29497+ iowrite64(cmd->params[i], &portal->params[i]);
29498+
29499+ /* submit the command by writing the header */
29500+ word = (uint32_t)mc_dec(cmd->header, 32, 32);
29501+ iowrite32(word, (((uint32_t *)&portal->header) + 1));
29502+
29503+ word = (uint32_t)mc_dec(cmd->header, 0, 32);
29504+ iowrite32(word, (uint32_t *)&portal->header);
29505+}
29506+
29507+/**
29508+ * mc_read_response - reads the response for the last MC command from a
29509+ * Management Complex (MC) portal
29510+ *
29511+ * @portal: pointer to an MC portal
29512+ * @resp: pointer to command response buffer
29513+ *
29514+ * Returns MC_CMD_STATUS_OK on Success; Error code otherwise.
29515+ */
29516+static inline enum mc_cmd_status mc_read_response(
29517+ struct mc_command __iomem *portal,
29518+ struct mc_command *resp)
29519+{
29520+ int i;
29521+ enum mc_cmd_status status;
29522+
29523+ /* Copy command response header from MC portal: */
29524+ resp->header = ioread64(&portal->header);
29525+ status = MC_CMD_HDR_READ_STATUS(resp->header);
29526+ if (status != MC_CMD_STATUS_OK)
29527+ return status;
29528+
29529+ /* Copy command response data from MC portal: */
29530+ for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
29531+ resp->params[i] = ioread64(&portal->params[i]);
29532+
29533+ return status;
29534+}
29535+
29536+#endif /* __FSL_MC_CMD_H */
29537diff --git a/drivers/net/dpaa2/mc/fsl_mc_sys.h b/drivers/net/dpaa2/mc/fsl_mc_sys.h
29538new file mode 100644
29539index 0000000..769c129
29540--- /dev/null
29541+++ b/drivers/net/dpaa2/mc/fsl_mc_sys.h
29542@@ -0,0 +1,95 @@
29543+/* Copyright 2013-2015 Freescale Semiconductor Inc.
29544+ *
29545+ * Redistribution and use in source and binary forms, with or without
29546+ * modification, are permitted provided that the following conditions are met:
29547+ * * Redistributions of source code must retain the above copyright
29548+ * notice, this list of conditions and the following disclaimer.
29549+ * * Redistributions in binary form must reproduce the above copyright
29550+ * notice, this list of conditions and the following disclaimer in the
29551+ * documentation and/or other materials provided with the distribution.
29552+ * * Neither the name of the above-listed copyright holders nor the
29553+ * names of any contributors may be used to endorse or promote products
29554+ * derived from this software without specific prior written permission.
29555+ *
29556+ *
29557+ * ALTERNATIVELY, this software may be distributed under the terms of the
29558+ * GNU General Public License ("GPL") as published by the Free Software
29559+ * Foundation, either version 2 of that License or (at your option) any
29560+ * later version.
29561+ *
29562+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29563+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29564+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29565+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
29566+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29567+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29568+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29569+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29570+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29571+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29572+ * POSSIBILITY OF SUCH DAMAGE.
29573+ */
29574+#ifndef _FSL_MC_SYS_H
29575+#define _FSL_MC_SYS_H
29576+
29577+#ifdef __linux_driver__
29578+
29579+#include <linux/errno.h>
29580+#include <asm/io.h>
29581+#include <linux/slab.h>
29582+
29583+struct fsl_mc_io {
29584+ void *regs;
29585+};
29586+
29587+#ifndef ENOTSUP
29588+#define ENOTSUP 95
29589+#endif
29590+
29591+#define ioread64(_p) readq(_p)
29592+#define iowrite64(_v, _p) writeq(_v, _p)
29593+
29594+#else /* __linux_driver__ */
29595+
29596+#include <stdio.h>
29597+#include <libio.h>
29598+#include <stdint.h>
29599+#include <errno.h>
29600+#include <sys/uio.h>
29601+#include <linux/byteorder/little_endian.h>
29602+
29603+#define cpu_to_le64(x) __cpu_to_le64(x)
29604+#ifndef dmb
29605+#define dmb() __asm__ __volatile__ ("" : : : "memory")
29606+#endif
29607+#define __iormb() dmb()
29608+#define __iowmb() dmb()
29609+#define __arch_getq(a) (*(volatile unsigned long *)(a))
29610+#define __arch_putq(v, a) (*(volatile unsigned long *)(a) = (v))
29611+#define __arch_putq32(v, a) (*(volatile unsigned int *)(a) = (v))
29612+#define readq(c) ({ uint64_t __v = __arch_getq(c); __iormb(); __v; })
29613+#define writeq(v, c) ({ uint64_t __v = v; __iowmb(); __arch_putq(__v, c); __v; })
29614+#define writeq32(v, c) ({ uint32_t __v = v; __iowmb(); __arch_putq32(__v, c); __v; })
29615+#define ioread64(_p) readq(_p)
29616+#define iowrite64(_v, _p) writeq(_v, _p)
29617+#define iowrite32(_v, _p) writeq32(_v, _p)
29618+#define __iomem
29619+
29620+struct fsl_mc_io {
29621+ void *regs;
29622+};
29623+
29624+#ifndef ENOTSUP
29625+#define ENOTSUP 95
29626+#endif
29627+
29628+/*GPP is supposed to use MC commands with low priority*/
29629+#define CMD_PRI_LOW 0 /*!< Low Priority command indication */
29630+
29631+struct mc_command;
29632+
29633+int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd);
29634+
29635+#endif /* __linux_driver__ */
29636+
29637+#endif /* _FSL_MC_SYS_H */
29638diff --git a/drivers/net/dpaa2/mc/fsl_net.h b/drivers/net/dpaa2/mc/fsl_net.h
29639new file mode 100644
29640index 0000000..43825b8
29641--- /dev/null
29642+++ b/drivers/net/dpaa2/mc/fsl_net.h
29643@@ -0,0 +1,480 @@
29644+/* Copyright 2013-2015 Freescale Semiconductor Inc.
29645+ *
29646+ * Redistribution and use in source and binary forms, with or without
29647+ * modification, are permitted provided that the following conditions are met:
29648+ * * Redistributions of source code must retain the above copyright
29649+ * notice, this list of conditions and the following disclaimer.
29650+ * * Redistributions in binary form must reproduce the above copyright
29651+ * notice, this list of conditions and the following disclaimer in the
29652+ * documentation and/or other materials provided with the distribution.
29653+ * * Neither the name of the above-listed copyright holders nor the
29654+ * names of any contributors may be used to endorse or promote products
29655+ * derived from this software without specific prior written permission.
29656+ *
29657+ *
29658+ * ALTERNATIVELY, this software may be distributed under the terms of the
29659+ * GNU General Public License ("GPL") as published by the Free Software
29660+ * Foundation, either version 2 of that License or (at your option) any
29661+ * later version.
29662+ *
29663+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29664+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29665+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29666+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
29667+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29668+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29669+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29670+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29671+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29672+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29673+ * POSSIBILITY OF SUCH DAMAGE.
29674+ */
29675+#ifndef __FSL_NET_H
29676+#define __FSL_NET_H
29677+
29678+#define LAST_HDR_INDEX 0xFFFFFFFF
29679+
29680+/*****************************************************************************/
29681+/* Protocol fields */
29682+/*****************************************************************************/
29683+
29684+/************************* Ethernet fields *********************************/
29685+#define NH_FLD_ETH_DA (1)
29686+#define NH_FLD_ETH_SA (NH_FLD_ETH_DA << 1)
29687+#define NH_FLD_ETH_LENGTH (NH_FLD_ETH_DA << 2)
29688+#define NH_FLD_ETH_TYPE (NH_FLD_ETH_DA << 3)
29689+#define NH_FLD_ETH_FINAL_CKSUM (NH_FLD_ETH_DA << 4)
29690+#define NH_FLD_ETH_PADDING (NH_FLD_ETH_DA << 5)
29691+#define NH_FLD_ETH_ALL_FIELDS ((NH_FLD_ETH_DA << 6) - 1)
29692+
29693+#define NH_FLD_ETH_ADDR_SIZE 6
29694+
29695+/*************************** VLAN fields ***********************************/
29696+#define NH_FLD_VLAN_VPRI (1)
29697+#define NH_FLD_VLAN_CFI (NH_FLD_VLAN_VPRI << 1)
29698+#define NH_FLD_VLAN_VID (NH_FLD_VLAN_VPRI << 2)
29699+#define NH_FLD_VLAN_LENGTH (NH_FLD_VLAN_VPRI << 3)
29700+#define NH_FLD_VLAN_TYPE (NH_FLD_VLAN_VPRI << 4)
29701+#define NH_FLD_VLAN_ALL_FIELDS ((NH_FLD_VLAN_VPRI << 5) - 1)
29702+
29703+#define NH_FLD_VLAN_TCI (NH_FLD_VLAN_VPRI | \
29704+ NH_FLD_VLAN_CFI | \
29705+ NH_FLD_VLAN_VID)
29706+
29707+/************************ IP (generic) fields ******************************/
29708+#define NH_FLD_IP_VER (1)
29709+#define NH_FLD_IP_DSCP (NH_FLD_IP_VER << 2)
29710+#define NH_FLD_IP_ECN (NH_FLD_IP_VER << 3)
29711+#define NH_FLD_IP_PROTO (NH_FLD_IP_VER << 4)
29712+#define NH_FLD_IP_SRC (NH_FLD_IP_VER << 5)
29713+#define NH_FLD_IP_DST (NH_FLD_IP_VER << 6)
29714+#define NH_FLD_IP_TOS_TC (NH_FLD_IP_VER << 7)
29715+#define NH_FLD_IP_ID (NH_FLD_IP_VER << 8)
29716+#define NH_FLD_IP_ALL_FIELDS ((NH_FLD_IP_VER << 9) - 1)
29717+
29718+#define NH_FLD_IP_PROTO_SIZE 1
29719+
29720+/***************************** IPV4 fields *********************************/
29721+#define NH_FLD_IPV4_VER (1)
29722+#define NH_FLD_IPV4_HDR_LEN (NH_FLD_IPV4_VER << 1)
29723+#define NH_FLD_IPV4_TOS (NH_FLD_IPV4_VER << 2)
29724+#define NH_FLD_IPV4_TOTAL_LEN (NH_FLD_IPV4_VER << 3)
29725+#define NH_FLD_IPV4_ID (NH_FLD_IPV4_VER << 4)
29726+#define NH_FLD_IPV4_FLAG_D (NH_FLD_IPV4_VER << 5)
29727+#define NH_FLD_IPV4_FLAG_M (NH_FLD_IPV4_VER << 6)
29728+#define NH_FLD_IPV4_OFFSET (NH_FLD_IPV4_VER << 7)
29729+#define NH_FLD_IPV4_TTL (NH_FLD_IPV4_VER << 8)
29730+#define NH_FLD_IPV4_PROTO (NH_FLD_IPV4_VER << 9)
29731+#define NH_FLD_IPV4_CKSUM (NH_FLD_IPV4_VER << 10)
29732+#define NH_FLD_IPV4_SRC_IP (NH_FLD_IPV4_VER << 11)
29733+#define NH_FLD_IPV4_DST_IP (NH_FLD_IPV4_VER << 12)
29734+#define NH_FLD_IPV4_OPTS (NH_FLD_IPV4_VER << 13)
29735+#define NH_FLD_IPV4_OPTS_COUNT (NH_FLD_IPV4_VER << 14)
29736+#define NH_FLD_IPV4_ALL_FIELDS ((NH_FLD_IPV4_VER << 15) - 1)
29737+
29738+#define NH_FLD_IPV4_ADDR_SIZE 4
29739+#define NH_FLD_IPV4_PROTO_SIZE 1
29740+
29741+/***************************** IPV6 fields *********************************/
29742+#define NH_FLD_IPV6_VER (1)
29743+#define NH_FLD_IPV6_TC (NH_FLD_IPV6_VER << 1)
29744+#define NH_FLD_IPV6_SRC_IP (NH_FLD_IPV6_VER << 2)
29745+#define NH_FLD_IPV6_DST_IP (NH_FLD_IPV6_VER << 3)
29746+#define NH_FLD_IPV6_NEXT_HDR (NH_FLD_IPV6_VER << 4)
29747+#define NH_FLD_IPV6_FL (NH_FLD_IPV6_VER << 5)
29748+#define NH_FLD_IPV6_HOP_LIMIT (NH_FLD_IPV6_VER << 6)
29749+#define NH_FLD_IPV6_ID (NH_FLD_IPV6_VER << 7)
29750+#define NH_FLD_IPV6_ALL_FIELDS ((NH_FLD_IPV6_VER << 8) - 1)
29751+
29752+#define NH_FLD_IPV6_ADDR_SIZE 16
29753+#define NH_FLD_IPV6_NEXT_HDR_SIZE 1
29754+
29755+/***************************** ICMP fields *********************************/
29756+#define NH_FLD_ICMP_TYPE (1)
29757+#define NH_FLD_ICMP_CODE (NH_FLD_ICMP_TYPE << 1)
29758+#define NH_FLD_ICMP_CKSUM (NH_FLD_ICMP_TYPE << 2)
29759+#define NH_FLD_ICMP_ID (NH_FLD_ICMP_TYPE << 3)
29760+#define NH_FLD_ICMP_SQ_NUM (NH_FLD_ICMP_TYPE << 4)
29761+#define NH_FLD_ICMP_ALL_FIELDS ((NH_FLD_ICMP_TYPE << 5) - 1)
29762+
29763+#define NH_FLD_ICMP_CODE_SIZE 1
29764+#define NH_FLD_ICMP_TYPE_SIZE 1
29765+
29766+/***************************** IGMP fields *********************************/
29767+#define NH_FLD_IGMP_VERSION (1)
29768+#define NH_FLD_IGMP_TYPE (NH_FLD_IGMP_VERSION << 1)
29769+#define NH_FLD_IGMP_CKSUM (NH_FLD_IGMP_VERSION << 2)
29770+#define NH_FLD_IGMP_DATA (NH_FLD_IGMP_VERSION << 3)
29771+#define NH_FLD_IGMP_ALL_FIELDS ((NH_FLD_IGMP_VERSION << 4) - 1)
29772+
29773+/***************************** TCP fields **********************************/
29774+#define NH_FLD_TCP_PORT_SRC (1)
29775+#define NH_FLD_TCP_PORT_DST (NH_FLD_TCP_PORT_SRC << 1)
29776+#define NH_FLD_TCP_SEQ (NH_FLD_TCP_PORT_SRC << 2)
29777+#define NH_FLD_TCP_ACK (NH_FLD_TCP_PORT_SRC << 3)
29778+#define NH_FLD_TCP_OFFSET (NH_FLD_TCP_PORT_SRC << 4)
29779+#define NH_FLD_TCP_FLAGS (NH_FLD_TCP_PORT_SRC << 5)
29780+#define NH_FLD_TCP_WINDOW (NH_FLD_TCP_PORT_SRC << 6)
29781+#define NH_FLD_TCP_CKSUM (NH_FLD_TCP_PORT_SRC << 7)
29782+#define NH_FLD_TCP_URGPTR (NH_FLD_TCP_PORT_SRC << 8)
29783+#define NH_FLD_TCP_OPTS (NH_FLD_TCP_PORT_SRC << 9)
29784+#define NH_FLD_TCP_OPTS_COUNT (NH_FLD_TCP_PORT_SRC << 10)
29785+#define NH_FLD_TCP_ALL_FIELDS ((NH_FLD_TCP_PORT_SRC << 11) - 1)
29786+
29787+#define NH_FLD_TCP_PORT_SIZE 2
29788+
29789+/***************************** UDP fields **********************************/
29790+#define NH_FLD_UDP_PORT_SRC (1)
29791+#define NH_FLD_UDP_PORT_DST (NH_FLD_UDP_PORT_SRC << 1)
29792+#define NH_FLD_UDP_LEN (NH_FLD_UDP_PORT_SRC << 2)
29793+#define NH_FLD_UDP_CKSUM (NH_FLD_UDP_PORT_SRC << 3)
29794+#define NH_FLD_UDP_ALL_FIELDS ((NH_FLD_UDP_PORT_SRC << 4) - 1)
29795+
29796+#define NH_FLD_UDP_PORT_SIZE 2
29797+
29798+/*************************** UDP-lite fields *******************************/
29799+#define NH_FLD_UDP_LITE_PORT_SRC (1)
29800+#define NH_FLD_UDP_LITE_PORT_DST (NH_FLD_UDP_LITE_PORT_SRC << 1)
29801+#define NH_FLD_UDP_LITE_ALL_FIELDS \
29802+ ((NH_FLD_UDP_LITE_PORT_SRC << 2) - 1)
29803+
29804+#define NH_FLD_UDP_LITE_PORT_SIZE 2
29805+
29806+/*************************** UDP-encap-ESP fields **************************/
29807+#define NH_FLD_UDP_ENC_ESP_PORT_SRC (1)
29808+#define NH_FLD_UDP_ENC_ESP_PORT_DST (NH_FLD_UDP_ENC_ESP_PORT_SRC << 1)
29809+#define NH_FLD_UDP_ENC_ESP_LEN (NH_FLD_UDP_ENC_ESP_PORT_SRC << 2)
29810+#define NH_FLD_UDP_ENC_ESP_CKSUM (NH_FLD_UDP_ENC_ESP_PORT_SRC << 3)
29811+#define NH_FLD_UDP_ENC_ESP_SPI (NH_FLD_UDP_ENC_ESP_PORT_SRC << 4)
29812+#define NH_FLD_UDP_ENC_ESP_SEQUENCE_NUM (NH_FLD_UDP_ENC_ESP_PORT_SRC << 5)
29813+#define NH_FLD_UDP_ENC_ESP_ALL_FIELDS \
29814+ ((NH_FLD_UDP_ENC_ESP_PORT_SRC << 6) - 1)
29815+
29816+#define NH_FLD_UDP_ENC_ESP_PORT_SIZE 2
29817+#define NH_FLD_UDP_ENC_ESP_SPI_SIZE 4
29818+
29819+/***************************** SCTP fields *********************************/
29820+#define NH_FLD_SCTP_PORT_SRC (1)
29821+#define NH_FLD_SCTP_PORT_DST (NH_FLD_SCTP_PORT_SRC << 1)
29822+#define NH_FLD_SCTP_VER_TAG (NH_FLD_SCTP_PORT_SRC << 2)
29823+#define NH_FLD_SCTP_CKSUM (NH_FLD_SCTP_PORT_SRC << 3)
29824+#define NH_FLD_SCTP_ALL_FIELDS ((NH_FLD_SCTP_PORT_SRC << 4) - 1)
29825+
29826+#define NH_FLD_SCTP_PORT_SIZE 2
29827+
29828+/***************************** DCCP fields *********************************/
29829+#define NH_FLD_DCCP_PORT_SRC (1)
29830+#define NH_FLD_DCCP_PORT_DST (NH_FLD_DCCP_PORT_SRC << 1)
29831+#define NH_FLD_DCCP_ALL_FIELDS ((NH_FLD_DCCP_PORT_SRC << 2) - 1)
29832+
29833+#define NH_FLD_DCCP_PORT_SIZE 2
29834+
29835+/***************************** IPHC fields *********************************/
29836+#define NH_FLD_IPHC_CID (1)
29837+#define NH_FLD_IPHC_CID_TYPE (NH_FLD_IPHC_CID << 1)
29838+#define NH_FLD_IPHC_HCINDEX (NH_FLD_IPHC_CID << 2)
29839+#define NH_FLD_IPHC_GEN (NH_FLD_IPHC_CID << 3)
29840+#define NH_FLD_IPHC_D_BIT (NH_FLD_IPHC_CID << 4)
29841+#define NH_FLD_IPHC_ALL_FIELDS ((NH_FLD_IPHC_CID << 5) - 1)
29842+
29843+/***************************** SCTP fields *********************************/
29844+#define NH_FLD_SCTP_CHUNK_DATA_TYPE (1)
29845+#define NH_FLD_SCTP_CHUNK_DATA_FLAGS (NH_FLD_SCTP_CHUNK_DATA_TYPE << 1)
29846+#define NH_FLD_SCTP_CHUNK_DATA_LENGTH (NH_FLD_SCTP_CHUNK_DATA_TYPE << 2)
29847+#define NH_FLD_SCTP_CHUNK_DATA_TSN (NH_FLD_SCTP_CHUNK_DATA_TYPE << 3)
29848+#define NH_FLD_SCTP_CHUNK_DATA_STREAM_ID (NH_FLD_SCTP_CHUNK_DATA_TYPE << 4)
29849+#define NH_FLD_SCTP_CHUNK_DATA_STREAM_SQN (NH_FLD_SCTP_CHUNK_DATA_TYPE << 5)
29850+#define NH_FLD_SCTP_CHUNK_DATA_PAYLOAD_PID (NH_FLD_SCTP_CHUNK_DATA_TYPE << 6)
29851+#define NH_FLD_SCTP_CHUNK_DATA_UNORDERED (NH_FLD_SCTP_CHUNK_DATA_TYPE << 7)
29852+#define NH_FLD_SCTP_CHUNK_DATA_BEGGINING (NH_FLD_SCTP_CHUNK_DATA_TYPE << 8)
29853+#define NH_FLD_SCTP_CHUNK_DATA_END (NH_FLD_SCTP_CHUNK_DATA_TYPE << 9)
29854+#define NH_FLD_SCTP_CHUNK_DATA_ALL_FIELDS \
29855+ ((NH_FLD_SCTP_CHUNK_DATA_TYPE << 10) - 1)
29856+
29857+/*************************** L2TPV2 fields *********************************/
29858+#define NH_FLD_L2TPV2_TYPE_BIT (1)
29859+#define NH_FLD_L2TPV2_LENGTH_BIT (NH_FLD_L2TPV2_TYPE_BIT << 1)
29860+#define NH_FLD_L2TPV2_SEQUENCE_BIT (NH_FLD_L2TPV2_TYPE_BIT << 2)
29861+#define NH_FLD_L2TPV2_OFFSET_BIT (NH_FLD_L2TPV2_TYPE_BIT << 3)
29862+#define NH_FLD_L2TPV2_PRIORITY_BIT (NH_FLD_L2TPV2_TYPE_BIT << 4)
29863+#define NH_FLD_L2TPV2_VERSION (NH_FLD_L2TPV2_TYPE_BIT << 5)
29864+#define NH_FLD_L2TPV2_LEN (NH_FLD_L2TPV2_TYPE_BIT << 6)
29865+#define NH_FLD_L2TPV2_TUNNEL_ID (NH_FLD_L2TPV2_TYPE_BIT << 7)
29866+#define NH_FLD_L2TPV2_SESSION_ID (NH_FLD_L2TPV2_TYPE_BIT << 8)
29867+#define NH_FLD_L2TPV2_NS (NH_FLD_L2TPV2_TYPE_BIT << 9)
29868+#define NH_FLD_L2TPV2_NR (NH_FLD_L2TPV2_TYPE_BIT << 10)
29869+#define NH_FLD_L2TPV2_OFFSET_SIZE (NH_FLD_L2TPV2_TYPE_BIT << 11)
29870+#define NH_FLD_L2TPV2_FIRST_BYTE (NH_FLD_L2TPV2_TYPE_BIT << 12)
29871+#define NH_FLD_L2TPV2_ALL_FIELDS \
29872+ ((NH_FLD_L2TPV2_TYPE_BIT << 13) - 1)
29873+
29874+/*************************** L2TPV3 fields *********************************/
29875+#define NH_FLD_L2TPV3_CTRL_TYPE_BIT (1)
29876+#define NH_FLD_L2TPV3_CTRL_LENGTH_BIT (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 1)
29877+#define NH_FLD_L2TPV3_CTRL_SEQUENCE_BIT (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 2)
29878+#define NH_FLD_L2TPV3_CTRL_VERSION (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 3)
29879+#define NH_FLD_L2TPV3_CTRL_LENGTH (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 4)
29880+#define NH_FLD_L2TPV3_CTRL_CONTROL (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 5)
29881+#define NH_FLD_L2TPV3_CTRL_SENT (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 6)
29882+#define NH_FLD_L2TPV3_CTRL_RECV (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 7)
29883+#define NH_FLD_L2TPV3_CTRL_FIRST_BYTE (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 8)
29884+#define NH_FLD_L2TPV3_CTRL_ALL_FIELDS \
29885+ ((NH_FLD_L2TPV3_CTRL_TYPE_BIT << 9) - 1)
29886+
29887+#define NH_FLD_L2TPV3_SESS_TYPE_BIT (1)
29888+#define NH_FLD_L2TPV3_SESS_VERSION (NH_FLD_L2TPV3_SESS_TYPE_BIT << 1)
29889+#define NH_FLD_L2TPV3_SESS_ID (NH_FLD_L2TPV3_SESS_TYPE_BIT << 2)
29890+#define NH_FLD_L2TPV3_SESS_COOKIE (NH_FLD_L2TPV3_SESS_TYPE_BIT << 3)
29891+#define NH_FLD_L2TPV3_SESS_ALL_FIELDS \
29892+ ((NH_FLD_L2TPV3_SESS_TYPE_BIT << 4) - 1)
29893+
29894+/**************************** PPP fields ***********************************/
29895+#define NH_FLD_PPP_PID (1)
29896+#define NH_FLD_PPP_COMPRESSED (NH_FLD_PPP_PID << 1)
29897+#define NH_FLD_PPP_ALL_FIELDS ((NH_FLD_PPP_PID << 2) - 1)
29898+
29899+/************************** PPPoE fields ***********************************/
29900+#define NH_FLD_PPPOE_VER (1)
29901+#define NH_FLD_PPPOE_TYPE (NH_FLD_PPPOE_VER << 1)
29902+#define NH_FLD_PPPOE_CODE (NH_FLD_PPPOE_VER << 2)
29903+#define NH_FLD_PPPOE_SID (NH_FLD_PPPOE_VER << 3)
29904+#define NH_FLD_PPPOE_LEN (NH_FLD_PPPOE_VER << 4)
29905+#define NH_FLD_PPPOE_SESSION (NH_FLD_PPPOE_VER << 5)
29906+#define NH_FLD_PPPOE_PID (NH_FLD_PPPOE_VER << 6)
29907+#define NH_FLD_PPPOE_ALL_FIELDS ((NH_FLD_PPPOE_VER << 7) - 1)
29908+
29909+/************************* PPP-Mux fields **********************************/
29910+#define NH_FLD_PPPMUX_PID (1)
29911+#define NH_FLD_PPPMUX_CKSUM (NH_FLD_PPPMUX_PID << 1)
29912+#define NH_FLD_PPPMUX_COMPRESSED (NH_FLD_PPPMUX_PID << 2)
29913+#define NH_FLD_PPPMUX_ALL_FIELDS ((NH_FLD_PPPMUX_PID << 3) - 1)
29914+
29915+/*********************** PPP-Mux sub-frame fields **************************/
29916+#define NH_FLD_PPPMUX_SUBFRM_PFF (1)
29917+#define NH_FLD_PPPMUX_SUBFRM_LXT (NH_FLD_PPPMUX_SUBFRM_PFF << 1)
29918+#define NH_FLD_PPPMUX_SUBFRM_LEN (NH_FLD_PPPMUX_SUBFRM_PFF << 2)
29919+#define NH_FLD_PPPMUX_SUBFRM_PID (NH_FLD_PPPMUX_SUBFRM_PFF << 3)
29920+#define NH_FLD_PPPMUX_SUBFRM_USE_PID (NH_FLD_PPPMUX_SUBFRM_PFF << 4)
29921+#define NH_FLD_PPPMUX_SUBFRM_ALL_FIELDS \
29922+ ((NH_FLD_PPPMUX_SUBFRM_PFF << 5) - 1)
29923+
29924+/*************************** LLC fields ************************************/
29925+#define NH_FLD_LLC_DSAP (1)
29926+#define NH_FLD_LLC_SSAP (NH_FLD_LLC_DSAP << 1)
29927+#define NH_FLD_LLC_CTRL (NH_FLD_LLC_DSAP << 2)
29928+#define NH_FLD_LLC_ALL_FIELDS ((NH_FLD_LLC_DSAP << 3) - 1)
29929+
29930+/*************************** NLPID fields **********************************/
29931+#define NH_FLD_NLPID_NLPID (1)
29932+#define NH_FLD_NLPID_ALL_FIELDS ((NH_FLD_NLPID_NLPID << 1) - 1)
29933+
29934+/*************************** SNAP fields ***********************************/
29935+#define NH_FLD_SNAP_OUI (1)
29936+#define NH_FLD_SNAP_PID (NH_FLD_SNAP_OUI << 1)
29937+#define NH_FLD_SNAP_ALL_FIELDS ((NH_FLD_SNAP_OUI << 2) - 1)
29938+
29939+/*************************** LLC SNAP fields *******************************/
29940+#define NH_FLD_LLC_SNAP_TYPE (1)
29941+#define NH_FLD_LLC_SNAP_ALL_FIELDS ((NH_FLD_LLC_SNAP_TYPE << 1) - 1)
29942+
29943+#define NH_FLD_ARP_HTYPE (1)
29944+#define NH_FLD_ARP_PTYPE (NH_FLD_ARP_HTYPE << 1)
29945+#define NH_FLD_ARP_HLEN (NH_FLD_ARP_HTYPE << 2)
29946+#define NH_FLD_ARP_PLEN (NH_FLD_ARP_HTYPE << 3)
29947+#define NH_FLD_ARP_OPER (NH_FLD_ARP_HTYPE << 4)
29948+#define NH_FLD_ARP_SHA (NH_FLD_ARP_HTYPE << 5)
29949+#define NH_FLD_ARP_SPA (NH_FLD_ARP_HTYPE << 6)
29950+#define NH_FLD_ARP_THA (NH_FLD_ARP_HTYPE << 7)
29951+#define NH_FLD_ARP_TPA (NH_FLD_ARP_HTYPE << 8)
29952+#define NH_FLD_ARP_ALL_FIELDS ((NH_FLD_ARP_HTYPE << 9) - 1)
29953+
29954+/*************************** RFC2684 fields ********************************/
29955+#define NH_FLD_RFC2684_LLC (1)
29956+#define NH_FLD_RFC2684_NLPID (NH_FLD_RFC2684_LLC << 1)
29957+#define NH_FLD_RFC2684_OUI (NH_FLD_RFC2684_LLC << 2)
29958+#define NH_FLD_RFC2684_PID (NH_FLD_RFC2684_LLC << 3)
29959+#define NH_FLD_RFC2684_VPN_OUI (NH_FLD_RFC2684_LLC << 4)
29960+#define NH_FLD_RFC2684_VPN_IDX (NH_FLD_RFC2684_LLC << 5)
29961+#define NH_FLD_RFC2684_ALL_FIELDS ((NH_FLD_RFC2684_LLC << 6) - 1)
29962+
29963+/*************************** User defined fields ***************************/
29964+#define NH_FLD_USER_DEFINED_SRCPORT (1)
29965+#define NH_FLD_USER_DEFINED_PCDID (NH_FLD_USER_DEFINED_SRCPORT << 1)
29966+#define NH_FLD_USER_DEFINED_ALL_FIELDS \
29967+ ((NH_FLD_USER_DEFINED_SRCPORT << 2) - 1)
29968+
29969+/*************************** Payload fields ********************************/
29970+#define NH_FLD_PAYLOAD_BUFFER (1)
29971+#define NH_FLD_PAYLOAD_SIZE (NH_FLD_PAYLOAD_BUFFER << 1)
29972+#define NH_FLD_MAX_FRM_SIZE (NH_FLD_PAYLOAD_BUFFER << 2)
29973+#define NH_FLD_MIN_FRM_SIZE (NH_FLD_PAYLOAD_BUFFER << 3)
29974+#define NH_FLD_PAYLOAD_TYPE (NH_FLD_PAYLOAD_BUFFER << 4)
29975+#define NH_FLD_FRAME_SIZE (NH_FLD_PAYLOAD_BUFFER << 5)
29976+#define NH_FLD_PAYLOAD_ALL_FIELDS ((NH_FLD_PAYLOAD_BUFFER << 6) - 1)
29977+
29978+/*************************** GRE fields ************************************/
29979+#define NH_FLD_GRE_TYPE (1)
29980+#define NH_FLD_GRE_ALL_FIELDS ((NH_FLD_GRE_TYPE << 1) - 1)
29981+
29982+/*************************** MINENCAP fields *******************************/
29983+#define NH_FLD_MINENCAP_SRC_IP (1)
29984+#define NH_FLD_MINENCAP_DST_IP (NH_FLD_MINENCAP_SRC_IP << 1)
29985+#define NH_FLD_MINENCAP_TYPE (NH_FLD_MINENCAP_SRC_IP << 2)
29986+#define NH_FLD_MINENCAP_ALL_FIELDS \
29987+ ((NH_FLD_MINENCAP_SRC_IP << 3) - 1)
29988+
29989+/*************************** IPSEC AH fields *******************************/
29990+#define NH_FLD_IPSEC_AH_SPI (1)
29991+#define NH_FLD_IPSEC_AH_NH (NH_FLD_IPSEC_AH_SPI << 1)
29992+#define NH_FLD_IPSEC_AH_ALL_FIELDS ((NH_FLD_IPSEC_AH_SPI << 2) - 1)
29993+
29994+/*************************** IPSEC ESP fields ******************************/
29995+#define NH_FLD_IPSEC_ESP_SPI (1)
29996+#define NH_FLD_IPSEC_ESP_SEQUENCE_NUM (NH_FLD_IPSEC_ESP_SPI << 1)
29997+#define NH_FLD_IPSEC_ESP_ALL_FIELDS ((NH_FLD_IPSEC_ESP_SPI << 2) - 1)
29998+
29999+#define NH_FLD_IPSEC_ESP_SPI_SIZE 4
30000+
30001+/*************************** MPLS fields ***********************************/
30002+#define NH_FLD_MPLS_LABEL_STACK (1)
30003+#define NH_FLD_MPLS_LABEL_STACK_ALL_FIELDS \
30004+ ((NH_FLD_MPLS_LABEL_STACK << 1) - 1)
30005+
30006+/*************************** MACSEC fields *********************************/
30007+#define NH_FLD_MACSEC_SECTAG (1)
30008+#define NH_FLD_MACSEC_ALL_FIELDS ((NH_FLD_MACSEC_SECTAG << 1) - 1)
30009+
30010+/*************************** GTP fields ************************************/
30011+#define NH_FLD_GTP_TEID (1)
30012+
30013+/* Protocol options */
30014+
30015+/* Ethernet options */
30016+#define NH_OPT_ETH_BROADCAST 1
30017+#define NH_OPT_ETH_MULTICAST 2
30018+#define NH_OPT_ETH_UNICAST 3
30019+#define NH_OPT_ETH_BPDU 4
30020+
30021+#define NH_ETH_IS_MULTICAST_ADDR(addr) (addr[0] & 0x01)
30022+/* also applicable for broadcast */
30023+
30024+/* VLAN options */
30025+#define NH_OPT_VLAN_CFI 1
30026+
30027+/* IPV4 options */
30028+#define NH_OPT_IPV4_UNICAST 1
30029+#define NH_OPT_IPV4_MULTICAST 2
30030+#define NH_OPT_IPV4_BROADCAST 3
30031+#define NH_OPT_IPV4_OPTION 4
30032+#define NH_OPT_IPV4_FRAG 5
30033+#define NH_OPT_IPV4_INITIAL_FRAG 6
30034+
30035+/* IPV6 options */
30036+#define NH_OPT_IPV6_UNICAST 1
30037+#define NH_OPT_IPV6_MULTICAST 2
30038+#define NH_OPT_IPV6_OPTION 3
30039+#define NH_OPT_IPV6_FRAG 4
30040+#define NH_OPT_IPV6_INITIAL_FRAG 5
30041+
30042+/* General IP options (may be used for any version) */
30043+#define NH_OPT_IP_FRAG 1
30044+#define NH_OPT_IP_INITIAL_FRAG 2
30045+#define NH_OPT_IP_OPTION 3
30046+
30047+/* Minenc. options */
30048+#define NH_OPT_MINENCAP_SRC_ADDR_PRESENT 1
30049+
30050+/* GRE. options */
30051+#define NH_OPT_GRE_ROUTING_PRESENT 1
30052+
30053+/* TCP options */
30054+#define NH_OPT_TCP_OPTIONS 1
30055+#define NH_OPT_TCP_CONTROL_HIGH_BITS 2
30056+#define NH_OPT_TCP_CONTROL_LOW_BITS 3
30057+
30058+/* CAPWAP options */
30059+#define NH_OPT_CAPWAP_DTLS 1
30060+
30061+enum net_prot {
30062+ NET_PROT_NONE = 0,
30063+ NET_PROT_PAYLOAD,
30064+ NET_PROT_ETH,
30065+ NET_PROT_VLAN,
30066+ NET_PROT_IPV4,
30067+ NET_PROT_IPV6,
30068+ NET_PROT_IP,
30069+ NET_PROT_TCP,
30070+ NET_PROT_UDP,
30071+ NET_PROT_UDP_LITE,
30072+ NET_PROT_IPHC,
30073+ NET_PROT_SCTP,
30074+ NET_PROT_SCTP_CHUNK_DATA,
30075+ NET_PROT_PPPOE,
30076+ NET_PROT_PPP,
30077+ NET_PROT_PPPMUX,
30078+ NET_PROT_PPPMUX_SUBFRM,
30079+ NET_PROT_L2TPV2,
30080+ NET_PROT_L2TPV3_CTRL,
30081+ NET_PROT_L2TPV3_SESS,
30082+ NET_PROT_LLC,
30083+ NET_PROT_LLC_SNAP,
30084+ NET_PROT_NLPID,
30085+ NET_PROT_SNAP,
30086+ NET_PROT_MPLS,
30087+ NET_PROT_IPSEC_AH,
30088+ NET_PROT_IPSEC_ESP,
30089+ NET_PROT_UDP_ENC_ESP, /* RFC 3948 */
30090+ NET_PROT_MACSEC,
30091+ NET_PROT_GRE,
30092+ NET_PROT_MINENCAP,
30093+ NET_PROT_DCCP,
30094+ NET_PROT_ICMP,
30095+ NET_PROT_IGMP,
30096+ NET_PROT_ARP,
30097+ NET_PROT_CAPWAP_DATA,
30098+ NET_PROT_CAPWAP_CTRL,
30099+ NET_PROT_RFC2684,
30100+ NET_PROT_ICMPV6,
30101+ NET_PROT_FCOE,
30102+ NET_PROT_FIP,
30103+ NET_PROT_ISCSI,
30104+ NET_PROT_GTP,
30105+ NET_PROT_USER_DEFINED_L2,
30106+ NET_PROT_USER_DEFINED_L3,
30107+ NET_PROT_USER_DEFINED_L4,
30108+ NET_PROT_USER_DEFINED_L5,
30109+ NET_PROT_USER_DEFINED_SHIM1,
30110+ NET_PROT_USER_DEFINED_SHIM2,
30111+
30112+ NET_PROT_DUMMY_LAST
30113+};
30114+
30115+/*! IEEE8021.Q */
30116+#define NH_IEEE8021Q_ETYPE 0x8100
30117+#define NH_IEEE8021Q_HDR(etype, pcp, dei, vlan_id) \
30118+ ((((uint32_t)(etype & 0xFFFF)) << 16) | \
30119+ (((uint32_t)(pcp & 0x07)) << 13) | \
30120+ (((uint32_t)(dei & 0x01)) << 12) | \
30121+ (((uint32_t)(vlan_id & 0xFFF))))
30122+
30123+#endif /* __FSL_NET_H */
30124diff --git a/drivers/net/dpaa2/mc/mc_sys.c b/drivers/net/dpaa2/mc/mc_sys.c
30125new file mode 100644
30126index 0000000..0a88cad
30127--- /dev/null
30128+++ b/drivers/net/dpaa2/mc/mc_sys.c
30129@@ -0,0 +1,129 @@
30130+/* Copyright 2013-2015 Freescale Semiconductor Inc.
30131+ *
30132+ * Redistribution and use in source and binary forms, with or without
30133+ * modification, are permitted provided that the following conditions are met:
30134+ * * Redistributions of source code must retain the above copyright
30135+ * notice, this list of conditions and the following disclaimer.
30136+ * * Redistributions in binary form must reproduce the above copyright
30137+ * notice, this list of conditions and the following disclaimer in the
30138+ * documentation and/or other materials provided with the distribution.
30139+ * * Neither the name of the above-listed copyright holders nor the
30140+ * names of any contributors may be used to endorse or promote products
30141+ * derived from this software without specific prior written permission.
30142+ *
30143+ *
30144+ * ALTERNATIVELY, this software may be distributed under the terms of the
30145+ * GNU General Public License ("GPL") as published by the Free Software
30146+ * Foundation, either version 2 of that License or (at your option) any
30147+ * later version.
30148+ *
30149+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30150+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30151+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30152+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
30153+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30154+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30155+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30156+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30157+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30158+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30159+ * POSSIBILITY OF SUCH DAMAGE.
30160+ */
30161+#include <fsl_mc_sys.h>
30162+#include <fsl_mc_cmd.h>
30163+
30164+/* ODP framework using MC poratl in shared mode. Following
30165+ changes to introduce Locks must be maintained while
30166+ merging the FLIB.
30167+*/
30168+
30169+/**
30170+* The mc_spinlock_t type.
30171+*/
30172+typedef struct {
30173+ volatile int locked; /**< lock status 0 = unlocked, 1 = locked */
30174+} mc_spinlock_t;
30175+
30176+/**
30177+* A static spinlock initializer.
30178+*/
30179+static mc_spinlock_t mc_portal_lock = { 0 };
30180+
30181+static inline void mc_pause(void) {}
30182+
30183+static inline void mc_spinlock_lock(mc_spinlock_t *sl)
30184+{
30185+ while (__sync_lock_test_and_set(&sl->locked, 1))
30186+ while (sl->locked)
30187+ mc_pause();
30188+}
30189+
30190+static inline void mc_spinlock_unlock(mc_spinlock_t *sl)
30191+{
30192+ __sync_lock_release(&sl->locked);
30193+}
30194+
30195+
30196+static int mc_status_to_error(enum mc_cmd_status status)
30197+{
30198+ switch (status) {
30199+ case MC_CMD_STATUS_OK:
30200+ return 0;
30201+ case MC_CMD_STATUS_AUTH_ERR:
30202+ return -EACCES; /* Token error */
30203+ case MC_CMD_STATUS_NO_PRIVILEGE:
30204+ return -EPERM; /* Permission denied */
30205+ case MC_CMD_STATUS_DMA_ERR:
30206+ return -EIO; /* Input/Output error */
30207+ case MC_CMD_STATUS_CONFIG_ERR:
30208+ return -EINVAL; /* Device not configured */
30209+ case MC_CMD_STATUS_TIMEOUT:
30210+ return -ETIMEDOUT; /* Operation timed out */
30211+ case MC_CMD_STATUS_NO_RESOURCE:
30212+ return -ENAVAIL; /* Resource temporarily unavailable */
30213+ case MC_CMD_STATUS_NO_MEMORY:
30214+ return -ENOMEM; /* Cannot allocate memory */
30215+ case MC_CMD_STATUS_BUSY:
30216+ return -EBUSY; /* Device busy */
30217+ case MC_CMD_STATUS_UNSUPPORTED_OP:
30218+ return -ENOTSUP; /* Operation not supported by device */
30219+ case MC_CMD_STATUS_INVALID_STATE:
30220+ return -ENODEV; /* Invalid device state */
30221+ default:
30222+ break;
30223+ }
30224+
30225+ /* Not expected to reach here */
30226+ return -EINVAL;
30227+}
30228+
30229+int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd)
30230+{
30231+ enum mc_cmd_status status;
30232+
30233+ if (!mc_io || !mc_io->regs)
30234+ return -EACCES;
30235+
30236+ /* --- Call lock function here in case portal is shared --- */
30237+ mc_spinlock_lock(&mc_portal_lock);
30238+
30239+ mc_write_command(mc_io->regs, cmd);
30240+
30241+ /* Spin until status changes */
30242+ do {
30243+ status = MC_CMD_HDR_READ_STATUS(ioread64(mc_io->regs));
30244+
30245+ /* --- Call wait function here to prevent blocking ---
30246+ * Change the loop condition accordingly to exit on timeout.
30247+ */
30248+ } while (status == MC_CMD_STATUS_READY);
30249+
30250+ /* Read the response back into the command buffer */
30251+ mc_read_response(mc_io->regs, cmd);
30252+
30253+ /* --- Call unlock function here in case portal is shared --- */
30254+ mc_spinlock_unlock(&mc_portal_lock);
30255+
30256+ return mc_status_to_error(status);
30257+}
30258+
30259diff --git a/drivers/net/dpaa2/qbman/driver/qbman_debug.c b/drivers/net/dpaa2/qbman/driver/qbman_debug.c
30260new file mode 100644
30261index 0000000..e205681
30262--- /dev/null
30263+++ b/drivers/net/dpaa2/qbman/driver/qbman_debug.c
30264@@ -0,0 +1,926 @@
30265+/* Copyright (C) 2015 Freescale Semiconductor, Inc.
30266+ *
30267+ * Redistribution and use in source and binary forms, with or without
30268+ * modification, are permitted provided that the following conditions are met:
30269+ * * Redistributions of source code must retain the above copyright
30270+ * notice, this list of conditions and the following disclaimer.
30271+ * * Redistributions in binary form must reproduce the above copyright
30272+ * notice, this list of conditions and the following disclaimer in the
30273+ * documentation and/or other materials provided with the distribution.
30274+ * * Neither the name of Freescale Semiconductor nor the
30275+ * names of its contributors may be used to endorse or promote products
30276+ * derived from this software without specific prior written permission.
30277+ *
30278+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
30279+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
30280+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30281+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
30282+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30283+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30284+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30285+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30286+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30287+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30288+ */
30289+
30290+#include "qbman_portal.h"
30291+#include "qbman_debug.h"
30292+#include <drivers/fsl_qbman_portal.h>
30293+
30294+/* QBMan portal management command code */
30295+#define QBMAN_BP_QUERY 0x32
30296+#define QBMAN_FQ_QUERY 0x44
30297+#define QBMAN_FQ_QUERY_NP 0x45
30298+#define QBMAN_WQ_QUERY 0x47
30299+#define QBMAN_CGR_QUERY 0x51
30300+#define QBMAN_WRED_QUERY 0x54
30301+#define QBMAN_CGR_STAT_QUERY 0x55
30302+#define QBMAN_CGR_STAT_QUERY_CLR 0x56
30303+
30304+enum qbman_attr_usage_e {
30305+ qbman_attr_usage_fq,
30306+ qbman_attr_usage_bpool,
30307+ qbman_attr_usage_cgr,
30308+ qbman_attr_usage_wqchan
30309+};
30310+
30311+struct int_qbman_attr {
30312+ uint32_t words[32];
30313+ enum qbman_attr_usage_e usage;
30314+};
30315+
30316+#define attr_type_set(a, e) \
30317+{ \
30318+ struct qbman_attr *__attr = a; \
30319+ enum qbman_attr_usage_e __usage = e; \
30320+ ((struct int_qbman_attr *)__attr)->usage = __usage; \
30321+}
30322+
30323+#define ATTR32(d) (&(d)->dont_manipulate_directly[0])
30324+#define ATTR32_1(d) (&(d)->dont_manipulate_directly[16])
30325+
30326+static struct qb_attr_code code_bp_bpid = QB_CODE(0, 16, 16);
30327+static struct qb_attr_code code_bp_bdi = QB_CODE(1, 16, 1);
30328+static struct qb_attr_code code_bp_va = QB_CODE(1, 17, 1);
30329+static struct qb_attr_code code_bp_wae = QB_CODE(1, 18, 1);
30330+static struct qb_attr_code code_bp_swdet = QB_CODE(4, 0, 16);
30331+static struct qb_attr_code code_bp_swdxt = QB_CODE(4, 16, 16);
30332+static struct qb_attr_code code_bp_hwdet = QB_CODE(5, 0, 16);
30333+static struct qb_attr_code code_bp_hwdxt = QB_CODE(5, 16, 16);
30334+static struct qb_attr_code code_bp_swset = QB_CODE(6, 0, 16);
30335+static struct qb_attr_code code_bp_swsxt = QB_CODE(6, 16, 16);
30336+static struct qb_attr_code code_bp_vbpid = QB_CODE(7, 0, 14);
30337+static struct qb_attr_code code_bp_icid = QB_CODE(7, 16, 15);
30338+static struct qb_attr_code code_bp_pl = QB_CODE(7, 31, 1);
30339+static struct qb_attr_code code_bp_bpscn_addr_lo = QB_CODE(8, 0, 32);
30340+static struct qb_attr_code code_bp_bpscn_addr_hi = QB_CODE(9, 0, 32);
30341+static struct qb_attr_code code_bp_bpscn_ctx_lo = QB_CODE(10, 0, 32);
30342+static struct qb_attr_code code_bp_bpscn_ctx_hi = QB_CODE(11, 0, 32);
30343+static struct qb_attr_code code_bp_hw_targ = QB_CODE(12, 0, 16);
30344+static struct qb_attr_code code_bp_state = QB_CODE(1, 24, 3);
30345+static struct qb_attr_code code_bp_fill = QB_CODE(2 , 0, 32);
30346+static struct qb_attr_code code_bp_hdptr = QB_CODE(3, 0, 32);
30347+static struct qb_attr_code code_bp_sdcnt = QB_CODE(13, 0, 8);
30348+static struct qb_attr_code code_bp_hdcnt = QB_CODE(13, 8, 8);
30349+static struct qb_attr_code code_bp_sscnt = QB_CODE(13, 16, 8);
30350+
30351+static void qbman_bp_attr_clear(struct qbman_attr *a)
30352+{
30353+ memset(a, 0, sizeof(*a));
30354+ attr_type_set(a, qbman_attr_usage_bpool);
30355+}
30356+
30357+int qbman_bp_query(struct qbman_swp *s, uint32_t bpid,
30358+ struct qbman_attr *a)
30359+{
30360+ uint32_t *p;
30361+ uint32_t rslt;
30362+ uint32_t *attr = ATTR32(a);
30363+
30364+ qbman_bp_attr_clear(a);
30365+
30366+ /* Start the management command */
30367+ p = qbman_swp_mc_start(s);
30368+ if (!p)
30369+ return -EBUSY;
30370+
30371+ /* Encode the caller-provided attributes */
30372+ qb_attr_code_encode(&code_bp_bpid, p, bpid);
30373+
30374+ /* Complete the management command */
30375+ p = qbman_swp_mc_complete(s, p, p[0] | QBMAN_BP_QUERY);
30376+
30377+ /* Decode the outcome */
30378+ rslt = qb_attr_code_decode(&code_generic_rslt, p);
30379+ BUG_ON(qb_attr_code_decode(&code_generic_verb, p) != QBMAN_BP_QUERY);
30380+
30381+ /* Determine success or failure */
30382+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
30383+ pr_err("Query of BPID 0x%x failed, code=0x%02x\n", bpid, rslt);
30384+ return -EIO;
30385+ }
30386+
30387+ /* For the query, word[0] of the result contains only the
30388+ * verb/rslt fields, so skip word[0].
30389+ */
30390+ word_copy(&attr[1], &p[1], 15);
30391+ return 0;
30392+}
30393+
30394+void qbman_bp_attr_get_bdi(struct qbman_attr *a, int *bdi, int *va, int *wae)
30395+{
30396+ uint32_t *p = ATTR32(a);
30397+
30398+ *bdi = !!qb_attr_code_decode(&code_bp_bdi, p);
30399+ *va = !!qb_attr_code_decode(&code_bp_va, p);
30400+ *wae = !!qb_attr_code_decode(&code_bp_wae, p);
30401+}
30402+
30403+static uint32_t qbman_bp_thresh_to_value(uint32_t val)
30404+{
30405+ return (val & 0xff) << ((val & 0xf00) >> 8);
30406+}
30407+
30408+void qbman_bp_attr_get_swdet(struct qbman_attr *a, uint32_t *swdet)
30409+{
30410+ uint32_t *p = ATTR32(a);
30411+
30412+ *swdet = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swdet,
30413+ p));
30414+}
30415+void qbman_bp_attr_get_swdxt(struct qbman_attr *a, uint32_t *swdxt)
30416+{
30417+ uint32_t *p = ATTR32(a);
30418+
30419+ *swdxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swdxt,
30420+ p));
30421+}
30422+void qbman_bp_attr_get_hwdet(struct qbman_attr *a, uint32_t *hwdet)
30423+{
30424+ uint32_t *p = ATTR32(a);
30425+
30426+ *hwdet = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_hwdet,
30427+ p));
30428+}
30429+void qbman_bp_attr_get_hwdxt(struct qbman_attr *a, uint32_t *hwdxt)
30430+{
30431+ uint32_t *p = ATTR32(a);
30432+
30433+ *hwdxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_hwdxt,
30434+ p));
30435+}
30436+
30437+void qbman_bp_attr_get_swset(struct qbman_attr *a, uint32_t *swset)
30438+{
30439+ uint32_t *p = ATTR32(a);
30440+
30441+ *swset = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swset,
30442+ p));
30443+}
30444+
30445+void qbman_bp_attr_get_swsxt(struct qbman_attr *a, uint32_t *swsxt)
30446+{
30447+ uint32_t *p = ATTR32(a);
30448+
30449+ *swsxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swsxt,
30450+ p));
30451+}
30452+
30453+void qbman_bp_attr_get_vbpid(struct qbman_attr *a, uint32_t *vbpid)
30454+{
30455+ uint32_t *p = ATTR32(a);
30456+
30457+ *vbpid = qb_attr_code_decode(&code_bp_vbpid, p);
30458+}
30459+
30460+void qbman_bp_attr_get_icid(struct qbman_attr *a, uint32_t *icid, int *pl)
30461+{
30462+ uint32_t *p = ATTR32(a);
30463+
30464+ *icid = qb_attr_code_decode(&code_bp_icid, p);
30465+ *pl = !!qb_attr_code_decode(&code_bp_pl, p);
30466+}
30467+
30468+void qbman_bp_attr_get_bpscn_addr(struct qbman_attr *a, uint64_t *bpscn_addr)
30469+{
30470+ uint32_t *p = ATTR32(a);
30471+
30472+ *bpscn_addr = ((uint64_t)qb_attr_code_decode(&code_bp_bpscn_addr_hi,
30473+ p) << 32) |
30474+ (uint64_t)qb_attr_code_decode(&code_bp_bpscn_addr_lo,
30475+ p);
30476+}
30477+
30478+void qbman_bp_attr_get_bpscn_ctx(struct qbman_attr *a, uint64_t *bpscn_ctx)
30479+{
30480+ uint32_t *p = ATTR32(a);
30481+
30482+ *bpscn_ctx = ((uint64_t)qb_attr_code_decode(&code_bp_bpscn_ctx_hi, p)
30483+ << 32) |
30484+ (uint64_t)qb_attr_code_decode(&code_bp_bpscn_ctx_lo,
30485+ p);
30486+}
30487+
30488+void qbman_bp_attr_get_hw_targ(struct qbman_attr *a, uint32_t *hw_targ)
30489+{
30490+ uint32_t *p = ATTR32(a);
30491+
30492+ *hw_targ = qb_attr_code_decode(&code_bp_hw_targ, p);
30493+}
30494+
30495+int qbman_bp_info_has_free_bufs(struct qbman_attr *a)
30496+{
30497+ uint32_t *p = ATTR32(a);
30498+
30499+ return !(int)(qb_attr_code_decode(&code_bp_state, p) & 0x1);
30500+}
30501+
30502+int qbman_bp_info_is_depleted(struct qbman_attr *a)
30503+{
30504+ uint32_t *p = ATTR32(a);
30505+
30506+ return (int)(qb_attr_code_decode(&code_bp_state, p) & 0x2);
30507+}
30508+
30509+int qbman_bp_info_is_surplus(struct qbman_attr *a)
30510+{
30511+ uint32_t *p = ATTR32(a);
30512+
30513+ return (int)(qb_attr_code_decode(&code_bp_state, p) & 0x4);
30514+}
30515+
30516+uint32_t qbman_bp_info_num_free_bufs(struct qbman_attr *a)
30517+{
30518+ uint32_t *p = ATTR32(a);
30519+
30520+ return qb_attr_code_decode(&code_bp_fill, p);
30521+}
30522+
30523+uint32_t qbman_bp_info_hdptr(struct qbman_attr *a)
30524+{
30525+ uint32_t *p = ATTR32(a);
30526+
30527+ return qb_attr_code_decode(&code_bp_hdptr, p);
30528+}
30529+
30530+uint32_t qbman_bp_info_sdcnt(struct qbman_attr *a)
30531+{
30532+ uint32_t *p = ATTR32(a);
30533+
30534+ return qb_attr_code_decode(&code_bp_sdcnt, p);
30535+}
30536+
30537+uint32_t qbman_bp_info_hdcnt(struct qbman_attr *a)
30538+{
30539+ uint32_t *p = ATTR32(a);
30540+
30541+ return qb_attr_code_decode(&code_bp_hdcnt, p);
30542+}
30543+
30544+uint32_t qbman_bp_info_sscnt(struct qbman_attr *a)
30545+{
30546+ uint32_t *p = ATTR32(a);
30547+
30548+ return qb_attr_code_decode(&code_bp_sscnt, p);
30549+}
30550+
30551+static struct qb_attr_code code_fq_fqid = QB_CODE(1, 0, 24);
30552+static struct qb_attr_code code_fq_cgrid = QB_CODE(2, 16, 16);
30553+static struct qb_attr_code code_fq_destwq = QB_CODE(3, 0, 15);
30554+static struct qb_attr_code code_fq_fqctrl = QB_CODE(3, 24, 8);
30555+static struct qb_attr_code code_fq_icscred = QB_CODE(4, 0, 15);
30556+static struct qb_attr_code code_fq_tdthresh = QB_CODE(4, 16, 13);
30557+static struct qb_attr_code code_fq_oa_len = QB_CODE(5, 0, 12);
30558+static struct qb_attr_code code_fq_oa_ics = QB_CODE(5, 14, 1);
30559+static struct qb_attr_code code_fq_oa_cgr = QB_CODE(5, 15, 1);
30560+static struct qb_attr_code code_fq_mctl_bdi = QB_CODE(5, 24, 1);
30561+static struct qb_attr_code code_fq_mctl_ff = QB_CODE(5, 25, 1);
30562+static struct qb_attr_code code_fq_mctl_va = QB_CODE(5, 26, 1);
30563+static struct qb_attr_code code_fq_mctl_ps = QB_CODE(5, 27, 1);
30564+static struct qb_attr_code code_fq_ctx_lower32 = QB_CODE(6, 0, 32);
30565+static struct qb_attr_code code_fq_ctx_upper32 = QB_CODE(7, 0, 32);
30566+static struct qb_attr_code code_fq_icid = QB_CODE(8, 0, 15);
30567+static struct qb_attr_code code_fq_pl = QB_CODE(8, 15, 1);
30568+static struct qb_attr_code code_fq_vfqid = QB_CODE(9, 0, 24);
30569+static struct qb_attr_code code_fq_erfqid = QB_CODE(10, 0, 24);
30570+
30571+static void qbman_fq_attr_clear(struct qbman_attr *a)
30572+{
30573+ memset(a, 0, sizeof(*a));
30574+ attr_type_set(a, qbman_attr_usage_fq);
30575+}
30576+
30577+/* FQ query function for programmable fields */
30578+int qbman_fq_query(struct qbman_swp *s, uint32_t fqid, struct qbman_attr *desc)
30579+{
30580+ uint32_t *p;
30581+ uint32_t rslt;
30582+ uint32_t *d = ATTR32(desc);
30583+
30584+ qbman_fq_attr_clear(desc);
30585+
30586+ p = qbman_swp_mc_start(s);
30587+ if (!p)
30588+ return -EBUSY;
30589+ qb_attr_code_encode(&code_fq_fqid, p, fqid);
30590+ p = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY);
30591+
30592+ /* Decode the outcome */
30593+ rslt = qb_attr_code_decode(&code_generic_rslt, p);
30594+ BUG_ON(qb_attr_code_decode(&code_generic_verb, p) != QBMAN_FQ_QUERY);
30595+
30596+ /* Determine success or failure */
30597+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
30598+ pr_err("Query of FQID 0x%x failed, code=0x%02x\n",
30599+ fqid, rslt);
30600+ return -EIO;
30601+ }
30602+ /* For the configure, word[0] of the command contains only the WE-mask.
30603+ * For the query, word[0] of the result contains only the verb/rslt
30604+ * fields. Skip word[0] in the latter case. */
30605+ word_copy(&d[1], &p[1], 15);
30606+ return 0;
30607+}
30608+
30609+void qbman_fq_attr_get_fqctrl(struct qbman_attr *d, uint32_t *fqctrl)
30610+{
30611+ uint32_t *p = ATTR32(d);
30612+
30613+ *fqctrl = qb_attr_code_decode(&code_fq_fqctrl, p);
30614+}
30615+
30616+void qbman_fq_attr_get_cgrid(struct qbman_attr *d, uint32_t *cgrid)
30617+{
30618+ uint32_t *p = ATTR32(d);
30619+
30620+ *cgrid = qb_attr_code_decode(&code_fq_cgrid, p);
30621+}
30622+
30623+void qbman_fq_attr_get_destwq(struct qbman_attr *d, uint32_t *destwq)
30624+{
30625+ uint32_t *p = ATTR32(d);
30626+
30627+ *destwq = qb_attr_code_decode(&code_fq_destwq, p);
30628+}
30629+
30630+void qbman_fq_attr_get_icscred(struct qbman_attr *d, uint32_t *icscred)
30631+{
30632+ uint32_t *p = ATTR32(d);
30633+
30634+ *icscred = qb_attr_code_decode(&code_fq_icscred, p);
30635+}
30636+
30637+static struct qb_attr_code code_tdthresh_exp = QB_CODE(0, 0, 5);
30638+static struct qb_attr_code code_tdthresh_mant = QB_CODE(0, 5, 8);
30639+static uint32_t qbman_thresh_to_value(uint32_t val)
30640+{
30641+ uint32_t m, e;
30642+
30643+ m = qb_attr_code_decode(&code_tdthresh_mant, &val);
30644+ e = qb_attr_code_decode(&code_tdthresh_exp, &val);
30645+ return m << e;
30646+}
30647+
30648+void qbman_fq_attr_get_tdthresh(struct qbman_attr *d, uint32_t *tdthresh)
30649+{
30650+ uint32_t *p = ATTR32(d);
30651+
30652+ *tdthresh = qbman_thresh_to_value(qb_attr_code_decode(&code_fq_tdthresh,
30653+ p));
30654+}
30655+
30656+void qbman_fq_attr_get_oa(struct qbman_attr *d,
30657+ int *oa_ics, int *oa_cgr, int32_t *oa_len)
30658+{
30659+ uint32_t *p = ATTR32(d);
30660+
30661+ *oa_ics = !!qb_attr_code_decode(&code_fq_oa_ics, p);
30662+ *oa_cgr = !!qb_attr_code_decode(&code_fq_oa_cgr, p);
30663+ *oa_len = qb_attr_code_makesigned(&code_fq_oa_len,
30664+ qb_attr_code_decode(&code_fq_oa_len, p));
30665+}
30666+
30667+void qbman_fq_attr_get_mctl(struct qbman_attr *d,
30668+ int *bdi, int *ff, int *va, int *ps)
30669+{
30670+ uint32_t *p = ATTR32(d);
30671+
30672+ *bdi = !!qb_attr_code_decode(&code_fq_mctl_bdi, p);
30673+ *ff = !!qb_attr_code_decode(&code_fq_mctl_ff, p);
30674+ *va = !!qb_attr_code_decode(&code_fq_mctl_va, p);
30675+ *ps = !!qb_attr_code_decode(&code_fq_mctl_ps, p);
30676+}
30677+
30678+void qbman_fq_attr_get_ctx(struct qbman_attr *d, uint32_t *hi, uint32_t *lo)
30679+{
30680+ uint32_t *p = ATTR32(d);
30681+
30682+ *hi = qb_attr_code_decode(&code_fq_ctx_upper32, p);
30683+ *lo = qb_attr_code_decode(&code_fq_ctx_lower32, p);
30684+}
30685+
30686+void qbman_fq_attr_get_icid(struct qbman_attr *d, uint32_t *icid, int *pl)
30687+{
30688+ uint32_t *p = ATTR32(d);
30689+
30690+ *icid = qb_attr_code_decode(&code_fq_icid, p);
30691+ *pl = !!qb_attr_code_decode(&code_fq_pl, p);
30692+}
30693+
30694+void qbman_fq_attr_get_vfqid(struct qbman_attr *d, uint32_t *vfqid)
30695+{
30696+ uint32_t *p = ATTR32(d);
30697+
30698+ *vfqid = qb_attr_code_decode(&code_fq_vfqid, p);
30699+}
30700+
30701+void qbman_fq_attr_get_erfqid(struct qbman_attr *d, uint32_t *erfqid)
30702+{
30703+ uint32_t *p = ATTR32(d);
30704+
30705+ *erfqid = qb_attr_code_decode(&code_fq_erfqid, p);
30706+}
30707+
30708+/* Query FQ Non-Programmalbe Fields */
30709+static struct qb_attr_code code_fq_np_state = QB_CODE(0, 16, 3);
30710+static struct qb_attr_code code_fq_np_fe = QB_CODE(0, 19, 1);
30711+static struct qb_attr_code code_fq_np_x = QB_CODE(0, 20, 1);
30712+static struct qb_attr_code code_fq_np_r = QB_CODE(0, 21, 1);
30713+static struct qb_attr_code code_fq_np_oe = QB_CODE(0, 22, 1);
30714+static struct qb_attr_code code_fq_np_frm_cnt = QB_CODE(6, 0, 24);
30715+static struct qb_attr_code code_fq_np_byte_cnt = QB_CODE(7, 0, 32);
30716+
30717+int qbman_fq_query_state(struct qbman_swp *s, uint32_t fqid,
30718+ struct qbman_attr *state)
30719+{
30720+ uint32_t *p;
30721+ uint32_t rslt;
30722+ uint32_t *d = ATTR32(state);
30723+
30724+ qbman_fq_attr_clear(state);
30725+
30726+ p = qbman_swp_mc_start(s);
30727+ if (!p)
30728+ return -EBUSY;
30729+ qb_attr_code_encode(&code_fq_fqid, p, fqid);
30730+ p = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY_NP);
30731+
30732+ /* Decode the outcome */
30733+ rslt = qb_attr_code_decode(&code_generic_rslt, p);
30734+ BUG_ON(qb_attr_code_decode(&code_generic_verb, p) != QBMAN_FQ_QUERY_NP);
30735+
30736+ /* Determine success or failure */
30737+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
30738+ pr_err("Query NP fields of FQID 0x%x failed, code=0x%02x\n",
30739+ fqid, rslt);
30740+ return -EIO;
30741+ }
30742+ word_copy(&d[0], &p[0], 16);
30743+ return 0;
30744+}
30745+
30746+uint32_t qbman_fq_state_schedstate(const struct qbman_attr *state)
30747+{
30748+ const uint32_t *p = ATTR32(state);
30749+
30750+ return qb_attr_code_decode(&code_fq_np_state, p);
30751+}
30752+
30753+int qbman_fq_state_force_eligible(const struct qbman_attr *state)
30754+{
30755+ const uint32_t *p = ATTR32(state);
30756+
30757+ return !!qb_attr_code_decode(&code_fq_np_fe, p);
30758+}
30759+
30760+int qbman_fq_state_xoff(const struct qbman_attr *state)
30761+{
30762+ const uint32_t *p = ATTR32(state);
30763+
30764+ return !!qb_attr_code_decode(&code_fq_np_x, p);
30765+}
30766+
30767+int qbman_fq_state_retirement_pending(const struct qbman_attr *state)
30768+{
30769+ const uint32_t *p = ATTR32(state);
30770+
30771+ return !!qb_attr_code_decode(&code_fq_np_r, p);
30772+}
30773+
30774+int qbman_fq_state_overflow_error(const struct qbman_attr *state)
30775+{
30776+ const uint32_t *p = ATTR32(state);
30777+
30778+ return !!qb_attr_code_decode(&code_fq_np_oe, p);
30779+}
30780+
30781+uint32_t qbman_fq_state_frame_count(const struct qbman_attr *state)
30782+{
30783+ const uint32_t *p = ATTR32(state);
30784+
30785+ return qb_attr_code_decode(&code_fq_np_frm_cnt, p);
30786+}
30787+
30788+uint32_t qbman_fq_state_byte_count(const struct qbman_attr *state)
30789+{
30790+ const uint32_t *p = ATTR32(state);
30791+
30792+ return qb_attr_code_decode(&code_fq_np_byte_cnt, p);
30793+}
30794+
30795+/* Query CGR */
30796+static struct qb_attr_code code_cgr_cgid = QB_CODE(0, 16, 16);
30797+static struct qb_attr_code code_cgr_cscn_wq_en_enter = QB_CODE(2, 0, 1);
30798+static struct qb_attr_code code_cgr_cscn_wq_en_exit = QB_CODE(2, 1, 1);
30799+static struct qb_attr_code code_cgr_cscn_wq_icd = QB_CODE(2, 2, 1);
30800+static struct qb_attr_code code_cgr_mode = QB_CODE(3, 16, 2);
30801+static struct qb_attr_code code_cgr_rej_cnt_mode = QB_CODE(3, 18, 1);
30802+static struct qb_attr_code code_cgr_cscn_bdi = QB_CODE(3, 19, 1);
30803+static struct qb_attr_code code_cgr_cscn_wr_en_enter = QB_CODE(3, 24, 1);
30804+static struct qb_attr_code code_cgr_cscn_wr_en_exit = QB_CODE(3, 25, 1);
30805+static struct qb_attr_code code_cgr_cg_wr_ae = QB_CODE(3, 26, 1);
30806+static struct qb_attr_code code_cgr_cscn_dcp_en = QB_CODE(3, 27, 1);
30807+static struct qb_attr_code code_cgr_cg_wr_va = QB_CODE(3, 28, 1);
30808+static struct qb_attr_code code_cgr_i_cnt_wr_en = QB_CODE(4, 0, 1);
30809+static struct qb_attr_code code_cgr_i_cnt_wr_bnd = QB_CODE(4, 1, 5);
30810+static struct qb_attr_code code_cgr_td_en = QB_CODE(4, 8, 1);
30811+static struct qb_attr_code code_cgr_cs_thres = QB_CODE(4, 16, 13);
30812+static struct qb_attr_code code_cgr_cs_thres_x = QB_CODE(5, 0, 13);
30813+static struct qb_attr_code code_cgr_td_thres = QB_CODE(5, 16, 13);
30814+static struct qb_attr_code code_cgr_cscn_tdcp = QB_CODE(6, 0, 16);
30815+static struct qb_attr_code code_cgr_cscn_wqid = QB_CODE(6, 16, 16);
30816+static struct qb_attr_code code_cgr_cscn_vcgid = QB_CODE(7, 0, 16);
30817+static struct qb_attr_code code_cgr_cg_icid = QB_CODE(7, 16, 15);
30818+static struct qb_attr_code code_cgr_cg_pl = QB_CODE(7, 31, 1);
30819+static struct qb_attr_code code_cgr_cg_wr_addr_lo = QB_CODE(8, 0, 32);
30820+static struct qb_attr_code code_cgr_cg_wr_addr_hi = QB_CODE(9, 0, 32);
30821+static struct qb_attr_code code_cgr_cscn_ctx_lo = QB_CODE(10, 0, 32);
30822+static struct qb_attr_code code_cgr_cscn_ctx_hi = QB_CODE(11, 0, 32);
30823+
30824+static void qbman_cgr_attr_clear(struct qbman_attr *a)
30825+{
30826+ memset(a, 0, sizeof(*a));
30827+ attr_type_set(a, qbman_attr_usage_cgr);
30828+}
30829+
30830+int qbman_cgr_query(struct qbman_swp *s, uint32_t cgid, struct qbman_attr *attr)
30831+{
30832+ uint32_t *p;
30833+ uint32_t verb, rslt;
30834+ uint32_t *d[2];
30835+ int i;
30836+ uint32_t query_verb;
30837+
30838+ d[0] = ATTR32(attr);
30839+ d[1] = ATTR32_1(attr);
30840+
30841+ qbman_cgr_attr_clear(attr);
30842+
30843+ for (i = 0; i < 2; i++) {
30844+ p = qbman_swp_mc_start(s);
30845+ if (!p)
30846+ return -EBUSY;
30847+ query_verb = i ? QBMAN_WRED_QUERY : QBMAN_CGR_QUERY;
30848+
30849+ qb_attr_code_encode(&code_cgr_cgid, p, cgid);
30850+ p = qbman_swp_mc_complete(s, p, p[0] | query_verb);
30851+
30852+ /* Decode the outcome */
30853+ verb = qb_attr_code_decode(&code_generic_verb, p);
30854+ rslt = qb_attr_code_decode(&code_generic_rslt, p);
30855+ BUG_ON(verb != query_verb);
30856+
30857+ /* Determine success or failure */
30858+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
30859+ pr_err("Query CGID 0x%x failed,", cgid);
30860+ pr_err(" verb=0x%02x, code=0x%02x\n", verb, rslt);
30861+ return -EIO;
30862+ }
30863+ /* For the configure, word[0] of the command contains only the
30864+ * verb/cgid. For the query, word[0] of the result contains
30865+ * only the verb/rslt fields. Skip word[0] in the latter case.
30866+ */
30867+ word_copy(&d[i][1], &p[1], 15);
30868+ }
30869+ return 0;
30870+}
30871+
30872+void qbman_cgr_attr_get_ctl1(struct qbman_attr *d, int *cscn_wq_en_enter,
30873+ int *cscn_wq_en_exit, int *cscn_wq_icd)
30874+ {
30875+ uint32_t *p = ATTR32(d);
30876+ *cscn_wq_en_enter = !!qb_attr_code_decode(&code_cgr_cscn_wq_en_enter,
30877+ p);
30878+ *cscn_wq_en_exit = !!qb_attr_code_decode(&code_cgr_cscn_wq_en_exit, p);
30879+ *cscn_wq_icd = !!qb_attr_code_decode(&code_cgr_cscn_wq_icd, p);
30880+}
30881+
30882+void qbman_cgr_attr_get_mode(struct qbman_attr *d, uint32_t *mode,
30883+ int *rej_cnt_mode, int *cscn_bdi)
30884+{
30885+ uint32_t *p = ATTR32(d);
30886+ *mode = qb_attr_code_decode(&code_cgr_mode, p);
30887+ *rej_cnt_mode = !!qb_attr_code_decode(&code_cgr_rej_cnt_mode, p);
30888+ *cscn_bdi = !!qb_attr_code_decode(&code_cgr_cscn_bdi, p);
30889+}
30890+
30891+void qbman_cgr_attr_get_ctl2(struct qbman_attr *d, int *cscn_wr_en_enter,
30892+ int *cscn_wr_en_exit, int *cg_wr_ae,
30893+ int *cscn_dcp_en, int *cg_wr_va)
30894+{
30895+ uint32_t *p = ATTR32(d);
30896+ *cscn_wr_en_enter = !!qb_attr_code_decode(&code_cgr_cscn_wr_en_enter,
30897+ p);
30898+ *cscn_wr_en_exit = !!qb_attr_code_decode(&code_cgr_cscn_wr_en_exit, p);
30899+ *cg_wr_ae = !!qb_attr_code_decode(&code_cgr_cg_wr_ae, p);
30900+ *cscn_dcp_en = !!qb_attr_code_decode(&code_cgr_cscn_dcp_en, p);
30901+ *cg_wr_va = !!qb_attr_code_decode(&code_cgr_cg_wr_va, p);
30902+}
30903+
30904+void qbman_cgr_attr_get_iwc(struct qbman_attr *d, int *i_cnt_wr_en,
30905+ uint32_t *i_cnt_wr_bnd)
30906+{
30907+ uint32_t *p = ATTR32(d);
30908+ *i_cnt_wr_en = !!qb_attr_code_decode(&code_cgr_i_cnt_wr_en, p);
30909+ *i_cnt_wr_bnd = qb_attr_code_decode(&code_cgr_i_cnt_wr_bnd, p);
30910+}
30911+
30912+void qbman_cgr_attr_get_tdc(struct qbman_attr *d, int *td_en)
30913+{
30914+ uint32_t *p = ATTR32(d);
30915+ *td_en = !!qb_attr_code_decode(&code_cgr_td_en, p);
30916+}
30917+
30918+void qbman_cgr_attr_get_cs_thres(struct qbman_attr *d, uint32_t *cs_thres)
30919+{
30920+ uint32_t *p = ATTR32(d);
30921+ *cs_thres = qbman_thresh_to_value(qb_attr_code_decode(
30922+ &code_cgr_cs_thres, p));
30923+}
30924+
30925+void qbman_cgr_attr_get_cs_thres_x(struct qbman_attr *d,
30926+ uint32_t *cs_thres_x)
30927+{
30928+ uint32_t *p = ATTR32(d);
30929+ *cs_thres_x = qbman_thresh_to_value(qb_attr_code_decode(
30930+ &code_cgr_cs_thres_x, p));
30931+}
30932+
30933+void qbman_cgr_attr_get_td_thres(struct qbman_attr *d, uint32_t *td_thres)
30934+{
30935+ uint32_t *p = ATTR32(d);
30936+ *td_thres = qbman_thresh_to_value(qb_attr_code_decode(
30937+ &code_cgr_td_thres, p));
30938+}
30939+
30940+void qbman_cgr_attr_get_cscn_tdcp(struct qbman_attr *d, uint32_t *cscn_tdcp)
30941+{
30942+ uint32_t *p = ATTR32(d);
30943+ *cscn_tdcp = qb_attr_code_decode(&code_cgr_cscn_tdcp, p);
30944+}
30945+
30946+void qbman_cgr_attr_get_cscn_wqid(struct qbman_attr *d, uint32_t *cscn_wqid)
30947+{
30948+ uint32_t *p = ATTR32(d);
30949+ *cscn_wqid = qb_attr_code_decode(&code_cgr_cscn_wqid, p);
30950+}
30951+
30952+void qbman_cgr_attr_get_cscn_vcgid(struct qbman_attr *d,
30953+ uint32_t *cscn_vcgid)
30954+{
30955+ uint32_t *p = ATTR32(d);
30956+ *cscn_vcgid = qb_attr_code_decode(&code_cgr_cscn_vcgid, p);
30957+}
30958+
30959+void qbman_cgr_attr_get_cg_icid(struct qbman_attr *d, uint32_t *icid,
30960+ int *pl)
30961+{
30962+ uint32_t *p = ATTR32(d);
30963+ *icid = qb_attr_code_decode(&code_cgr_cg_icid, p);
30964+ *pl = !!qb_attr_code_decode(&code_cgr_cg_pl, p);
30965+}
30966+
30967+void qbman_cgr_attr_get_cg_wr_addr(struct qbman_attr *d,
30968+ uint64_t *cg_wr_addr)
30969+{
30970+ uint32_t *p = ATTR32(d);
30971+ *cg_wr_addr = ((uint64_t)qb_attr_code_decode(&code_cgr_cg_wr_addr_hi,
30972+ p) << 32) |
30973+ (uint64_t)qb_attr_code_decode(&code_cgr_cg_wr_addr_lo,
30974+ p);
30975+}
30976+
30977+void qbman_cgr_attr_get_cscn_ctx(struct qbman_attr *d, uint64_t *cscn_ctx)
30978+{
30979+ uint32_t *p = ATTR32(d);
30980+ *cscn_ctx = ((uint64_t)qb_attr_code_decode(&code_cgr_cscn_ctx_hi, p)
30981+ << 32) |
30982+ (uint64_t)qb_attr_code_decode(&code_cgr_cscn_ctx_lo, p);
30983+}
30984+
30985+#define WRED_EDP_WORD(n) (18 + n/4)
30986+#define WRED_EDP_OFFSET(n) (8 * (n % 4))
30987+#define WRED_PARM_DP_WORD(n) (n + 20)
30988+#define WRED_WE_EDP(n) (16 + n * 2)
30989+#define WRED_WE_PARM_DP(n) (17 + n * 2)
30990+void qbman_cgr_attr_wred_get_edp(struct qbman_attr *d, uint32_t idx,
30991+ int *edp)
30992+{
30993+ uint32_t *p = ATTR32(d);
30994+ struct qb_attr_code code_wred_edp = QB_CODE(WRED_EDP_WORD(idx),
30995+ WRED_EDP_OFFSET(idx), 8);
30996+ *edp = (int)qb_attr_code_decode(&code_wred_edp, p);
30997+}
30998+
30999+void qbman_cgr_attr_wred_dp_decompose(uint32_t dp, uint64_t *minth,
31000+ uint64_t *maxth, uint8_t *maxp)
31001+{
31002+ uint8_t ma, mn, step_i, step_s, pn;
31003+
31004+ ma = (uint8_t)(dp >> 24);
31005+ mn = (uint8_t)(dp >> 19) & 0x1f;
31006+ step_i = (uint8_t)(dp >> 11);
31007+ step_s = (uint8_t)(dp >> 6) & 0x1f;
31008+ pn = (uint8_t)dp & 0x3f;
31009+
31010+ *maxp = (uint8_t)(((pn<<2) * 100)/256);
31011+
31012+ if (mn == 0)
31013+ *maxth = ma;
31014+ else
31015+ *maxth = ((ma+256) * (1<<(mn-1)));
31016+
31017+ if (step_s == 0)
31018+ *minth = *maxth - step_i;
31019+ else
31020+ *minth = *maxth - (256 + step_i) * (1<<(step_s - 1));
31021+}
31022+
31023+void qbman_cgr_attr_wred_get_parm_dp(struct qbman_attr *d, uint32_t idx,
31024+ uint32_t *dp)
31025+{
31026+ uint32_t *p = ATTR32(d);
31027+ struct qb_attr_code code_wred_parm_dp = QB_CODE(WRED_PARM_DP_WORD(idx),
31028+ 0, 8);
31029+ *dp = qb_attr_code_decode(&code_wred_parm_dp, p);
31030+}
31031+
31032+/* Query CGR/CCGR/CQ statistics */
31033+static struct qb_attr_code code_cgr_stat_ct = QB_CODE(4, 0, 32);
31034+static struct qb_attr_code code_cgr_stat_frame_cnt_lo = QB_CODE(4, 0, 32);
31035+static struct qb_attr_code code_cgr_stat_frame_cnt_hi = QB_CODE(5, 0, 8);
31036+static struct qb_attr_code code_cgr_stat_byte_cnt_lo = QB_CODE(6, 0, 32);
31037+static struct qb_attr_code code_cgr_stat_byte_cnt_hi = QB_CODE(7, 0, 16);
31038+static int qbman_cgr_statistics_query(struct qbman_swp *s, uint32_t cgid,
31039+ int clear, uint32_t command_type,
31040+ uint64_t *frame_cnt, uint64_t *byte_cnt)
31041+{
31042+ uint32_t *p;
31043+ uint32_t verb, rslt;
31044+ uint32_t query_verb;
31045+ uint32_t hi, lo;
31046+
31047+ p = qbman_swp_mc_start(s);
31048+ if (!p)
31049+ return -EBUSY;
31050+
31051+ qb_attr_code_encode(&code_cgr_cgid, p, cgid);
31052+ if (command_type < 2)
31053+ qb_attr_code_encode(&code_cgr_stat_ct, p, command_type);
31054+ query_verb = clear ?
31055+ QBMAN_CGR_STAT_QUERY_CLR : QBMAN_CGR_STAT_QUERY;
31056+ p = qbman_swp_mc_complete(s, p, p[0] | query_verb);
31057+
31058+ /* Decode the outcome */
31059+ verb = qb_attr_code_decode(&code_generic_verb, p);
31060+ rslt = qb_attr_code_decode(&code_generic_rslt, p);
31061+ BUG_ON(verb != query_verb);
31062+
31063+ /* Determine success or failure */
31064+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
31065+ pr_err("Query statistics of CGID 0x%x failed,", cgid);
31066+ pr_err(" verb=0x%02x code=0x%02x\n", verb, rslt);
31067+ return -EIO;
31068+ }
31069+
31070+ if (*frame_cnt) {
31071+ hi = qb_attr_code_decode(&code_cgr_stat_frame_cnt_hi, p);
31072+ lo = qb_attr_code_decode(&code_cgr_stat_frame_cnt_lo, p);
31073+ *frame_cnt = ((uint64_t)hi << 32) | (uint64_t)lo;
31074+ }
31075+ if (*byte_cnt) {
31076+ hi = qb_attr_code_decode(&code_cgr_stat_byte_cnt_hi, p);
31077+ lo = qb_attr_code_decode(&code_cgr_stat_byte_cnt_lo, p);
31078+ *byte_cnt = ((uint64_t)hi << 32) | (uint64_t)lo;
31079+ }
31080+
31081+ return 0;
31082+}
31083+
31084+int qbman_cgr_reject_statistics(struct qbman_swp *s, uint32_t cgid, int clear,
31085+ uint64_t *frame_cnt, uint64_t *byte_cnt)
31086+{
31087+ return qbman_cgr_statistics_query(s, cgid, clear, 0xff,
31088+ frame_cnt, byte_cnt);
31089+}
31090+
31091+int qbman_ccgr_reject_statistics(struct qbman_swp *s, uint32_t cgid, int clear,
31092+ uint64_t *frame_cnt, uint64_t *byte_cnt)
31093+{
31094+ return qbman_cgr_statistics_query(s, cgid, clear, 1,
31095+ frame_cnt, byte_cnt);
31096+}
31097+
31098+int qbman_cq_dequeue_statistics(struct qbman_swp *s, uint32_t cgid, int clear,
31099+ uint64_t *frame_cnt, uint64_t *byte_cnt)
31100+{
31101+ return qbman_cgr_statistics_query(s, cgid, clear, 0,
31102+ frame_cnt, byte_cnt);
31103+}
31104+
31105+/* WQ Chan Query */
31106+static struct qb_attr_code code_wqchan_chanid = QB_CODE(0, 16, 16);
31107+static struct qb_attr_code code_wqchan_cdan_ctx_lo = QB_CODE(2, 0, 32);
31108+static struct qb_attr_code code_wqchan_cdan_ctx_hi = QB_CODE(3, 0, 32);
31109+static struct qb_attr_code code_wqchan_cdan_wqid = QB_CODE(1, 16, 16);
31110+static struct qb_attr_code code_wqchan_ctrl = QB_CODE(1, 8, 8);
31111+
31112+static void qbman_wqchan_attr_clear(struct qbman_attr *a)
31113+{
31114+ memset(a, 0, sizeof(*a));
31115+ attr_type_set(a, qbman_attr_usage_wqchan);
31116+}
31117+
31118+int qbman_wqchan_query(struct qbman_swp *s, uint16_t chanid,
31119+ struct qbman_attr *a)
31120+{
31121+ uint32_t *p;
31122+ uint32_t rslt;
31123+ uint32_t *attr = ATTR32(a);
31124+
31125+ qbman_wqchan_attr_clear(a);
31126+
31127+ /* Start the management command */
31128+ p = qbman_swp_mc_start(s);
31129+ if (!p)
31130+ return -EBUSY;
31131+
31132+ /* Encode the caller-provided attributes */
31133+ qb_attr_code_encode(&code_wqchan_chanid, p, chanid);
31134+
31135+ /* Complete the management command */
31136+ p = qbman_swp_mc_complete(s, p, p[0] | QBMAN_WQ_QUERY);
31137+
31138+ /* Decode the outcome */
31139+ rslt = qb_attr_code_decode(&code_generic_rslt, p);
31140+ BUG_ON(qb_attr_code_decode(&code_generic_verb, p); != QBMAN_WQ_QUERY);
31141+
31142+ /* Determine success or failure */
31143+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
31144+ pr_err("Query of WQCHAN 0x%x failed, code=0x%02x\n",
31145+ chanid, rslt);
31146+ return -EIO;
31147+ }
31148+
31149+ /* For the query, word[0] of the result contains only the
31150+ * verb/rslt fields, so skip word[0].
31151+ */
31152+ word_copy(&attr[1], &p[1], 15);
31153+ return 0;
31154+}
31155+
31156+void qbman_wqchan_attr_get_wqlen(struct qbman_attr *attr, int wq, uint32_t *len)
31157+{
31158+ uint32_t *p = ATTR32(attr);
31159+ struct qb_attr_code code_wqchan_len = QB_CODE(wq+ 8, 0, 24);
31160+ *len = qb_attr_code_decode(&code_wqchan_len, p);
31161+}
31162+
31163+void qbman_wqchan_attr_get_cdan_ctx(struct qbman_attr *attr, uint64_t *cdan_ctx)
31164+{
31165+ uint32_t lo, hi;
31166+ uint32_t *p = ATTR32(attr);
31167+
31168+ lo = qb_attr_code_decode(&code_wqchan_cdan_ctx_lo, p);
31169+ hi = qb_attr_code_decode(&code_wqchan_cdan_ctx_hi, p);
31170+ *cdan_ctx = ((uint64_t)hi << 32) | (uint64_t)lo;
31171+}
31172+
31173+void qbman_wqchan_attr_get_cdan_wqid(struct qbman_attr *attr,
31174+ uint16_t *cdan_wqid)
31175+{
31176+ uint32_t *p = ATTR32(attr);
31177+ *cdan_wqid = (uint16_t)qb_attr_code_decode(&code_wqchan_cdan_wqid, p);
31178+}
31179+
31180+void qbman_wqchan_attr_get_ctrl(struct qbman_attr *attr, uint8_t *ctrl)
31181+{
31182+ uint32_t *p = ATTR32(attr);
31183+ *ctrl = (uint8_t)qb_attr_code_decode(&code_wqchan_ctrl, p);
31184+}
31185+void qbman_wqchan_attr_get_chanid(struct qbman_attr *attr, uint16_t *chanid)
31186+{
31187+ uint32_t *p = ATTR32(attr);
31188+ *chanid = (uint16_t)qb_attr_code_decode(&code_wqchan_chanid, p);
31189+}
31190+
31191diff --git a/drivers/net/dpaa2/qbman/driver/qbman_debug.h b/drivers/net/dpaa2/qbman/driver/qbman_debug.h
31192new file mode 100644
31193index 0000000..8c89731
31194--- /dev/null
31195+++ b/drivers/net/dpaa2/qbman/driver/qbman_debug.h
31196@@ -0,0 +1,140 @@
31197+/* Copyright (C) 2015 Freescale Semiconductor, Inc.
31198+ *
31199+ * Redistribution and use in source and binary forms, with or without
31200+ * modification, are permitted provided that the following conditions are met:
31201+ * * Redistributions of source code must retain the above copyright
31202+ * notice, this list of conditions and the following disclaimer.
31203+ * * Redistributions in binary form must reproduce the above copyright
31204+ * notice, this list of conditions and the following disclaimer in the
31205+ * documentation and/or other materials provided with the distribution.
31206+ * * Neither the name of Freescale Semiconductor nor the
31207+ * names of its contributors may be used to endorse or promote products
31208+ * derived from this software without specific prior written permission.
31209+ *
31210+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
31211+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
31212+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31213+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
31214+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31215+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31216+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31217+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31218+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
31219+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31220+ */
31221+
31222+struct qbman_attr {
31223+ uint32_t dont_manipulate_directly[40];
31224+};
31225+
31226+/* Buffer pool query commands */
31227+int qbman_bp_query(struct qbman_swp *s, uint32_t bpid,
31228+ struct qbman_attr *a);
31229+void qbman_bp_attr_get_bdi(struct qbman_attr *a, int *bdi, int *va, int *wae);
31230+void qbman_bp_attr_get_swdet(struct qbman_attr *a, uint32_t *swdet);
31231+void qbman_bp_attr_get_swdxt(struct qbman_attr *a, uint32_t *swdxt);
31232+void qbman_bp_attr_get_hwdet(struct qbman_attr *a, uint32_t *hwdet);
31233+void qbman_bp_attr_get_hwdxt(struct qbman_attr *a, uint32_t *hwdxt);
31234+void qbman_bp_attr_get_swset(struct qbman_attr *a, uint32_t *swset);
31235+void qbman_bp_attr_get_swsxt(struct qbman_attr *a, uint32_t *swsxt);
31236+void qbman_bp_attr_get_vbpid(struct qbman_attr *a, uint32_t *vbpid);
31237+void qbman_bp_attr_get_icid(struct qbman_attr *a, uint32_t *icid, int *pl);
31238+void qbman_bp_attr_get_bpscn_addr(struct qbman_attr *a, uint64_t *bpscn_addr);
31239+void qbman_bp_attr_get_bpscn_ctx(struct qbman_attr *a, uint64_t *bpscn_ctx);
31240+void qbman_bp_attr_get_hw_targ(struct qbman_attr *a, uint32_t *hw_targ);
31241+int qbman_bp_info_has_free_bufs(struct qbman_attr *a);
31242+int qbman_bp_info_is_depleted(struct qbman_attr *a);
31243+int qbman_bp_info_is_surplus(struct qbman_attr *a);
31244+uint32_t qbman_bp_info_num_free_bufs(struct qbman_attr *a);
31245+uint32_t qbman_bp_info_hdptr(struct qbman_attr *a);
31246+uint32_t qbman_bp_info_sdcnt(struct qbman_attr *a);
31247+uint32_t qbman_bp_info_hdcnt(struct qbman_attr *a);
31248+uint32_t qbman_bp_info_sscnt(struct qbman_attr *a);
31249+
31250+/* FQ query function for programmable fields */
31251+int qbman_fq_query(struct qbman_swp *s, uint32_t fqid,
31252+ struct qbman_attr *desc);
31253+void qbman_fq_attr_get_fqctrl(struct qbman_attr *d, uint32_t *fqctrl);
31254+void qbman_fq_attr_get_cgrid(struct qbman_attr *d, uint32_t *cgrid);
31255+void qbman_fq_attr_get_destwq(struct qbman_attr *d, uint32_t *destwq);
31256+void qbman_fq_attr_get_icscred(struct qbman_attr *d, uint32_t *icscred);
31257+void qbman_fq_attr_get_tdthresh(struct qbman_attr *d, uint32_t *tdthresh);
31258+void qbman_fq_attr_get_oa(struct qbman_attr *d,
31259+ int *oa_ics, int *oa_cgr, int32_t *oa_len);
31260+void qbman_fq_attr_get_mctl(struct qbman_attr *d,
31261+ int *bdi, int *ff, int *va, int *ps);
31262+void qbman_fq_attr_get_ctx(struct qbman_attr *d, uint32_t *hi, uint32_t *lo);
31263+void qbman_fq_attr_get_icid(struct qbman_attr *d, uint32_t *icid, int *pl);
31264+void qbman_fq_attr_get_vfqid(struct qbman_attr *d, uint32_t *vfqid);
31265+void qbman_fq_attr_get_erfqid(struct qbman_attr *d, uint32_t *erfqid);
31266+
31267+/* FQ query command for non-programmable fields*/
31268+enum qbman_fq_schedstate_e {
31269+ qbman_fq_schedstate_oos = 0,
31270+ qbman_fq_schedstate_retired,
31271+ qbman_fq_schedstate_tentatively_scheduled,
31272+ qbman_fq_schedstate_truly_scheduled,
31273+ qbman_fq_schedstate_parked,
31274+ qbman_fq_schedstate_held_active,
31275+};
31276+
31277+int qbman_fq_query_state(struct qbman_swp *s, uint32_t fqid,
31278+ struct qbman_attr *state);
31279+uint32_t qbman_fq_state_schedstate(const struct qbman_attr *state);
31280+int qbman_fq_state_force_eligible(const struct qbman_attr *state);
31281+int qbman_fq_state_xoff(const struct qbman_attr *state);
31282+int qbman_fq_state_retirement_pending(const struct qbman_attr *state);
31283+int qbman_fq_state_overflow_error(const struct qbman_attr *state);
31284+uint32_t qbman_fq_state_frame_count(const struct qbman_attr *state);
31285+uint32_t qbman_fq_state_byte_count(const struct qbman_attr *state);
31286+
31287+/* CGR query */
31288+int qbman_cgr_query(struct qbman_swp *s, uint32_t cgid,
31289+ struct qbman_attr *attr);
31290+void qbman_cgr_attr_get_ctl1(struct qbman_attr *d, int *cscn_wq_en_enter,
31291+ int *cscn_wq_en_exit, int *cscn_wq_icd);
31292+void qbman_cgr_attr_get_mode(struct qbman_attr *d, uint32_t *mode,
31293+ int *rej_cnt_mode, int *cscn_bdi);
31294+void qbman_cgr_attr_get_ctl2(struct qbman_attr *d, int *cscn_wr_en_enter,
31295+ int *cscn_wr_en_exit, int *cg_wr_ae,
31296+ int *cscn_dcp_en, int *cg_wr_va);
31297+void qbman_cgr_attr_get_iwc(struct qbman_attr *d, int *i_cnt_wr_en,
31298+ uint32_t *i_cnt_wr_bnd);
31299+void qbman_cgr_attr_get_tdc(struct qbman_attr *d, int *td_en);
31300+void qbman_cgr_attr_get_cs_thres(struct qbman_attr *d, uint32_t *cs_thres);
31301+void qbman_cgr_attr_get_cs_thres_x(struct qbman_attr *d,
31302+ uint32_t *cs_thres_x);
31303+void qbman_cgr_attr_get_td_thres(struct qbman_attr *d, uint32_t *td_thres);
31304+void qbman_cgr_attr_get_cscn_tdcp(struct qbman_attr *d, uint32_t *cscn_tdcp);
31305+void qbman_cgr_attr_get_cscn_wqid(struct qbman_attr *d, uint32_t *cscn_wqid);
31306+void qbman_cgr_attr_get_cscn_vcgid(struct qbman_attr *d,
31307+ uint32_t *cscn_vcgid);
31308+void qbman_cgr_attr_get_cg_icid(struct qbman_attr *d, uint32_t *icid,
31309+ int *pl);
31310+void qbman_cgr_attr_get_cg_wr_addr(struct qbman_attr *d,
31311+ uint64_t *cg_wr_addr);
31312+void qbman_cgr_attr_get_cscn_ctx(struct qbman_attr *d, uint64_t *cscn_ctx);
31313+void qbman_cgr_attr_wred_get_edp(struct qbman_attr *d, uint32_t idx,
31314+ int *edp);
31315+void qbman_cgr_attr_wred_dp_decompose(uint32_t dp, uint64_t *minth,
31316+ uint64_t *maxth, uint8_t *maxp);
31317+void qbman_cgr_attr_wred_get_parm_dp(struct qbman_attr *d, uint32_t idx,
31318+ uint32_t *dp);
31319+
31320+/* CGR/CCGR/CQ statistics query */
31321+int qbman_cgr_reject_statistics(struct qbman_swp *s, uint32_t cgid, int clear,
31322+ uint64_t *frame_cnt, uint64_t *byte_cnt);
31323+int qbman_ccgr_reject_statistics(struct qbman_swp *s, uint32_t cgid, int clear,
31324+ uint64_t *frame_cnt, uint64_t *byte_cnt);
31325+int qbman_cq_dequeue_statistics(struct qbman_swp *s, uint32_t cgid, int clear,
31326+ uint64_t *frame_cnt, uint64_t *byte_cnt);
31327+
31328+/* Query Work Queue Channel */
31329+int qbman_wqchan_query(struct qbman_swp *s, uint16_t chanid,
31330+ struct qbman_attr *attr);
31331+void qbman_wqchan_attr_get_wqlen(struct qbman_attr *attr, int wq, uint32_t *len);
31332+void qbman_wqchan_attr_get_cdan_ctx(struct qbman_attr *attr, uint64_t *cdan_ctx);
31333+void qbman_wqchan_attr_get_cdan_wqid(struct qbman_attr *attr,
31334+ uint16_t *cdan_wqid);
31335+void qbman_wqchan_attr_get_ctrl(struct qbman_attr *attr, uint8_t *ctrl);
31336+void qbman_wqchan_attr_get_chanid(struct qbman_attr *attr, uint16_t *chanid);
31337diff --git a/drivers/net/dpaa2/qbman/driver/qbman_portal.c b/drivers/net/dpaa2/qbman/driver/qbman_portal.c
31338new file mode 100644
31339index 0000000..464f386
31340--- /dev/null
31341+++ b/drivers/net/dpaa2/qbman/driver/qbman_portal.c
31342@@ -0,0 +1,1407 @@
31343+/* Copyright (C) 2014 Freescale Semiconductor, Inc.
31344+ *
31345+ * Redistribution and use in source and binary forms, with or without
31346+ * modification, are permitted provided that the following conditions are met:
31347+ * * Redistributions of source code must retain the above copyright
31348+ * notice, this list of conditions and the following disclaimer.
31349+ * * Redistributions in binary form must reproduce the above copyright
31350+ * notice, this list of conditions and the following disclaimer in the
31351+ * documentation and/or other materials provided with the distribution.
31352+ * * Neither the name of Freescale Semiconductor nor the
31353+ * names of its contributors may be used to endorse or promote products
31354+ * derived from this software without specific prior written permission.
31355+ *
31356+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
31357+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
31358+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31359+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
31360+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31361+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31362+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31363+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31364+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
31365+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31366+ */
31367+
31368+#include "qbman_portal.h"
31369+
31370+/* QBMan portal management command codes */
31371+#define QBMAN_MC_ACQUIRE 0x30
31372+#define QBMAN_WQCHAN_CONFIGURE 0x46
31373+
31374+/* CINH register offsets */
31375+#define QBMAN_CINH_SWP_EQCR_PI 0x800
31376+#define QBMAN_CINH_SWP_EQCR_CI 0x840
31377+#define QBMAN_CINH_SWP_EQAR 0x8c0
31378+#define QBMAN_CINH_SWP_DQPI 0xa00
31379+#define QBMAN_CINH_SWP_DCAP 0xac0
31380+#define QBMAN_CINH_SWP_SDQCR 0xb00
31381+#define QBMAN_CINH_SWP_RAR 0xcc0
31382+#define QBMAN_CINH_SWP_ISR 0xe00
31383+#define QBMAN_CINH_SWP_IER 0xe40
31384+#define QBMAN_CINH_SWP_ISDR 0xe80
31385+#define QBMAN_CINH_SWP_IIR 0xec0
31386+
31387+/* CENA register offsets */
31388+#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((uint32_t)(n) << 6))
31389+#define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((uint32_t)(n) << 6))
31390+#define QBMAN_CENA_SWP_RCR(n) (0x400 + ((uint32_t)(n) << 6))
31391+#define QBMAN_CENA_SWP_CR 0x600
31392+#define QBMAN_CENA_SWP_RR(vb) (0x700 + ((uint32_t)(vb) >> 1))
31393+#define QBMAN_CENA_SWP_VDQCR 0x780
31394+#define QBMAN_CENA_SWP_EQCR_CI 0x840
31395+
31396+/* Reverse mapping of QBMAN_CENA_SWP_DQRR() */
31397+#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0x1ff) >> 6)
31398+
31399+/* QBMan FQ management command codes */
31400+#define QBMAN_FQ_SCHEDULE 0x48
31401+#define QBMAN_FQ_FORCE 0x49
31402+#define QBMAN_FQ_XON 0x4d
31403+#define QBMAN_FQ_XOFF 0x4e
31404+
31405+/*******************************/
31406+/* Pre-defined attribute codes */
31407+/*******************************/
31408+
31409+struct qb_attr_code code_generic_verb = QB_CODE(0, 0, 7);
31410+struct qb_attr_code code_generic_rslt = QB_CODE(0, 8, 8);
31411+
31412+/*************************/
31413+/* SDQCR attribute codes */
31414+/*************************/
31415+
31416+/* we put these here because at least some of them are required by
31417+ * qbman_swp_init() */
31418+struct qb_attr_code code_sdqcr_dct = QB_CODE(0, 24, 2);
31419+struct qb_attr_code code_sdqcr_fc = QB_CODE(0, 29, 1);
31420+struct qb_attr_code code_sdqcr_tok = QB_CODE(0, 16, 8);
31421+#define CODE_SDQCR_DQSRC(n) QB_CODE(0, n, 1)
31422+enum qbman_sdqcr_dct {
31423+ qbman_sdqcr_dct_null = 0,
31424+ qbman_sdqcr_dct_prio_ics,
31425+ qbman_sdqcr_dct_active_ics,
31426+ qbman_sdqcr_dct_active
31427+};
31428+enum qbman_sdqcr_fc {
31429+ qbman_sdqcr_fc_one = 0,
31430+ qbman_sdqcr_fc_up_to_3 = 1
31431+};
31432+struct qb_attr_code code_sdqcr_dqsrc = QB_CODE(0, 0, 16);
31433+
31434+/*********************************/
31435+/* Portal constructor/destructor */
31436+/*********************************/
31437+
31438+/* Software portals should always be in the power-on state when we initialise,
31439+ * due to the CCSR-based portal reset functionality that MC has.
31440+ *
31441+ * Erk! Turns out that QMan versions prior to 4.1 do not correctly reset DQRR
31442+ * valid-bits, so we need to support a workaround where we don't trust
31443+ * valid-bits when detecting new entries until any stale ring entries have been
31444+ * overwritten at least once. The idea is that we read PI for the first few
31445+ * entries, then switch to valid-bit after that. The trick is to clear the
31446+ * bug-work-around boolean once the PI wraps around the ring for the first time.
31447+ *
31448+ * Note: this still carries a slight additional cost once the decrementer hits
31449+ * zero.
31450+ */
31451+struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
31452+{
31453+ int ret;
31454+ uint32_t eqcr_pi;
31455+ struct qbman_swp *p = kmalloc(sizeof(*p), GFP_KERNEL);
31456+ if (!p)
31457+ return NULL;
31458+ p->desc = d;
31459+#ifdef QBMAN_CHECKING
31460+ p->mc.check = swp_mc_can_start;
31461+#endif
31462+ p->mc.valid_bit = QB_VALID_BIT;
31463+ p->sdq = 0;
31464+ qb_attr_code_encode(&code_sdqcr_dct, &p->sdq, qbman_sdqcr_dct_prio_ics);
31465+ qb_attr_code_encode(&code_sdqcr_fc, &p->sdq, qbman_sdqcr_fc_up_to_3);
31466+ qb_attr_code_encode(&code_sdqcr_tok, &p->sdq, 0xbb);
31467+ atomic_set(&p->vdq.busy, 1);
31468+ p->vdq.valid_bit = QB_VALID_BIT;
31469+ p->dqrr.next_idx = 0;
31470+ p->dqrr.valid_bit = QB_VALID_BIT;
31471+ qman_version = p->desc->qman_version;
31472+ if ((qman_version & 0xFFFF0000) < QMAN_REV_4100) {
31473+ p->dqrr.dqrr_size = 4;
31474+ p->dqrr.reset_bug = 1;
31475+ } else {
31476+ p->dqrr.dqrr_size = 8;
31477+ p->dqrr.reset_bug = 0;
31478+ }
31479+
31480+ ret = qbman_swp_sys_init(&p->sys, d, p->dqrr.dqrr_size);
31481+ if (ret) {
31482+ kfree(p);
31483+ pr_err("qbman_swp_sys_init() failed %d\n", ret);
31484+ return NULL;
31485+ }
31486+ /* SDQCR needs to be initialized to 0 when no channels are
31487+ being dequeued from or else the QMan HW will indicate an
31488+ error. The values that were calculated above will be
31489+ applied when dequeues from a specific channel are enabled */
31490+ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_SDQCR, 0);
31491+ eqcr_pi = qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_EQCR_PI);
31492+ p->eqcr.pi = eqcr_pi & 0xF;
31493+ p->eqcr.pi_vb = eqcr_pi & QB_VALID_BIT;
31494+ p->eqcr.ci = qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_EQCR_CI) & 0xF;
31495+ p->eqcr.available = QBMAN_EQCR_SIZE - qm_cyc_diff(QBMAN_EQCR_SIZE,
31496+ p->eqcr.ci, p->eqcr.pi);
31497+
31498+ return p;
31499+}
31500+
31501+void qbman_swp_finish(struct qbman_swp *p)
31502+{
31503+#ifdef QBMAN_CHECKING
31504+ BUG_ON(p->mc.check != swp_mc_can_start);
31505+#endif
31506+ qbman_swp_sys_finish(&p->sys);
31507+ kfree(p);
31508+}
31509+
31510+const struct qbman_swp_desc *qbman_swp_get_desc(struct qbman_swp *p)
31511+{
31512+ return p->desc;
31513+}
31514+
31515+/**************/
31516+/* Interrupts */
31517+/**************/
31518+
31519+uint32_t qbman_swp_interrupt_get_vanish(struct qbman_swp *p)
31520+{
31521+ return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ISDR);
31522+}
31523+
31524+void qbman_swp_interrupt_set_vanish(struct qbman_swp *p, uint32_t mask)
31525+{
31526+ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ISDR, mask);
31527+}
31528+
31529+uint32_t qbman_swp_interrupt_read_status(struct qbman_swp *p)
31530+{
31531+ return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ISR);
31532+}
31533+
31534+void qbman_swp_interrupt_clear_status(struct qbman_swp *p, uint32_t mask)
31535+{
31536+ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ISR, mask);
31537+}
31538+
31539+uint32_t qbman_swp_interrupt_get_trigger(struct qbman_swp *p)
31540+{
31541+ return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_IER);
31542+}
31543+
31544+void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, uint32_t mask)
31545+{
31546+ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_IER, mask);
31547+}
31548+
31549+int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p)
31550+{
31551+ return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_IIR);
31552+}
31553+
31554+void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit)
31555+{
31556+ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_IIR, inhibit ? 0xffffffff : 0);
31557+}
31558+
31559+/***********************/
31560+/* Management commands */
31561+/***********************/
31562+
31563+/*
31564+ * Internal code common to all types of management commands.
31565+ */
31566+
31567+void *qbman_swp_mc_start(struct qbman_swp *p)
31568+{
31569+ void *ret;
31570+#ifdef QBMAN_CHECKING
31571+ BUG_ON(p->mc.check != swp_mc_can_start);
31572+#endif
31573+ ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR);
31574+#ifdef QBMAN_CHECKING
31575+ if (!ret)
31576+ p->mc.check = swp_mc_can_submit;
31577+#endif
31578+ return ret;
31579+}
31580+
31581+void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb)
31582+{
31583+ uint32_t *v = cmd;
31584+#ifdef QBMAN_CHECKING
31585+ BUG_ON(!p->mc.check != swp_mc_can_submit);
31586+#endif
31587+ /* TBD: "|=" is going to hurt performance. Need to move as many fields
31588+ * out of word zero, and for those that remain, the "OR" needs to occur
31589+ * at the caller side. This debug check helps to catch cases where the
31590+ * caller wants to OR but has forgotten to do so. */
31591+ BUG_ON((*v & cmd_verb) != *v);
31592+ *v = cmd_verb | p->mc.valid_bit;
31593+ qbman_cena_write_complete(&p->sys, QBMAN_CENA_SWP_CR, cmd);
31594+#ifdef QBMAN_CHECKING
31595+ p->mc.check = swp_mc_can_poll;
31596+#endif
31597+}
31598+
31599+void *qbman_swp_mc_result(struct qbman_swp *p)
31600+{
31601+ uint32_t *ret, verb;
31602+#ifdef QBMAN_CHECKING
31603+ BUG_ON(p->mc.check != swp_mc_can_poll);
31604+#endif
31605+ qbman_cena_invalidate_prefetch(&p->sys,
31606+ QBMAN_CENA_SWP_RR(p->mc.valid_bit));
31607+ ret = qbman_cena_read(&p->sys, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
31608+ /* Remove the valid-bit - command completed iff the rest is non-zero */
31609+ verb = ret[0] & ~QB_VALID_BIT;
31610+ if (!verb)
31611+ return NULL;
31612+#ifdef QBMAN_CHECKING
31613+ p->mc.check = swp_mc_can_start;
31614+#endif
31615+ p->mc.valid_bit ^= QB_VALID_BIT;
31616+ return ret;
31617+}
31618+
31619+/***********/
31620+/* Enqueue */
31621+/***********/
31622+
31623+/* These should be const, eventually */
31624+static struct qb_attr_code code_eq_cmd = QB_CODE(0, 0, 2);
31625+static struct qb_attr_code code_eq_eqdi = QB_CODE(0, 3, 1);
31626+static struct qb_attr_code code_eq_dca_en = QB_CODE(0, 15, 1);
31627+static struct qb_attr_code code_eq_dca_pk = QB_CODE(0, 14, 1);
31628+static struct qb_attr_code code_eq_dca_idx = QB_CODE(0, 8, 2);
31629+static struct qb_attr_code code_eq_orp_en = QB_CODE(0, 2, 1);
31630+static struct qb_attr_code code_eq_orp_is_nesn = QB_CODE(0, 31, 1);
31631+static struct qb_attr_code code_eq_orp_nlis = QB_CODE(0, 30, 1);
31632+static struct qb_attr_code code_eq_orp_seqnum = QB_CODE(0, 16, 14);
31633+static struct qb_attr_code code_eq_opr_id = QB_CODE(1, 0, 16);
31634+static struct qb_attr_code code_eq_tgt_id = QB_CODE(2, 0, 24);
31635+/* static struct qb_attr_code code_eq_tag = QB_CODE(3, 0, 32); */
31636+static struct qb_attr_code code_eq_qd_en = QB_CODE(0, 4, 1);
31637+static struct qb_attr_code code_eq_qd_bin = QB_CODE(4, 0, 16);
31638+static struct qb_attr_code code_eq_qd_pri = QB_CODE(4, 16, 4);
31639+static struct qb_attr_code code_eq_rsp_stash = QB_CODE(5, 16, 1);
31640+static struct qb_attr_code code_eq_rsp_id = QB_CODE(5, 24, 8);
31641+static struct qb_attr_code code_eq_rsp_lo = QB_CODE(6, 0, 32);
31642+
31643+enum qbman_eq_cmd_e {
31644+ /* No enqueue, primarily for plugging ORP gaps for dropped frames */
31645+ qbman_eq_cmd_empty,
31646+ /* DMA an enqueue response once complete */
31647+ qbman_eq_cmd_respond,
31648+ /* DMA an enqueue response only if the enqueue fails */
31649+ qbman_eq_cmd_respond_reject
31650+};
31651+
31652+void qbman_eq_desc_clear(struct qbman_eq_desc *d)
31653+{
31654+ memset(d, 0, sizeof(*d));
31655+}
31656+
31657+void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success)
31658+{
31659+ uint32_t *cl = qb_cl(d);
31660+ qb_attr_code_encode(&code_eq_orp_en, cl, 0);
31661+ qb_attr_code_encode(&code_eq_cmd, cl,
31662+ respond_success ? qbman_eq_cmd_respond :
31663+ qbman_eq_cmd_respond_reject);
31664+}
31665+
31666+void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success,
31667+ uint32_t opr_id, uint32_t seqnum, int incomplete)
31668+{
31669+ uint32_t *cl = qb_cl(d);
31670+ qb_attr_code_encode(&code_eq_orp_en, cl, 1);
31671+ qb_attr_code_encode(&code_eq_cmd, cl,
31672+ respond_success ? qbman_eq_cmd_respond :
31673+ qbman_eq_cmd_respond_reject);
31674+ qb_attr_code_encode(&code_eq_opr_id, cl, opr_id);
31675+ qb_attr_code_encode(&code_eq_orp_seqnum, cl, seqnum);
31676+ qb_attr_code_encode(&code_eq_orp_nlis, cl, !!incomplete);
31677+}
31678+
31679+void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, uint32_t opr_id,
31680+ uint32_t seqnum)
31681+{
31682+ uint32_t *cl = qb_cl(d);
31683+ qb_attr_code_encode(&code_eq_orp_en, cl, 1);
31684+ qb_attr_code_encode(&code_eq_cmd, cl, qbman_eq_cmd_empty);
31685+ qb_attr_code_encode(&code_eq_opr_id, cl, opr_id);
31686+ qb_attr_code_encode(&code_eq_orp_seqnum, cl, seqnum);
31687+ qb_attr_code_encode(&code_eq_orp_nlis, cl, 0);
31688+ qb_attr_code_encode(&code_eq_orp_is_nesn, cl, 0);
31689+}
31690+
31691+void qbman_eq_desc_set_orp_nesn(struct qbman_eq_desc *d, uint32_t opr_id,
31692+ uint32_t seqnum)
31693+{
31694+ uint32_t *cl = qb_cl(d);
31695+ qb_attr_code_encode(&code_eq_orp_en, cl, 1);
31696+ qb_attr_code_encode(&code_eq_cmd, cl, qbman_eq_cmd_empty);
31697+ qb_attr_code_encode(&code_eq_opr_id, cl, opr_id);
31698+ qb_attr_code_encode(&code_eq_orp_seqnum, cl, seqnum);
31699+ qb_attr_code_encode(&code_eq_orp_nlis, cl, 0);
31700+ qb_attr_code_encode(&code_eq_orp_is_nesn, cl, 1);
31701+}
31702+
31703+void qbman_eq_desc_set_response(struct qbman_eq_desc *d,
31704+ dma_addr_t storage_phys,
31705+ int stash)
31706+{
31707+ uint32_t *cl = qb_cl(d);
31708+ qb_attr_code_encode_64(&code_eq_rsp_lo, (uint64_t *)cl, storage_phys);
31709+ qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash);
31710+}
31711+
31712+void qbman_eq_desc_set_token(struct qbman_eq_desc *d, uint8_t token)
31713+{
31714+ uint32_t *cl = qb_cl(d);
31715+ qb_attr_code_encode(&code_eq_rsp_id, cl, (uint32_t)token);
31716+}
31717+
31718+void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, uint32_t fqid)
31719+{
31720+ uint32_t *cl = qb_cl(d);
31721+ qb_attr_code_encode(&code_eq_qd_en, cl, 0);
31722+ qb_attr_code_encode(&code_eq_tgt_id, cl, fqid);
31723+}
31724+
31725+void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid,
31726+ uint32_t qd_bin, uint32_t qd_prio)
31727+{
31728+ uint32_t *cl = qb_cl(d);
31729+ qb_attr_code_encode(&code_eq_qd_en, cl, 1);
31730+ qb_attr_code_encode(&code_eq_tgt_id, cl, qdid);
31731+ qb_attr_code_encode(&code_eq_qd_bin, cl, qd_bin);
31732+ qb_attr_code_encode(&code_eq_qd_pri, cl, qd_prio);
31733+}
31734+
31735+void qbman_eq_desc_set_eqdi(struct qbman_eq_desc *d, int enable)
31736+{
31737+ uint32_t *cl = qb_cl(d);
31738+ qb_attr_code_encode(&code_eq_eqdi, cl, !!enable);
31739+}
31740+
31741+void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable,
31742+ uint32_t dqrr_idx, int park)
31743+{
31744+ uint32_t *cl = qb_cl(d);
31745+ qb_attr_code_encode(&code_eq_dca_en, cl, !!enable);
31746+ if (enable) {
31747+ qb_attr_code_encode(&code_eq_dca_pk, cl, !!park);
31748+ qb_attr_code_encode(&code_eq_dca_idx, cl, dqrr_idx);
31749+ }
31750+}
31751+
31752+#define EQAR_IDX(eqar) ((eqar) & 0x7)
31753+#define EQAR_VB(eqar) ((eqar) & 0x80)
31754+#define EQAR_SUCCESS(eqar) ((eqar) & 0x100)
31755+static int qbman_swp_enqueue_array_mode(struct qbman_swp *s,
31756+ const struct qbman_eq_desc *d,
31757+ const struct qbman_fd *fd)
31758+{
31759+ uint32_t *p;
31760+ const uint32_t *cl = qb_cl(d);
31761+ uint32_t eqar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_EQAR);
31762+ pr_debug("EQAR=%08x\n", eqar);
31763+ if (!EQAR_SUCCESS(eqar))
31764+ return -EBUSY;
31765+ p = qbman_cena_write_start_wo_shadow(&s->sys,
31766+ QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
31767+ word_copy(&p[1], &cl[1], 7);
31768+ word_copy(&p[8], fd, sizeof(*fd) >> 2);
31769+ /* Set the verb byte, have to substitute in the valid-bit */
31770+ lwsync();
31771+ p[0] = cl[0] | EQAR_VB(eqar);
31772+ qbman_cena_write_complete_wo_shadow(&s->sys,
31773+ QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
31774+ return 0;
31775+}
31776+
31777+static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s,
31778+ const struct qbman_eq_desc *d,
31779+ const struct qbman_fd *fd)
31780+{
31781+ uint32_t *p;
31782+ const uint32_t *cl = qb_cl(d);
31783+ uint32_t eqcr_ci;
31784+ uint8_t diff;
31785+
31786+ if (!s->eqcr.available) {
31787+ eqcr_ci = s->eqcr.ci;
31788+ s->eqcr.ci = qbman_cena_read_reg(&s->sys,
31789+ QBMAN_CENA_SWP_EQCR_CI) & 0xF;
31790+ diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
31791+ eqcr_ci, s->eqcr.ci);
31792+ s->eqcr.available += diff;
31793+ if (!diff)
31794+ return -EBUSY;
31795+ }
31796+
31797+ p = qbman_cena_write_start_wo_shadow(&s->sys,
31798+ QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7));
31799+ word_copy(&p[1], &cl[1], 7);
31800+ word_copy(&p[8], fd, sizeof(*fd) >> 2);
31801+ lwsync();
31802+ /* Set the verb byte, have to substitute in the valid-bit */
31803+ p[0] = cl[0] | s->eqcr.pi_vb;
31804+ qbman_cena_write_complete_wo_shadow(&s->sys,
31805+ QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7));
31806+ s->eqcr.pi++;
31807+ s->eqcr.pi &= 0xF;
31808+ s->eqcr.available--;
31809+ if (!(s->eqcr.pi & 7))
31810+ s->eqcr.pi_vb ^= QB_VALID_BIT;
31811+ return 0;
31812+}
31813+
31814+int qbman_swp_fill_ring(struct qbman_swp *s,
31815+ const struct qbman_eq_desc *d,
31816+ const struct qbman_fd *fd,
31817+ __attribute__((unused)) uint8_t burst_index)
31818+{
31819+ uint32_t *p;
31820+ const uint32_t *cl = qb_cl(d);
31821+ uint32_t eqcr_ci;
31822+ uint8_t diff;
31823+
31824+ if (!s->eqcr.available) {
31825+ eqcr_ci = s->eqcr.ci;
31826+ s->eqcr.ci = qbman_cena_read_reg(&s->sys,
31827+ QBMAN_CENA_SWP_EQCR_CI) & 0xF;
31828+ diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
31829+ eqcr_ci, s->eqcr.ci);
31830+ s->eqcr.available += diff;
31831+ if (!diff) {
31832+ return -EBUSY;
31833+ }
31834+ }
31835+ p = qbman_cena_write_start_wo_shadow(&s->sys,
31836+ QBMAN_CENA_SWP_EQCR((s->eqcr.pi/* +burst_index */) & 7));
31837+ //word_copy(&p[1], &cl[1], 7);
31838+ memcpy(&p[1], &cl[1], 7);
31839+ /* word_copy(&p[8], fd, sizeof(*fd) >> 2); */
31840+ memcpy(&p[8], fd, sizeof(struct qbman_fd));
31841+
31842+ //lwsync();
31843+
31844+ p[0] = cl[0] | s->eqcr.pi_vb;
31845+
31846+ s->eqcr.pi++;
31847+ s->eqcr.pi &= 0xF;
31848+ s->eqcr.available--;
31849+ if (!(s->eqcr.pi & 7))
31850+ s->eqcr.pi_vb ^= QB_VALID_BIT;
31851+
31852+ return 0;
31853+}
31854+
31855+int qbman_swp_flush_ring(struct qbman_swp *s)
31856+{
31857+ void *ptr = s->sys.addr_cena;
31858+ dcbf((uint64_t)ptr);
31859+ dcbf((uint64_t)ptr + 0x40);
31860+ dcbf((uint64_t)ptr + 0x80);
31861+ dcbf((uint64_t)ptr + 0xc0);
31862+ dcbf((uint64_t)ptr + 0x100);
31863+ dcbf((uint64_t)ptr + 0x140);
31864+ dcbf((uint64_t)ptr + 0x180);
31865+ dcbf((uint64_t)ptr + 0x1c0);
31866+
31867+ return 0;
31868+}
31869+
31870+void qbman_sync(void)
31871+{
31872+ lwsync();
31873+}
31874+
31875+int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
31876+ const struct qbman_fd *fd)
31877+{
31878+ if (s->sys.eqcr_mode == qman_eqcr_vb_array)
31879+ return qbman_swp_enqueue_array_mode(s, d, fd);
31880+ else /* Use ring mode by default */
31881+ return qbman_swp_enqueue_ring_mode(s, d, fd);
31882+}
31883+
31884+/*************************/
31885+/* Static (push) dequeue */
31886+/*************************/
31887+
31888+void qbman_swp_push_get(struct qbman_swp *s, uint8_t channel_idx, int *enabled)
31889+{
31890+ struct qb_attr_code code = CODE_SDQCR_DQSRC(channel_idx);
31891+
31892+ BUG_ON(channel_idx > 15);
31893+ *enabled = (int)qb_attr_code_decode(&code, &s->sdq);
31894+}
31895+
31896+void qbman_swp_push_set(struct qbman_swp *s, uint8_t channel_idx, int enable)
31897+{
31898+ uint16_t dqsrc;
31899+ struct qb_attr_code code = CODE_SDQCR_DQSRC(channel_idx);
31900+ BUG_ON(channel_idx > 15);
31901+ qb_attr_code_encode(&code, &s->sdq, !!enable);
31902+ /* Read make the complete src map. If no channels are enabled
31903+ the SDQCR must be 0 or else QMan will assert errors */
31904+ dqsrc = (uint16_t)qb_attr_code_decode(&code_sdqcr_dqsrc, &s->sdq);
31905+ if (dqsrc != 0)
31906+ qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_SDQCR, s->sdq);
31907+ else
31908+ qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_SDQCR, 0);
31909+}
31910+
31911+/***************************/
31912+/* Volatile (pull) dequeue */
31913+/***************************/
31914+
31915+/* These should be const, eventually */
31916+static struct qb_attr_code code_pull_dct = QB_CODE(0, 0, 2);
31917+static struct qb_attr_code code_pull_dt = QB_CODE(0, 2, 2);
31918+static struct qb_attr_code code_pull_rls = QB_CODE(0, 4, 1);
31919+static struct qb_attr_code code_pull_stash = QB_CODE(0, 5, 1);
31920+static struct qb_attr_code code_pull_numframes = QB_CODE(0, 8, 4);
31921+static struct qb_attr_code code_pull_token = QB_CODE(0, 16, 8);
31922+static struct qb_attr_code code_pull_dqsource = QB_CODE(1, 0, 24);
31923+static struct qb_attr_code code_pull_rsp_lo = QB_CODE(2, 0, 32);
31924+
31925+enum qb_pull_dt_e {
31926+ qb_pull_dt_channel,
31927+ qb_pull_dt_workqueue,
31928+ qb_pull_dt_framequeue
31929+};
31930+
31931+void qbman_pull_desc_clear(struct qbman_pull_desc *d)
31932+{
31933+ memset(d, 0, sizeof(*d));
31934+}
31935+
31936+void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
31937+ struct qbman_result *storage,
31938+ dma_addr_t storage_phys,
31939+ int stash)
31940+{
31941+ uint32_t *cl = qb_cl(d);
31942+ /* Squiggle the pointer 'storage' into the extra 2 words of the
31943+ * descriptor (which aren't copied to the hw command) */
31944+ *(void **)&cl[4] = storage;
31945+ if (!storage) {
31946+ qb_attr_code_encode(&code_pull_rls, cl, 0);
31947+ return;
31948+ }
31949+ qb_attr_code_encode(&code_pull_rls, cl, 1);
31950+ qb_attr_code_encode(&code_pull_stash, cl, !!stash);
31951+ qb_attr_code_encode_64(&code_pull_rsp_lo, (uint64_t *)cl, storage_phys);
31952+}
31953+
31954+void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, uint8_t numframes)
31955+{
31956+ uint32_t *cl = qb_cl(d);
31957+ BUG_ON(!numframes || (numframes > 16));
31958+ qb_attr_code_encode(&code_pull_numframes, cl,
31959+ (uint32_t)(numframes - 1));
31960+}
31961+
31962+void qbman_pull_desc_set_token(struct qbman_pull_desc *d, uint8_t token)
31963+{
31964+ uint32_t *cl = qb_cl(d);
31965+ qb_attr_code_encode(&code_pull_token, cl, token);
31966+}
31967+
31968+void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, uint32_t fqid)
31969+{
31970+ uint32_t *cl = qb_cl(d);
31971+ qb_attr_code_encode(&code_pull_dct, cl, 1);
31972+ qb_attr_code_encode(&code_pull_dt, cl, qb_pull_dt_framequeue);
31973+ qb_attr_code_encode(&code_pull_dqsource, cl, fqid);
31974+}
31975+
31976+void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, uint32_t wqid,
31977+ enum qbman_pull_type_e dct)
31978+{
31979+ uint32_t *cl = qb_cl(d);
31980+ qb_attr_code_encode(&code_pull_dct, cl, dct);
31981+ qb_attr_code_encode(&code_pull_dt, cl, qb_pull_dt_workqueue);
31982+ qb_attr_code_encode(&code_pull_dqsource, cl, wqid);
31983+}
31984+
31985+void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, uint32_t chid,
31986+ enum qbman_pull_type_e dct)
31987+{
31988+ uint32_t *cl = qb_cl(d);
31989+ qb_attr_code_encode(&code_pull_dct, cl, dct);
31990+ qb_attr_code_encode(&code_pull_dt, cl, qb_pull_dt_channel);
31991+ qb_attr_code_encode(&code_pull_dqsource, cl, chid);
31992+}
31993+
31994+int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
31995+{
31996+ uint32_t *p;
31997+ uint32_t *cl = qb_cl(d);
31998+ if (!atomic_dec_and_test(&s->vdq.busy)) {
31999+ atomic_inc(&s->vdq.busy);
32000+ return -EBUSY;
32001+ }
32002+ s->vdq.storage = *(void **)&cl[4];
32003+ qb_attr_code_encode(&code_pull_token, cl, 1);
32004+ p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR);
32005+ word_copy(&p[1], &cl[1], 3);
32006+ /* Set the verb byte, have to substitute in the valid-bit */
32007+ lwsync();
32008+ p[0] = cl[0] | s->vdq.valid_bit;
32009+ s->vdq.valid_bit ^= QB_VALID_BIT;
32010+ qbman_cena_write_complete_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR);
32011+ return 0;
32012+}
32013+
32014+/****************/
32015+/* Polling DQRR */
32016+/****************/
32017+
32018+static struct qb_attr_code code_dqrr_verb = QB_CODE(0, 0, 8);
32019+static struct qb_attr_code code_dqrr_response = QB_CODE(0, 0, 7);
32020+static struct qb_attr_code code_dqrr_stat = QB_CODE(0, 8, 8);
32021+static struct qb_attr_code code_dqrr_seqnum = QB_CODE(0, 16, 14);
32022+static struct qb_attr_code code_dqrr_odpid = QB_CODE(1, 0, 16);
32023+/* static struct qb_attr_code code_dqrr_tok = QB_CODE(1, 24, 8); */
32024+static struct qb_attr_code code_dqrr_fqid = QB_CODE(2, 0, 24);
32025+static struct qb_attr_code code_dqrr_byte_count = QB_CODE(4, 0, 32);
32026+static struct qb_attr_code code_dqrr_frame_count = QB_CODE(5, 0, 24);
32027+static struct qb_attr_code code_dqrr_ctx_lo = QB_CODE(6, 0, 32);
32028+
32029+#define QBMAN_RESULT_DQ 0x60
32030+#define QBMAN_RESULT_FQRN 0x21
32031+#define QBMAN_RESULT_FQRNI 0x22
32032+#define QBMAN_RESULT_FQPN 0x24
32033+#define QBMAN_RESULT_FQDAN 0x25
32034+#define QBMAN_RESULT_CDAN 0x26
32035+#define QBMAN_RESULT_CSCN_MEM 0x27
32036+#define QBMAN_RESULT_CGCU 0x28
32037+#define QBMAN_RESULT_BPSCN 0x29
32038+#define QBMAN_RESULT_CSCN_WQ 0x2a
32039+
32040+static struct qb_attr_code code_dqpi_pi = QB_CODE(0, 0, 4);
32041+
32042+/* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry
32043+ * only once, so repeated calls can return a sequence of DQRR entries, without
32044+ * requiring they be consumed immediately or in any particular order. */
32045+const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s)
32046+{
32047+ uint32_t verb;
32048+ uint32_t response_verb;
32049+ uint32_t flags;
32050+ const struct qbman_result *dq;
32051+ const uint32_t *p;
32052+
32053+ /* Before using valid-bit to detect if something is there, we have to
32054+ * handle the case of the DQRR reset bug... */
32055+ if (unlikely(s->dqrr.reset_bug)) {
32056+ /* We pick up new entries by cache-inhibited producer index,
32057+ * which means that a non-coherent mapping would require us to
32058+ * invalidate and read *only* once that PI has indicated that
32059+ * there's an entry here. The first trip around the DQRR ring
32060+ * will be much less efficient than all subsequent trips around
32061+ * it...
32062+ */
32063+ uint32_t dqpi = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_DQPI);
32064+ uint32_t pi = qb_attr_code_decode(&code_dqpi_pi, &dqpi);
32065+ /* there are new entries iff pi != next_idx */
32066+ if (pi == s->dqrr.next_idx)
32067+ return NULL;
32068+ /* if next_idx is/was the last ring index, and 'pi' is
32069+ * different, we can disable the workaround as all the ring
32070+ * entries have now been DMA'd to so valid-bit checking is
32071+ * repaired. Note: this logic needs to be based on next_idx
32072+ * (which increments one at a time), rather than on pi (which
32073+ * can burst and wrap-around between our snapshots of it).
32074+ */
32075+ BUG_ON((s->dqrr.dqrr_size - 1) < 0);
32076+ if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1u)) {
32077+ pr_debug("DEBUG: next_idx=%d, pi=%d, clear reset bug\n",
32078+ s->dqrr.next_idx, pi);
32079+ s->dqrr.reset_bug = 0;
32080+ }
32081+ qbman_cena_invalidate_prefetch(&s->sys,
32082+ QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
32083+ }
32084+ dq = qbman_cena_read_wo_shadow(&s->sys,
32085+ QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
32086+ p = qb_cl(dq);
32087+ verb = qb_attr_code_decode(&code_dqrr_verb, p);
32088+ /* If the valid-bit isn't of the expected polarity, nothing there. Note,
32089+ * in the DQRR reset bug workaround, we shouldn't need to skip these
32090+ * check, because we've already determined that a new entry is available
32091+ * and we've invalidated the cacheline before reading it, so the
32092+ * valid-bit behaviour is repaired and should tell us what we already
32093+ * knew from reading PI.
32094+ */
32095+ if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit)
32096+ return NULL;
32097+
32098+ /* There's something there. Move "next_idx" attention to the next ring
32099+ * entry (and prefetch it) before returning what we found. */
32100+ s->dqrr.next_idx++;
32101+ if (s->dqrr.next_idx == QBMAN_DQRR_SIZE) {
32102+ s->dqrr.next_idx = 0;
32103+ s->dqrr.valid_bit ^= QB_VALID_BIT;
32104+ }
32105+ /* If this is the final response to a volatile dequeue command
32106+ indicate that the vdq is no longer busy */
32107+ flags = qbman_result_DQ_flags(dq);
32108+ response_verb = qb_attr_code_decode(&code_dqrr_response, &verb);
32109+ if ((response_verb == QBMAN_RESULT_DQ) &&
32110+ (flags & QBMAN_DQ_STAT_VOLATILE) &&
32111+ (flags & QBMAN_DQ_STAT_EXPIRED))
32112+ atomic_inc(&s->vdq.busy);
32113+
32114+ return dq;
32115+}
32116+
32117+/* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */
32118+void qbman_swp_dqrr_consume(struct qbman_swp *s,
32119+ const struct qbman_result *dq)
32120+{
32121+ qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq));
32122+}
32123+
32124+/*********************************/
32125+/* Polling user-provided storage */
32126+/*********************************/
32127+
32128+int qbman_result_has_new_result(__attribute__((unused)) struct qbman_swp *s,
32129+ const struct qbman_result *dq)
32130+{
32131+ /* To avoid converting the little-endian DQ entry to host-endian prior
32132+ * to us knowing whether there is a valid entry or not (and run the
32133+ * risk of corrupting the incoming hardware LE write), we detect in
32134+ * hardware endianness rather than host. This means we need a different
32135+ * "code" depending on whether we are BE or LE in software, which is
32136+ * where DQRR_TOK_OFFSET comes in... */
32137+ static struct qb_attr_code code_dqrr_tok_detect =
32138+ QB_CODE(0, DQRR_TOK_OFFSET, 8);
32139+ /* The user trying to poll for a result treats "dq" as const. It is
32140+ * however the same address that was provided to us non-const in the
32141+ * first place, for directing hardware DMA to. So we can cast away the
32142+ * const because it is mutable from our perspective. */
32143+ uint32_t *p = (uint32_t *)(unsigned long)qb_cl(dq);
32144+ uint32_t token;
32145+
32146+ token = qb_attr_code_decode(&code_dqrr_tok_detect, &p[1]);
32147+ if (token != 1)
32148+ return 0;
32149+ qb_attr_code_encode(&code_dqrr_tok_detect, &p[1], 0);
32150+
32151+ /* Only now do we convert from hardware to host endianness. Also, as we
32152+ * are returning success, the user has promised not to call us again, so
32153+ * there's no risk of us converting the endianness twice... */
32154+ make_le32_n(p, 16);
32155+ return 1;
32156+}
32157+
32158+int qbman_check_command_complete(struct qbman_swp *s,
32159+ const struct qbman_result *dq)
32160+{
32161+ /* To avoid converting the little-endian DQ entry to host-endian prior
32162+ * to us knowing whether there is a valid entry or not (and run the
32163+ * risk of corrupting the incoming hardware LE write), we detect in
32164+ * hardware endianness rather than host. This means we need a different
32165+ * "code" depending on whether we are BE or LE in software, which is
32166+ * where DQRR_TOK_OFFSET comes in... */
32167+ static struct qb_attr_code code_dqrr_tok_detect =
32168+ QB_CODE(0, DQRR_TOK_OFFSET, 8);
32169+ /* The user trying to poll for a result treats "dq" as const. It is
32170+ * however the same address that was provided to us non-const in the
32171+ * first place, for directing hardware DMA to. So we can cast away the
32172+ * const because it is mutable from our perspective. */
32173+ uint32_t *p = (uint32_t *)(unsigned long)qb_cl(dq);
32174+ uint32_t token;
32175+
32176+ token = qb_attr_code_decode(&code_dqrr_tok_detect, &p[1]);
32177+ if(token!=1)
32178+ return 0;
32179+ /*When token is set it indicates that VDQ command has been fetched by qbman and
32180+ *is working on it. It is safe for software to issue another VDQ command, so
32181+ *incrementing the busy variable.*/
32182+ if (s->vdq.storage == dq) {
32183+ s->vdq.storage = NULL;
32184+ atomic_inc(&s->vdq.busy);
32185+ }
32186+ return 1;
32187+}
32188+
32189+/********************************/
32190+/* Categorising qbman results */
32191+/********************************/
32192+
32193+static struct qb_attr_code code_result_in_mem =
32194+ QB_CODE(0, QBMAN_RESULT_VERB_OFFSET_IN_MEM, 7);
32195+
32196+static inline int __qbman_result_is_x(const struct qbman_result *dq,
32197+ uint32_t x)
32198+{
32199+ const uint32_t *p = qb_cl(dq);
32200+ uint32_t response_verb = qb_attr_code_decode(&code_dqrr_response, p);
32201+ return (response_verb == x);
32202+}
32203+
32204+static inline int __qbman_result_is_x_in_mem(const struct qbman_result *dq,
32205+ uint32_t x)
32206+{
32207+ const uint32_t *p = qb_cl(dq);
32208+ uint32_t response_verb = qb_attr_code_decode(&code_result_in_mem, p);
32209+
32210+ return (response_verb == x);
32211+}
32212+
32213+int qbman_result_is_DQ(const struct qbman_result *dq)
32214+{
32215+ return __qbman_result_is_x(dq, QBMAN_RESULT_DQ);
32216+}
32217+
32218+int qbman_result_is_FQDAN(const struct qbman_result *dq)
32219+{
32220+ return __qbman_result_is_x(dq, QBMAN_RESULT_FQDAN);
32221+}
32222+
32223+int qbman_result_is_CDAN(const struct qbman_result *dq)
32224+{
32225+ return __qbman_result_is_x(dq, QBMAN_RESULT_CDAN);
32226+}
32227+
32228+int qbman_result_is_CSCN(const struct qbman_result *dq)
32229+{
32230+ return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_CSCN_MEM) ||
32231+ __qbman_result_is_x(dq, QBMAN_RESULT_CSCN_WQ);
32232+}
32233+
32234+int qbman_result_is_BPSCN(const struct qbman_result *dq)
32235+{
32236+ return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_BPSCN);
32237+}
32238+
32239+int qbman_result_is_CGCU(const struct qbman_result *dq)
32240+{
32241+ return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_CGCU);
32242+}
32243+
32244+int qbman_result_is_FQRN(const struct qbman_result *dq)
32245+{
32246+ return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_FQRN);
32247+}
32248+
32249+int qbman_result_is_FQRNI(const struct qbman_result *dq)
32250+{
32251+ return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_FQRNI);
32252+}
32253+
32254+int qbman_result_is_FQPN(const struct qbman_result *dq)
32255+{
32256+ return __qbman_result_is_x(dq, QBMAN_RESULT_FQPN);
32257+}
32258+
32259+/*********************************/
32260+/* Parsing frame dequeue results */
32261+/*********************************/
32262+
32263+/* These APIs assume qbman_result_is_DQ() is TRUE */
32264+
32265+uint32_t qbman_result_DQ_flags(const struct qbman_result *dq)
32266+{
32267+ const uint32_t *p = qb_cl(dq);
32268+ return qb_attr_code_decode(&code_dqrr_stat, p);
32269+}
32270+
32271+uint16_t qbman_result_DQ_seqnum(const struct qbman_result *dq)
32272+{
32273+ const uint32_t *p = qb_cl(dq);
32274+ return (uint16_t)qb_attr_code_decode(&code_dqrr_seqnum, p);
32275+}
32276+
32277+uint16_t qbman_result_DQ_odpid(const struct qbman_result *dq)
32278+{
32279+ const uint32_t *p = qb_cl(dq);
32280+ return (uint16_t)qb_attr_code_decode(&code_dqrr_odpid, p);
32281+}
32282+
32283+uint32_t qbman_result_DQ_fqid(const struct qbman_result *dq)
32284+{
32285+ const uint32_t *p = qb_cl(dq);
32286+ return qb_attr_code_decode(&code_dqrr_fqid, p);
32287+}
32288+
32289+uint32_t qbman_result_DQ_byte_count(const struct qbman_result *dq)
32290+{
32291+ const uint32_t *p = qb_cl(dq);
32292+ return qb_attr_code_decode(&code_dqrr_byte_count, p);
32293+}
32294+
32295+uint32_t qbman_result_DQ_frame_count(const struct qbman_result *dq)
32296+{
32297+ const uint32_t *p = qb_cl(dq);
32298+ return qb_attr_code_decode(&code_dqrr_frame_count, p);
32299+}
32300+
32301+uint64_t qbman_result_DQ_fqd_ctx(const struct qbman_result *dq)
32302+{
32303+ const uint64_t *p = (const uint64_t *)qb_cl(dq);
32304+
32305+ return qb_attr_code_decode_64(&code_dqrr_ctx_lo, p);
32306+}
32307+
32308+const struct qbman_fd *qbman_result_DQ_fd(const struct qbman_result *dq)
32309+{
32310+ const uint32_t *p = qb_cl(dq);
32311+ return (const struct qbman_fd *)&p[8];
32312+}
32313+
32314+/**************************************/
32315+/* Parsing state-change notifications */
32316+/**************************************/
32317+
32318+static struct qb_attr_code code_scn_state = QB_CODE(0, 16, 8);
32319+static struct qb_attr_code code_scn_rid = QB_CODE(1, 0, 24);
32320+static struct qb_attr_code code_scn_state_in_mem =
32321+ QB_CODE(0, SCN_STATE_OFFSET_IN_MEM, 8);
32322+static struct qb_attr_code code_scn_rid_in_mem =
32323+ QB_CODE(1, SCN_RID_OFFSET_IN_MEM, 24);
32324+static struct qb_attr_code code_scn_ctx_lo = QB_CODE(2, 0, 32);
32325+
32326+uint8_t qbman_result_SCN_state(const struct qbman_result *scn)
32327+{
32328+ const uint32_t *p = qb_cl(scn);
32329+ return (uint8_t)qb_attr_code_decode(&code_scn_state, p);
32330+}
32331+
32332+uint32_t qbman_result_SCN_rid(const struct qbman_result *scn)
32333+{
32334+ const uint32_t *p = qb_cl(scn);
32335+ return qb_attr_code_decode(&code_scn_rid, p);
32336+}
32337+
32338+uint64_t qbman_result_SCN_ctx(const struct qbman_result *scn)
32339+{
32340+ const uint64_t *p = (const uint64_t *)qb_cl(scn);
32341+
32342+ return qb_attr_code_decode_64(&code_scn_ctx_lo, p);
32343+}
32344+
32345+uint8_t qbman_result_SCN_state_in_mem(const struct qbman_result *scn)
32346+{
32347+ const uint32_t *p = qb_cl(scn);
32348+
32349+ return (uint8_t)qb_attr_code_decode(&code_scn_state_in_mem, p);
32350+}
32351+
32352+uint32_t qbman_result_SCN_rid_in_mem(const struct qbman_result *scn)
32353+{
32354+ const uint32_t *p = qb_cl(scn);
32355+ uint32_t result_rid;
32356+
32357+ result_rid = qb_attr_code_decode(&code_scn_rid_in_mem, p);
32358+ return make_le24(result_rid);
32359+}
32360+
32361+/*****************/
32362+/* Parsing BPSCN */
32363+/*****************/
32364+uint16_t qbman_result_bpscn_bpid(const struct qbman_result *scn)
32365+{
32366+ return (uint16_t)qbman_result_SCN_rid_in_mem(scn) & 0x3FFF;
32367+}
32368+
32369+int qbman_result_bpscn_has_free_bufs(const struct qbman_result *scn)
32370+{
32371+ return !(int)(qbman_result_SCN_state_in_mem(scn) & 0x1);
32372+}
32373+
32374+int qbman_result_bpscn_is_depleted(const struct qbman_result *scn)
32375+{
32376+ return (int)(qbman_result_SCN_state_in_mem(scn) & 0x2);
32377+}
32378+
32379+int qbman_result_bpscn_is_surplus(const struct qbman_result *scn)
32380+{
32381+ return (int)(qbman_result_SCN_state_in_mem(scn) & 0x4);
32382+}
32383+
32384+uint64_t qbman_result_bpscn_ctx(const struct qbman_result *scn)
32385+{
32386+ uint64_t ctx;
32387+ uint32_t ctx_hi, ctx_lo;
32388+
32389+ ctx = qbman_result_SCN_ctx(scn);
32390+ ctx_hi = upper32(ctx);
32391+ ctx_lo = lower32(ctx);
32392+ return ((uint64_t)make_le32(ctx_hi) << 32 |
32393+ (uint64_t)make_le32(ctx_lo));
32394+}
32395+
32396+/*****************/
32397+/* Parsing CGCU */
32398+/*****************/
32399+uint16_t qbman_result_cgcu_cgid(const struct qbman_result *scn)
32400+{
32401+ return (uint16_t)qbman_result_SCN_rid_in_mem(scn) & 0xFFFF;
32402+}
32403+
32404+uint64_t qbman_result_cgcu_icnt(const struct qbman_result *scn)
32405+{
32406+ uint64_t ctx;
32407+ uint32_t ctx_hi, ctx_lo;
32408+
32409+ ctx = qbman_result_SCN_ctx(scn);
32410+ ctx_hi = upper32(ctx);
32411+ ctx_lo = lower32(ctx);
32412+ return ((uint64_t)(make_le32(ctx_hi) & 0xFF) << 32) |
32413+ (uint64_t)make_le32(ctx_lo);
32414+}
32415+
32416+/******************/
32417+/* Buffer release */
32418+/******************/
32419+
32420+/* These should be const, eventually */
32421+/* static struct qb_attr_code code_release_num = QB_CODE(0, 0, 3); */
32422+static struct qb_attr_code code_release_set_me = QB_CODE(0, 5, 1);
32423+static struct qb_attr_code code_release_rcdi = QB_CODE(0, 6, 1);
32424+static struct qb_attr_code code_release_bpid = QB_CODE(0, 16, 16);
32425+
32426+void qbman_release_desc_clear(struct qbman_release_desc *d)
32427+{
32428+ uint32_t *cl;
32429+ memset(d, 0, sizeof(*d));
32430+ cl = qb_cl(d);
32431+ qb_attr_code_encode(&code_release_set_me, cl, 1);
32432+}
32433+
32434+void qbman_release_desc_set_bpid(struct qbman_release_desc *d, uint32_t bpid)
32435+{
32436+ uint32_t *cl = qb_cl(d);
32437+ qb_attr_code_encode(&code_release_bpid, cl, bpid);
32438+}
32439+
32440+void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable)
32441+{
32442+ uint32_t *cl = qb_cl(d);
32443+ qb_attr_code_encode(&code_release_rcdi, cl, !!enable);
32444+}
32445+
32446+#define RAR_IDX(rar) ((rar) & 0x7)
32447+#define RAR_VB(rar) ((rar) & 0x80)
32448+#define RAR_SUCCESS(rar) ((rar) & 0x100)
32449+
32450+int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
32451+ const uint64_t *buffers, unsigned int num_buffers)
32452+{
32453+ uint32_t *p;
32454+ const uint32_t *cl = qb_cl(d);
32455+ uint32_t rar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_RAR);
32456+ pr_debug("RAR=%08x\n", rar);
32457+ if (!RAR_SUCCESS(rar))
32458+ return -EBUSY;
32459+ BUG_ON(!num_buffers || (num_buffers > 7));
32460+ /* Start the release command */
32461+ p = qbman_cena_write_start_wo_shadow(&s->sys,
32462+ QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
32463+ /* Copy the caller's buffer pointers to the command */
32464+ u64_to_le32_copy(&p[2], buffers, num_buffers);
32465+ /* Set the verb byte, have to substitute in the valid-bit and the number
32466+ * of buffers. */
32467+ lwsync();
32468+ p[0] = cl[0] | RAR_VB(rar) | num_buffers;
32469+ qbman_cena_write_complete_wo_shadow(&s->sys,
32470+ QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
32471+ return 0;
32472+}
32473+
32474+/*******************/
32475+/* Buffer acquires */
32476+/*******************/
32477+
32478+/* These should be const, eventually */
32479+static struct qb_attr_code code_acquire_bpid = QB_CODE(0, 16, 16);
32480+static struct qb_attr_code code_acquire_num = QB_CODE(1, 0, 3);
32481+static struct qb_attr_code code_acquire_r_num = QB_CODE(1, 0, 3);
32482+
32483+int qbman_swp_acquire(struct qbman_swp *s, uint32_t bpid, uint64_t *buffers,
32484+ unsigned int num_buffers)
32485+{
32486+ uint32_t *p;
32487+ uint32_t rslt, num;
32488+ BUG_ON(!num_buffers || (num_buffers > 7));
32489+
32490+ /* Start the management command */
32491+ p = qbman_swp_mc_start(s);
32492+
32493+ if (!p)
32494+ return -EBUSY;
32495+
32496+ /* Encode the caller-provided attributes */
32497+ qb_attr_code_encode(&code_acquire_bpid, p, bpid);
32498+ qb_attr_code_encode(&code_acquire_num, p, num_buffers);
32499+
32500+ /* Complete the management command */
32501+ p = qbman_swp_mc_complete(s, p, p[0] | QBMAN_MC_ACQUIRE);
32502+
32503+ /* Decode the outcome */
32504+ rslt = qb_attr_code_decode(&code_generic_rslt, p);
32505+ num = qb_attr_code_decode(&code_acquire_r_num, p);
32506+ BUG_ON(qb_attr_code_decode(&code_generic_verb, p) != QBMAN_MC_ACQUIRE);
32507+
32508+ /* Determine success or failure */
32509+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
32510+ pr_err("Acquire buffers from BPID 0x%x failed, code=0x%02x\n",
32511+ bpid, rslt);
32512+ return -EIO;
32513+ }
32514+ BUG_ON(num > num_buffers);
32515+ /* Copy the acquired buffers to the caller's array */
32516+ u64_from_le32_copy(buffers, &p[2], num);
32517+ return (int)num;
32518+}
32519+
32520+/*****************/
32521+/* FQ management */
32522+/*****************/
32523+
32524+static struct qb_attr_code code_fqalt_fqid = QB_CODE(1, 0, 32);
32525+
32526+static int qbman_swp_alt_fq_state(struct qbman_swp *s, uint32_t fqid,
32527+ uint8_t alt_fq_verb)
32528+{
32529+ uint32_t *p;
32530+ uint32_t rslt;
32531+
32532+ /* Start the management command */
32533+ p = qbman_swp_mc_start(s);
32534+ if (!p)
32535+ return -EBUSY;
32536+
32537+ qb_attr_code_encode(&code_fqalt_fqid, p, fqid);
32538+ /* Complete the management command */
32539+ p = qbman_swp_mc_complete(s, p, p[0] | alt_fq_verb);
32540+
32541+ /* Decode the outcome */
32542+ rslt = qb_attr_code_decode(&code_generic_rslt, p);
32543+ BUG_ON(qb_attr_code_decode(&code_generic_verb, p) != alt_fq_verb);
32544+
32545+ /* Determine success or failure */
32546+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
32547+ pr_err("ALT FQID %d failed: verb = 0x%08x, code = 0x%02x\n",
32548+ fqid, alt_fq_verb, rslt);
32549+ return -EIO;
32550+ }
32551+
32552+ return 0;
32553+}
32554+
32555+int qbman_swp_fq_schedule(struct qbman_swp *s, uint32_t fqid)
32556+{
32557+ return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_SCHEDULE);
32558+}
32559+
32560+int qbman_swp_fq_force(struct qbman_swp *s, uint32_t fqid)
32561+{
32562+ return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_FORCE);
32563+}
32564+
32565+int qbman_swp_fq_xon(struct qbman_swp *s, uint32_t fqid)
32566+{
32567+ return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XON);
32568+}
32569+
32570+int qbman_swp_fq_xoff(struct qbman_swp *s, uint32_t fqid)
32571+{
32572+ return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XOFF);
32573+}
32574+
32575+/**********************/
32576+/* Channel management */
32577+/**********************/
32578+
32579+static struct qb_attr_code code_cdan_cid = QB_CODE(0, 16, 12);
32580+static struct qb_attr_code code_cdan_we = QB_CODE(1, 0, 8);
32581+static struct qb_attr_code code_cdan_en = QB_CODE(1, 8, 1);
32582+static struct qb_attr_code code_cdan_ctx_lo = QB_CODE(2, 0, 32);
32583+
32584+/* Hide "ICD" for now as we don't use it, don't set it, and don't test it, so it
32585+ * would be irresponsible to expose it. */
32586+#define CODE_CDAN_WE_EN 0x1
32587+#define CODE_CDAN_WE_CTX 0x4
32588+
32589+static int qbman_swp_CDAN_set(struct qbman_swp *s, uint16_t channelid,
32590+ uint8_t we_mask, uint8_t cdan_en,
32591+ uint64_t ctx)
32592+{
32593+ uint32_t *p;
32594+ uint32_t rslt;
32595+
32596+ /* Start the management command */
32597+ p = qbman_swp_mc_start(s);
32598+ if (!p)
32599+ return -EBUSY;
32600+
32601+ /* Encode the caller-provided attributes */
32602+ qb_attr_code_encode(&code_cdan_cid, p, channelid);
32603+ qb_attr_code_encode(&code_cdan_we, p, we_mask);
32604+ qb_attr_code_encode(&code_cdan_en, p, cdan_en);
32605+ qb_attr_code_encode_64(&code_cdan_ctx_lo, (uint64_t *)p, ctx);
32606+ /* Complete the management command */
32607+ p = qbman_swp_mc_complete(s, p, p[0] | QBMAN_WQCHAN_CONFIGURE);
32608+
32609+ /* Decode the outcome */
32610+ rslt = qb_attr_code_decode(&code_generic_rslt, p);
32611+ BUG_ON(qb_attr_code_decode(&code_generic_verb, p)
32612+ != QBMAN_WQCHAN_CONFIGURE);
32613+
32614+ /* Determine success or failure */
32615+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
32616+ pr_err("CDAN cQID %d failed: code = 0x%02x\n",
32617+ channelid, rslt);
32618+ return -EIO;
32619+ }
32620+
32621+ return 0;
32622+}
32623+
32624+int qbman_swp_CDAN_set_context(struct qbman_swp *s, uint16_t channelid,
32625+ uint64_t ctx)
32626+{
32627+ return qbman_swp_CDAN_set(s, channelid,
32628+ CODE_CDAN_WE_CTX,
32629+ 0, ctx);
32630+}
32631+
32632+int qbman_swp_CDAN_enable(struct qbman_swp *s, uint16_t channelid)
32633+{
32634+ return qbman_swp_CDAN_set(s, channelid,
32635+ CODE_CDAN_WE_EN,
32636+ 1, 0);
32637+}
32638+
32639+int qbman_swp_CDAN_disable(struct qbman_swp *s, uint16_t channelid)
32640+{
32641+ return qbman_swp_CDAN_set(s, channelid,
32642+ CODE_CDAN_WE_EN,
32643+ 0, 0);
32644+}
32645+
32646+int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s, uint16_t channelid,
32647+ uint64_t ctx)
32648+{
32649+ return qbman_swp_CDAN_set(s, channelid,
32650+ CODE_CDAN_WE_EN | CODE_CDAN_WE_CTX,
32651+ 1, ctx);
32652+}
32653+
32654+uint8_t qbman_get_dqrr_idx(struct qbman_result *dqrr)
32655+{
32656+ return QBMAN_IDX_FROM_DQRR(dqrr);
32657+}
32658+
32659+struct qbman_result *qbman_get_dqrr_from_idx(struct qbman_swp *s, uint8_t idx)
32660+{
32661+ struct qbman_result *dq;
32662+ dq = qbman_cena_read(&s->sys, QBMAN_CENA_SWP_DQRR(idx));
32663+ return dq;
32664+}
32665+
32666+int qbman_swp_send_multiple(struct qbman_swp *s,
32667+ const struct qbman_eq_desc *d,
32668+ const struct qbman_fd *fd,
32669+ int frames_to_send)
32670+{
32671+ uint32_t *p;
32672+ const uint32_t *cl = qb_cl(d);
32673+ uint32_t eqcr_ci;
32674+ uint8_t diff;
32675+ int sent = 0;
32676+ int i;
32677+ int initial_pi = s->eqcr.pi;
32678+ uint64_t start_pointer;
32679+
32680+
32681+ /* we are trying to send frames_to_send if we have enough space in the ring */
32682+ while(frames_to_send--)
32683+ {
32684+ if (!s->eqcr.available) {
32685+ eqcr_ci = s->eqcr.ci;
32686+ s->eqcr.ci = qbman_cena_read_reg(&s->sys,
32687+ QBMAN_CENA_SWP_EQCR_CI) & 0xF;
32688+ diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
32689+ eqcr_ci, s->eqcr.ci);
32690+ s->eqcr.available += diff;
32691+ if (!diff)
32692+ {
32693+ goto done;
32694+ }
32695+ }
32696+
32697+ p = qbman_cena_write_start_wo_shadow_fast(&s->sys,
32698+ QBMAN_CENA_SWP_EQCR((initial_pi) & 7));
32699+ /* Write command (except of first byte) and FD */
32700+ memcpy(&p[1], &cl[1], 7);
32701+ memcpy(&p[8], &fd[sent], sizeof(struct qbman_fd));
32702+
32703+ initial_pi++;
32704+ initial_pi &= 0xF;
32705+ s->eqcr.available--;
32706+ sent++;
32707+
32708+ }
32709+
32710+ done:
32711+ initial_pi = s->eqcr.pi;
32712+ lwsync();
32713+
32714+ /* in order for flushes to complete faster */
32715+ /*For that we use a following trick: we record all lines in 32 bit word */
32716+
32717+ initial_pi = s->eqcr.pi;
32718+ for(i = 0; i < sent; i++)
32719+ {
32720+ p = qbman_cena_write_start_wo_shadow_fast(&s->sys,
32721+ QBMAN_CENA_SWP_EQCR((initial_pi) & 7));
32722+
32723+ p[0] = cl[0] | s->eqcr.pi_vb;
32724+ initial_pi++;
32725+ initial_pi &= 0xF;
32726+
32727+ if (!(initial_pi & 7))
32728+ s->eqcr.pi_vb ^= QB_VALID_BIT;
32729+
32730+ }
32731+
32732+ initial_pi = s->eqcr.pi;
32733+
32734+ /* We need to flush all the lines but without load/store operations between them */
32735+ /* We assign start_pointer before we start loop so that in loop we do not read it from memory */
32736+ start_pointer = (uint64_t) s->sys.addr_cena;
32737+ for(i = 0; i < sent; i++)
32738+ {
32739+ p = (uint32_t *)(start_pointer + QBMAN_CENA_SWP_EQCR(initial_pi & 7));
32740+ dcbf((uint64_t)p);
32741+ initial_pi++;
32742+ initial_pi &= 0xF;
32743+ }
32744+
32745+ /* Update producer index for the next call */
32746+ s->eqcr.pi = initial_pi;
32747+
32748+ return sent;
32749+}
32750diff --git a/drivers/net/dpaa2/qbman/driver/qbman_portal.h b/drivers/net/dpaa2/qbman/driver/qbman_portal.h
32751new file mode 100644
32752index 0000000..f6ba86a
32753--- /dev/null
32754+++ b/drivers/net/dpaa2/qbman/driver/qbman_portal.h
32755@@ -0,0 +1,266 @@
32756+/* Copyright (C) 2014 Freescale Semiconductor, Inc.
32757+ *
32758+ * Redistribution and use in source and binary forms, with or without
32759+ * modification, are permitted provided that the following conditions are met:
32760+ * * Redistributions of source code must retain the above copyright
32761+ * notice, this list of conditions and the following disclaimer.
32762+ * * Redistributions in binary form must reproduce the above copyright
32763+ * notice, this list of conditions and the following disclaimer in the
32764+ * documentation and/or other materials provided with the distribution.
32765+ * * Neither the name of Freescale Semiconductor nor the
32766+ * names of its contributors may be used to endorse or promote products
32767+ * derived from this software without specific prior written permission.
32768+ *
32769+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
32770+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32771+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32772+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
32773+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32774+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32775+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32776+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32777+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32778+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32779+ */
32780+
32781+#include "qbman_private.h"
32782+#include <drivers/fsl_qbman_portal.h>
32783+
32784+uint32_t qman_version;
32785+/* All QBMan command and result structures use this "valid bit" encoding */
32786+#define QB_VALID_BIT ((uint32_t)0x80)
32787+
32788+/* Management command result codes */
32789+#define QBMAN_MC_RSLT_OK 0xf0
32790+
32791+/* TBD: as of QBMan 4.1, DQRR will be 8 rather than 4! */
32792+#define QBMAN_DQRR_SIZE 4
32793+
32794+#define QBMAN_EQCR_SIZE 8
32795+
32796+static inline u8 qm_cyc_diff(u8 ringsize, u8 first, u8 last)
32797+{
32798+ /* 'first' is included, 'last' is excluded */
32799+ if (first <= last)
32800+ return last - first;
32801+ return (2 * ringsize) + last - first;
32802+}
32803+
32804+/* --------------------- */
32805+/* portal data structure */
32806+/* --------------------- */
32807+
32808+struct qbman_swp {
32809+ const struct qbman_swp_desc *desc;
32810+ /* The qbman_sys (ie. arch/OS-specific) support code can put anything it
32811+ * needs in here. */
32812+ struct qbman_swp_sys sys;
32813+ /* Management commands */
32814+ struct {
32815+#ifdef QBMAN_CHECKING
32816+ enum swp_mc_check {
32817+ swp_mc_can_start, /* call __qbman_swp_mc_start() */
32818+ swp_mc_can_submit, /* call __qbman_swp_mc_submit() */
32819+ swp_mc_can_poll, /* call __qbman_swp_mc_result() */
32820+ } check;
32821+#endif
32822+ uint32_t valid_bit; /* 0x00 or 0x80 */
32823+ } mc;
32824+ /* Push dequeues */
32825+ uint32_t sdq;
32826+ /* Volatile dequeues */
32827+ struct {
32828+ /* VDQCR supports a "1 deep pipeline", meaning that if you know
32829+ * the last-submitted command is already executing in the
32830+ * hardware (as evidenced by at least 1 valid dequeue result),
32831+ * you can write another dequeue command to the register, the
32832+ * hardware will start executing it as soon as the
32833+ * already-executing command terminates. (This minimises latency
32834+ * and stalls.) With that in mind, this "busy" variable refers
32835+ * to whether or not a command can be submitted, not whether or
32836+ * not a previously-submitted command is still executing. In
32837+ * other words, once proof is seen that the previously-submitted
32838+ * command is executing, "vdq" is no longer "busy". */
32839+ atomic_t busy;
32840+ uint32_t valid_bit; /* 0x00 or 0x80 */
32841+ /* We need to determine when vdq is no longer busy. This depends
32842+ * on whether the "busy" (last-submitted) dequeue command is
32843+ * targetting DQRR or main-memory, and detected is based on the
32844+ * presence of the dequeue command's "token" showing up in
32845+ * dequeue entries in DQRR or main-memory (respectively). */
32846+ struct qbman_result *storage; /* NULL if DQRR */
32847+ } vdq;
32848+ /* DQRR */
32849+ struct {
32850+ uint32_t next_idx;
32851+ uint32_t valid_bit;
32852+ uint8_t dqrr_size;
32853+ int reset_bug;
32854+ } dqrr;
32855+ struct {
32856+ uint32_t pi;
32857+ uint32_t pi_vb;
32858+ uint32_t ci;
32859+ int available;
32860+ } eqcr;
32861+};
32862+
32863+/* -------------------------- */
32864+/* portal management commands */
32865+/* -------------------------- */
32866+
32867+/* Different management commands all use this common base layer of code to issue
32868+ * commands and poll for results. The first function returns a pointer to where
32869+ * the caller should fill in their MC command (though they should ignore the
32870+ * verb byte), the second function commits merges in the caller-supplied command
32871+ * verb (which should not include the valid-bit) and submits the command to
32872+ * hardware, and the third function checks for a completed response (returns
32873+ * non-NULL if only if the response is complete). */
32874+void *qbman_swp_mc_start(struct qbman_swp *p);
32875+void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb);
32876+void *qbman_swp_mc_result(struct qbman_swp *p);
32877+
32878+/* Wraps up submit + poll-for-result */
32879+static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd,
32880+ uint32_t cmd_verb)
32881+{
32882+ int loopvar;
32883+ qbman_swp_mc_submit(swp, cmd, cmd_verb);
32884+ DBG_POLL_START(loopvar);
32885+ do {
32886+ DBG_POLL_CHECK(loopvar);
32887+ cmd = qbman_swp_mc_result(swp);
32888+ } while (!cmd);
32889+ return cmd;
32890+}
32891+
32892+/* ------------ */
32893+/* qb_attr_code */
32894+/* ------------ */
32895+
32896+/* This struct locates a sub-field within a QBMan portal (CENA) cacheline which
32897+ * is either serving as a configuration command or a query result. The
32898+ * representation is inherently little-endian, as the indexing of the words is
32899+ * itself little-endian in nature and DPAA2 QBMan is little endian for anything
32900+ * that crosses a word boundary too (64-bit fields are the obvious examples).
32901+ */
32902+struct qb_attr_code {
32903+ unsigned int word; /* which uint32_t[] array member encodes the field */
32904+ unsigned int lsoffset; /* encoding offset from ls-bit */
32905+ unsigned int width; /* encoding width. (bool must be 1.) */
32906+};
32907+
32908+/* Some pre-defined codes */
32909+extern struct qb_attr_code code_generic_verb;
32910+extern struct qb_attr_code code_generic_rslt;
32911+
32912+/* Macros to define codes */
32913+#define QB_CODE(a, b, c) { a, b, c}
32914+#define QB_CODE_NULL \
32915+ QB_CODE((unsigned int)-1, (unsigned int)-1, (unsigned int)-1)
32916+
32917+/* Rotate a code "ms", meaning that it moves from less-significant bytes to
32918+ * more-significant, from less-significant words to more-significant, etc. The
32919+ * "ls" version does the inverse, from more-significant towards
32920+ * less-significant.
32921+ */
32922+static inline void qb_attr_code_rotate_ms(struct qb_attr_code *code,
32923+ unsigned int bits)
32924+{
32925+ code->lsoffset += bits;
32926+ while (code->lsoffset > 31) {
32927+ code->word++;
32928+ code->lsoffset -= 32;
32929+ }
32930+}
32931+static inline void qb_attr_code_rotate_ls(struct qb_attr_code *code,
32932+ unsigned int bits)
32933+{
32934+ /* Don't be fooled, this trick should work because the types are
32935+ * unsigned. So the case that interests the while loop (the rotate has
32936+ * gone too far and the word count needs to compensate for it), is
32937+ * manifested when lsoffset is negative. But that equates to a really
32938+ * large unsigned value, starting with lots of "F"s. As such, we can
32939+ * continue adding 32 back to it until it wraps back round above zero,
32940+ * to a value of 31 or less...
32941+ */
32942+ code->lsoffset -= bits;
32943+ while (code->lsoffset > 31) {
32944+ code->word--;
32945+ code->lsoffset += 32;
32946+ }
32947+}
32948+/* Implement a loop of code rotations until 'expr' evaluates to FALSE (0). */
32949+#define qb_attr_code_for_ms(code, bits, expr) \
32950+ for (; expr; qb_attr_code_rotate_ms(code, bits))
32951+#define qb_attr_code_for_ls(code, bits, expr) \
32952+ for (; expr; qb_attr_code_rotate_ls(code, bits))
32953+
32954+/* decode a field from a cacheline */
32955+static inline uint32_t qb_attr_code_decode(const struct qb_attr_code *code,
32956+ const uint32_t *cacheline)
32957+{
32958+ return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]);
32959+}
32960+static inline uint64_t qb_attr_code_decode_64(const struct qb_attr_code *code,
32961+ const uint64_t *cacheline)
32962+{
32963+ return cacheline[code->word / 2];
32964+}
32965+
32966+/* encode a field to a cacheline */
32967+static inline void qb_attr_code_encode(const struct qb_attr_code *code,
32968+ uint32_t *cacheline, uint32_t val)
32969+{
32970+ cacheline[code->word] =
32971+ r32_uint32_t(code->lsoffset, code->width, cacheline[code->word])
32972+ | e32_uint32_t(code->lsoffset, code->width, val);
32973+}
32974+static inline void qb_attr_code_encode_64(const struct qb_attr_code *code,
32975+ uint64_t *cacheline, uint64_t val)
32976+{
32977+ cacheline[code->word / 2] = val;
32978+}
32979+
32980+/* Small-width signed values (two's-complement) will decode into medium-width
32981+ * positives. (Eg. for an 8-bit signed field, which stores values from -128 to
32982+ * +127, a setting of -7 would appear to decode to the 32-bit unsigned value
32983+ * 249. Likewise -120 would decode as 136.) This function allows the caller to
32984+ * "re-sign" such fields to 32-bit signed. (Eg. -7, which was 249 with an 8-bit
32985+ * encoding, will become 0xfffffff9 if you cast the return value to uint32_t).
32986+ */
32987+static inline int32_t qb_attr_code_makesigned(const struct qb_attr_code *code,
32988+ uint32_t val)
32989+{
32990+ BUG_ON(val >= (1u << code->width));
32991+ /* code->width should never exceed the width of val. If it does then a
32992+ * different function with larger val size must be used to translate
32993+ * from unsigned to signed */
32994+ BUG_ON(code->width > sizeof(val) * CHAR_BIT);
32995+ /* If the high bit was set, it was encoding a negative */
32996+ if (val >= 1u << (code->width - 1))
32997+ return (int32_t)0 - (int32_t)(((uint32_t)1 << code->width) -
32998+ val);
32999+ /* Otherwise, it was encoding a positive */
33000+ return (int32_t)val;
33001+}
33002+
33003+/* ---------------------- */
33004+/* Descriptors/cachelines */
33005+/* ---------------------- */
33006+
33007+/* To avoid needless dynamic allocation, the driver API often gives the caller
33008+ * a "descriptor" type that the caller can instantiate however they like.
33009+ * Ultimately though, it is just a cacheline of binary storage (or something
33010+ * smaller when it is known that the descriptor doesn't need all 64 bytes) for
33011+ * holding pre-formatted pieces of harware commands. The performance-critical
33012+ * code can then copy these descriptors directly into hardware command
33013+ * registers more efficiently than trying to construct/format commands
33014+ * on-the-fly. The API user sees the descriptor as an array of 32-bit words in
33015+ * order for the compiler to know its size, but the internal details are not
33016+ * exposed. The following macro is used within the driver for converting *any*
33017+ * descriptor pointer to a usable array pointer. The use of a macro (instead of
33018+ * an inline) is necessary to work with different descriptor types and to work
33019+ * correctly with const and non-const inputs (and similarly-qualified outputs).
33020+ */
33021+#define qb_cl(d) (&(d)->dont_manipulate_directly[0])
33022diff --git a/drivers/net/dpaa2/qbman/driver/qbman_private.h b/drivers/net/dpaa2/qbman/driver/qbman_private.h
33023new file mode 100644
33024index 0000000..4e50b61
33025--- /dev/null
33026+++ b/drivers/net/dpaa2/qbman/driver/qbman_private.h
33027@@ -0,0 +1,165 @@
33028+/* Copyright (C) 2014 Freescale Semiconductor, Inc.
33029+ *
33030+ * Redistribution and use in source and binary forms, with or without
33031+ * modification, are permitted provided that the following conditions are met:
33032+ * * Redistributions of source code must retain the above copyright
33033+ * notice, this list of conditions and the following disclaimer.
33034+ * * Redistributions in binary form must reproduce the above copyright
33035+ * notice, this list of conditions and the following disclaimer in the
33036+ * documentation and/or other materials provided with the distribution.
33037+ * * Neither the name of Freescale Semiconductor nor the
33038+ * names of its contributors may be used to endorse or promote products
33039+ * derived from this software without specific prior written permission.
33040+ *
33041+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
33042+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33043+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33044+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
33045+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
33046+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33047+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
33048+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33049+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33050+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33051+*/
33052+
33053+/* Perform extra checking */
33054+#define QBMAN_CHECKING
33055+
33056+/* To maximise the amount of logic that is common between the Linux driver and
33057+ * other targets (such as the embedded MC firmware), we pivot here between the
33058+ * inclusion of two platform-specific headers.
33059+ *
33060+ * The first, qbman_sys_decl.h, includes any and all required system headers as
33061+ * well as providing any definitions for the purposes of compatibility. The
33062+ * second, qbman_sys.h, is where platform-specific routines go.
33063+ *
33064+ * The point of the split is that the platform-independent code (including this
33065+ * header) may depend on platform-specific declarations, yet other
33066+ * platform-specific routines may depend on platform-independent definitions.
33067+ */
33068+
33069+#include "qbman_sys_decl.h"
33070+
33071+/* When things go wrong, it is a convenient trick to insert a few FOO()
33072+ * statements in the code to trace progress. TODO: remove this once we are
33073+ * hacking the code less actively.
33074+ */
33075+#define FOO() fsl_os_print("FOO: %s:%d\n", __FILE__, __LINE__)
33076+
33077+/* Any time there is a register interface which we poll on, this provides a
33078+ * "break after x iterations" scheme for it. It's handy for debugging, eg.
33079+ * where you don't want millions of lines of log output from a polling loop
33080+ * that won't, because such things tend to drown out the earlier log output
33081+ * that might explain what caused the problem. (NB: put ";" after each macro!)
33082+ * TODO: we should probably remove this once we're done sanitising the
33083+ * simulator...
33084+ */
33085+#define DBG_POLL_START(loopvar) (loopvar = 10)
33086+#define DBG_POLL_CHECK(loopvar) \
33087+ do {if (!(loopvar--)) BUG_ON(NULL == "DBG_POLL_CHECK"); } while (0)
33088+
33089+/* For CCSR or portal-CINH registers that contain fields at arbitrary offsets
33090+ * and widths, these macro-generated encode/decode/isolate/remove inlines can
33091+ * be used.
33092+ *
33093+ * Eg. to "d"ecode a 14-bit field out of a register (into a "uint16_t" type),
33094+ * where the field is located 3 bits "up" from the least-significant bit of the
33095+ * register (ie. the field location within the 32-bit register corresponds to a
33096+ * mask of 0x0001fff8), you would do;
33097+ * uint16_t field = d32_uint16_t(3, 14, reg_value);
33098+ *
33099+ * Or to "e"ncode a 1-bit boolean value (input type is "int", zero is FALSE,
33100+ * non-zero is TRUE, so must convert all non-zero inputs to 1, hence the "!!"
33101+ * operator) into a register at bit location 0x00080000 (19 bits "in" from the
33102+ * LS bit), do;
33103+ * reg_value |= e32_int(19, 1, !!field);
33104+ *
33105+ * If you wish to read-modify-write a register, such that you leave the 14-bit
33106+ * field as-is but have all other fields set to zero, then "i"solate the 14-bit
33107+ * value using;
33108+ * reg_value = i32_uint16_t(3, 14, reg_value);
33109+ *
33110+ * Alternatively, you could "r"emove the 1-bit boolean field (setting it to
33111+ * zero) but leaving all other fields as-is;
33112+ * reg_val = r32_int(19, 1, reg_value);
33113+ *
33114+ */
33115+#define MAKE_MASK32(width) (width == 32 ? 0xffffffff : \
33116+ (uint32_t)((1 << width) - 1))
33117+#define DECLARE_CODEC32(t) \
33118+static inline uint32_t e32_##t(uint32_t lsoffset, uint32_t width, t val) \
33119+{ \
33120+ BUG_ON(width > (sizeof(t) * 8)); \
33121+ return ((uint32_t)val & MAKE_MASK32(width)) << lsoffset; \
33122+} \
33123+static inline t d32_##t(uint32_t lsoffset, uint32_t width, uint32_t val) \
33124+{ \
33125+ BUG_ON(width > (sizeof(t) * 8)); \
33126+ return (t)((val >> lsoffset) & MAKE_MASK32(width)); \
33127+} \
33128+static inline uint32_t i32_##t(uint32_t lsoffset, uint32_t width, \
33129+ uint32_t val) \
33130+{ \
33131+ BUG_ON(width > (sizeof(t) * 8)); \
33132+ return e32_##t(lsoffset, width, d32_##t(lsoffset, width, val)); \
33133+} \
33134+static inline uint32_t r32_##t(uint32_t lsoffset, uint32_t width, \
33135+ uint32_t val) \
33136+{ \
33137+ BUG_ON(width > (sizeof(t) * 8)); \
33138+ return ~(MAKE_MASK32(width) << lsoffset) & val; \
33139+}
33140+DECLARE_CODEC32(uint32_t)
33141+DECLARE_CODEC32(uint16_t)
33142+DECLARE_CODEC32(uint8_t)
33143+DECLARE_CODEC32(int)
33144+
33145+ /*********************/
33146+ /* Debugging assists */
33147+ /*********************/
33148+
33149+static inline void __hexdump(unsigned long start, unsigned long end,
33150+ unsigned long p, size_t sz, const unsigned char *c)
33151+{
33152+ while (start < end) {
33153+ unsigned int pos = 0;
33154+ char buf[64];
33155+ int nl = 0;
33156+ pos += sprintf(buf + pos, "%08lx: ", start);
33157+ do {
33158+ if ((start < p) || (start >= (p + sz)))
33159+ pos += sprintf(buf + pos, "..");
33160+ else
33161+ pos += sprintf(buf + pos, "%02x", *(c++));
33162+ if (!(++start & 15)) {
33163+ buf[pos++] = '\n';
33164+ nl = 1;
33165+ } else {
33166+ nl = 0;
33167+ if (!(start & 1))
33168+ buf[pos++] = ' ';
33169+ if (!(start & 3))
33170+ buf[pos++] = ' ';
33171+ }
33172+ } while (start & 15);
33173+ if (!nl)
33174+ buf[pos++] = '\n';
33175+ buf[pos] = '\0';
33176+ pr_info("%s", buf);
33177+ }
33178+}
33179+static inline void hexdump(const void *ptr, size_t sz)
33180+{
33181+ unsigned long p = (unsigned long)ptr;
33182+ unsigned long start = p & ~(unsigned long)15;
33183+ unsigned long end = (p + sz + 15) & ~(unsigned long)15;
33184+ const unsigned char *c = ptr;
33185+ __hexdump(start, end, p, sz, c);
33186+}
33187+
33188+#define QMAN_REV_4000 0x04000000
33189+#define QMAN_REV_4100 0x04010000
33190+#define QMAN_REV_4101 0x04010001
33191+
33192+#include "qbman_sys.h"
33193diff --git a/drivers/net/dpaa2/qbman/driver/qbman_sys.h b/drivers/net/dpaa2/qbman/driver/qbman_sys.h
33194new file mode 100644
33195index 0000000..d912ab0
33196--- /dev/null
33197+++ b/drivers/net/dpaa2/qbman/driver/qbman_sys.h
33198@@ -0,0 +1,367 @@
33199+/* Copyright (C) 2014 Freescale Semiconductor, Inc.
33200+ *
33201+ * Redistribution and use in source and binary forms, with or without
33202+ * modification, are permitted provided that the following conditions are met:
33203+ * * Redistributions of source code must retain the above copyright
33204+ * notice, this list of conditions and the following disclaimer.
33205+ * * Redistributions in binary form must reproduce the above copyright
33206+ * notice, this list of conditions and the following disclaimer in the
33207+ * documentation and/or other materials provided with the distribution.
33208+ * * Neither the name of Freescale Semiconductor nor the
33209+ * names of its contributors may be used to endorse or promote products
33210+ * derived from this software without specific prior written permission.
33211+ *
33212+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
33213+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33214+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33215+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
33216+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
33217+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33218+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
33219+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33220+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33221+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33222+ */
33223+/* qbman_sys_decl.h and qbman_sys.h are the two platform-specific files in the
33224+ * driver. They are only included via qbman_private.h, which is itself a
33225+ * platform-independent file and is included by all the other driver source.
33226+ *
33227+ * qbman_sys_decl.h is included prior to all other declarations and logic, and
33228+ * it exists to provide compatibility with any linux interfaces our
33229+ * single-source driver code is dependent on (eg. kmalloc). Ie. this file
33230+ * provides linux compatibility.
33231+ *
33232+ * This qbman_sys.h header, on the other hand, is included *after* any common
33233+ * and platform-neutral declarations and logic in qbman_private.h, and exists to
33234+ * implement any platform-specific logic of the qbman driver itself. Ie. it is
33235+ * *not* to provide linux compatibility.
33236+ */
33237+
33238+/* Trace the 3 different classes of read/write access to QBMan. #undef as
33239+ * required. */
33240+#undef QBMAN_CCSR_TRACE
33241+#undef QBMAN_CINH_TRACE
33242+#undef QBMAN_CENA_TRACE
33243+
33244+static inline void word_copy(void *d, const void *s, unsigned int cnt)
33245+{
33246+ uint32_t *dd = d;
33247+ const uint32_t *ss = s;
33248+ while (cnt--)
33249+ *(dd++) = *(ss++);
33250+}
33251+
33252+/* Currently, the CENA support code expects each 32-bit word to be written in
33253+ * host order, and these are converted to hardware (little-endian) order on
33254+ * command submission. However, 64-bit quantities are must be written (and read)
33255+ * as two 32-bit words with the least-significant word first, irrespective of
33256+ * host endianness. */
33257+static inline void u64_to_le32_copy(void *d, const uint64_t *s,
33258+ unsigned int cnt)
33259+{
33260+ uint32_t *dd = d;
33261+ const uint32_t *ss = (const uint32_t *)s;
33262+ while (cnt--) {
33263+ /* TBD: the toolchain was choking on the use of 64-bit types up
33264+ * until recently so this works entirely with 32-bit variables.
33265+ * When 64-bit types become usable again, investigate better
33266+ * ways of doing this. */
33267+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
33268+ *(dd++) = ss[1];
33269+ *(dd++) = ss[0];
33270+ ss += 2;
33271+#else
33272+ *(dd++) = *(ss++);
33273+ *(dd++) = *(ss++);
33274+#endif
33275+ }
33276+}
33277+static inline void u64_from_le32_copy(uint64_t *d, const void *s,
33278+ unsigned int cnt)
33279+{
33280+ const uint32_t *ss = s;
33281+ uint32_t *dd = (uint32_t *)d;
33282+ while (cnt--) {
33283+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
33284+ dd[1] = *(ss++);
33285+ dd[0] = *(ss++);
33286+ dd += 2;
33287+#else
33288+ *(dd++) = *(ss++);
33289+ *(dd++) = *(ss++);
33290+#endif
33291+ }
33292+}
33293+
33294+/* Convert a host-native 32bit value into little endian */
33295+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
33296+static inline uint32_t make_le32(uint32_t val)
33297+{
33298+ return ((val & 0xff) << 24) | ((val & 0xff00) << 8) |
33299+ ((val & 0xff0000) >> 8) | ((val & 0xff000000) >> 24);
33300+}
33301+static inline uint32_t make_le24(uint32_t val)
33302+{
33303+ return (((val & 0xff) << 16) | (val & 0xff00) |
33304+ ((val & 0xff0000) >> 16));
33305+}
33306+#else
33307+#define make_le32(val) (val)
33308+#define make_le24(val) (val)
33309+#endif
33310+static inline void make_le32_n(uint32_t *val, unsigned int num)
33311+{
33312+ while (num--) {
33313+ *val = make_le32(*val);
33314+ val++;
33315+ }
33316+}
33317+
33318+ /******************/
33319+ /* Portal access */
33320+ /******************/
33321+struct qbman_swp_sys {
33322+ /* On GPP, the sys support for qbman_swp is here. The CENA region isi
33323+ * not an mmap() of the real portal registers, but an allocated
33324+ * place-holder, because the actual writes/reads to/from the portal are
33325+ * marshalled from these allocated areas using QBMan's "MC access
33326+ * registers". CINH accesses are atomic so there's no need for a
33327+ * place-holder. */
33328+ uint8_t *cena;
33329+ uint8_t __iomem *addr_cena;
33330+ uint8_t __iomem *addr_cinh;
33331+ uint32_t idx;
33332+ enum qbman_eqcr_mode eqcr_mode;
33333+};
33334+
33335+/* P_OFFSET is (ACCESS_CMD,0,12) - offset within the portal
33336+ * C is (ACCESS_CMD,12,1) - is inhibited? (0==CENA, 1==CINH)
33337+ * SWP_IDX is (ACCESS_CMD,16,10) - Software portal index
33338+ * P is (ACCESS_CMD,28,1) - (0==special portal, 1==any portal)
33339+ * T is (ACCESS_CMD,29,1) - Command type (0==READ, 1==WRITE)
33340+ * E is (ACCESS_CMD,31,1) - Command execute (1 to issue, poll for 0==complete)
33341+ */
33342+
33343+static inline void qbman_cinh_write(struct qbman_swp_sys *s, uint32_t offset,
33344+ uint32_t val)
33345+{
33346+
33347+ __raw_writel(val, s->addr_cinh + offset);
33348+#ifdef QBMAN_CINH_TRACE
33349+ pr_info("qbman_cinh_write(%p:%d:0x%03x) 0x%08x\n",
33350+ s->addr_cinh, s->idx, offset, val);
33351+#endif
33352+}
33353+
33354+static inline uint32_t qbman_cinh_read(struct qbman_swp_sys *s, uint32_t offset)
33355+{
33356+ uint32_t reg = __raw_readl(s->addr_cinh + offset);
33357+#ifdef QBMAN_CINH_TRACE
33358+ pr_info("qbman_cinh_read(%p:%d:0x%03x) 0x%08x\n",
33359+ s->addr_cinh, s->idx, offset, reg);
33360+#endif
33361+ return reg;
33362+}
33363+
33364+static inline void *qbman_cena_write_start(struct qbman_swp_sys *s,
33365+ uint32_t offset)
33366+{
33367+ void *shadow = s->cena + offset;
33368+
33369+#ifdef QBMAN_CENA_TRACE
33370+ pr_info("qbman_cena_write_start(%p:%d:0x%03x) %p\n",
33371+ s->addr_cena, s->idx, offset, shadow);
33372+#endif
33373+ BUG_ON(offset & 63);
33374+ dcbz(shadow);
33375+ return shadow;
33376+}
33377+
33378+static inline void *qbman_cena_write_start_wo_shadow(struct qbman_swp_sys *s,
33379+ uint32_t offset)
33380+{
33381+#ifdef QBMAN_CENA_TRACE
33382+ pr_info("qbman_cena_write_start(%p:%d:0x%03x)\n",
33383+ s->addr_cena, s->idx, offset);
33384+#endif
33385+ BUG_ON(offset & 63);
33386+ return (s->addr_cena + offset);
33387+}
33388+
33389+static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
33390+ uint32_t offset, void *cmd)
33391+{
33392+ const uint32_t *shadow = cmd;
33393+ int loop;
33394+#ifdef QBMAN_CENA_TRACE
33395+ pr_info("qbman_cena_write_complete(%p:%d:0x%03x) %p\n",
33396+ s->addr_cena, s->idx, offset, shadow);
33397+ hexdump(cmd, 64);
33398+#endif
33399+ for (loop = 15; loop >= 1; loop--)
33400+ __raw_writel(shadow[loop], s->addr_cena +
33401+ offset + loop * 4);
33402+ lwsync();
33403+ __raw_writel(shadow[0], s->addr_cena + offset);
33404+ dcbf(s->addr_cena + offset);
33405+}
33406+
33407+static inline void qbman_cena_write_complete_wo_shadow(struct qbman_swp_sys *s,
33408+ uint32_t offset)
33409+{
33410+#ifdef QBMAN_CENA_TRACE
33411+ pr_info("qbman_cena_write_complete(%p:%d:0x%03x)\n",
33412+ s->addr_cena, s->idx, offset);
33413+ hexdump(cmd, 64);
33414+#endif
33415+ dcbf(s->addr_cena + offset);
33416+}
33417+
33418+static inline uint32_t qbman_cena_read_reg(struct qbman_swp_sys *s,
33419+ uint32_t offset)
33420+{
33421+ return __raw_readl(s->addr_cena + offset);
33422+}
33423+
33424+static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset)
33425+{
33426+ uint32_t *shadow = (uint32_t *)(s->cena + offset);
33427+ unsigned int loop;
33428+#ifdef QBMAN_CENA_TRACE
33429+ pr_info("qbman_cena_read(%p:%d:0x%03x) %p\n",
33430+ s->addr_cena, s->idx, offset, shadow);
33431+#endif
33432+
33433+ for (loop = 0; loop < 16; loop++)
33434+ shadow[loop] = __raw_readl(s->addr_cena + offset
33435+ + loop * 4);
33436+#ifdef QBMAN_CENA_TRACE
33437+ hexdump(shadow, 64);
33438+#endif
33439+ return shadow;
33440+}
33441+
33442+static inline void *qbman_cena_read_wo_shadow(struct qbman_swp_sys *s,
33443+ uint32_t offset)
33444+{
33445+#ifdef QBMAN_CENA_TRACE
33446+ pr_info("qbman_cena_read(%p:%d:0x%03x) %p\n",
33447+ s->addr_cena, s->idx, offset, shadow);
33448+#endif
33449+
33450+#ifdef QBMAN_CENA_TRACE
33451+ hexdump(shadow, 64);
33452+#endif
33453+ return s->addr_cena + offset;
33454+}
33455+
33456+static inline void qbman_cena_invalidate(struct qbman_swp_sys *s,
33457+ uint32_t offset)
33458+{
33459+ dccivac(s->addr_cena + offset);
33460+}
33461+
33462+static inline void qbman_cena_invalidate_prefetch(struct qbman_swp_sys *s,
33463+ uint32_t offset)
33464+{
33465+ dccivac(s->addr_cena + offset);
33466+ prefetch_for_load(s->addr_cena + offset);
33467+}
33468+
33469+static inline void qbman_cena_prefetch(struct qbman_swp_sys *s,
33470+ uint32_t offset)
33471+{
33472+ prefetch_for_load(s->addr_cena + offset);
33473+}
33474+
33475+ /******************/
33476+ /* Portal support */
33477+ /******************/
33478+
33479+/* The SWP_CFG portal register is special, in that it is used by the
33480+ * platform-specific code rather than the platform-independent code in
33481+ * qbman_portal.c. So use of it is declared locally here. */
33482+#define QBMAN_CINH_SWP_CFG 0xd00
33483+
33484+/* For MC portal use, we always configure with
33485+ * DQRR_MF is (SWP_CFG,20,3) - DQRR max fill (<- 0x4)
33486+ * EST is (SWP_CFG,16,3) - EQCR_CI stashing threshold (<- 0x2)
33487+ * RPM is (SWP_CFG,12,2) - RCR production notification mode (<- 0x3)
33488+ * DCM is (SWP_CFG,10,2) - DQRR consumption notification mode (<- 0x2)
33489+ * EPM is (SWP_CFG,8,2) - EQCR production notification mode (<- 0x2)
33490+ * SD is (SWP_CFG,5,1) - memory stashing drop enable (<- TRUE)
33491+ * SP is (SWP_CFG,4,1) - memory stashing priority (<- TRUE)
33492+ * SE is (SWP_CFG,3,1) - memory stashing enable (<- TRUE)
33493+ * DP is (SWP_CFG,2,1) - dequeue stashing priority (<- TRUE)
33494+ * DE is (SWP_CFG,1,1) - dequeue stashing enable (<- TRUE)
33495+ * EP is (SWP_CFG,0,1) - EQCR_CI stashing priority (<- TRUE)
33496+ */
33497+static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn,
33498+ uint8_t est, uint8_t rpm, uint8_t dcm,
33499+ uint8_t epm, int sd, int sp, int se,
33500+ int dp, int de, int ep)
33501+{
33502+ uint32_t reg;
33503+ reg = e32_uint8_t(20, (uint32_t)(3 + (max_fill >> 3)), max_fill) |
33504+ e32_uint8_t(16, 3, est) |
33505+ e32_uint8_t(12, 2, rpm) | e32_uint8_t(10, 2, dcm) |
33506+ e32_uint8_t(8, 2, epm) | e32_int(5, 1, sd) |
33507+ e32_int(4, 1, sp) | e32_int(3, 1, se) | e32_int(2, 1, dp) |
33508+ e32_int(1, 1, de) | e32_int(0, 1, ep) | e32_uint8_t(14, 1, wn);
33509+ return reg;
33510+}
33511+
33512+static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
33513+ const struct qbman_swp_desc *d,
33514+ uint8_t dqrr_size)
33515+{
33516+ uint32_t reg;
33517+ s->addr_cena = d->cena_bar;
33518+ s->addr_cinh = d->cinh_bar;
33519+ s->idx = (uint32_t)d->idx;
33520+ s->cena = (void *)get_zeroed_page(GFP_KERNEL);
33521+ if (!s->cena) {
33522+ pr_err("Could not allocate page for cena shadow\n");
33523+ return -1;
33524+ }
33525+ s->eqcr_mode = d->eqcr_mode;
33526+ BUG_ON(d->idx < 0);
33527+#ifdef QBMAN_CHECKING
33528+ /* We should never be asked to initialise for a portal that isn't in
33529+ * the power-on state. (Ie. don't forget to reset portals when they are
33530+ * decommissioned!)
33531+ */
33532+ reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
33533+ BUG_ON(reg);
33534+#endif
33535+ if (s->eqcr_mode == qman_eqcr_vb_array)
33536+ reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 1, 1, 1, 1,
33537+ 1, 1);
33538+ else
33539+ reg = qbman_set_swp_cfg(dqrr_size, 0, 2, 3, 2, 2, 1, 1, 1, 1,
33540+ 1, 1);
33541+ qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
33542+ reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
33543+ if (!reg) {
33544+ pr_err("The portal %d is not enabled!\n", s->idx);
33545+ kfree(s->cena);
33546+ return -1;
33547+ }
33548+ return 0;
33549+}
33550+
33551+static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s)
33552+{
33553+ free_page((unsigned long)s->cena);
33554+}
33555+
33556+static inline void *qbman_cena_write_start_wo_shadow_fast(struct qbman_swp_sys *s,
33557+ uint32_t offset)
33558+{
33559+ #ifdef QBMAN_CENA_TRACE
33560+ pr_info("qbman_cena_write_start(%p:%d:0x%03x)\n",
33561+ s->addr_cena, s->idx, offset);
33562+ #endif
33563+ BUG_ON(offset & 63);
33564+ return (s->addr_cena + offset);
33565+}
33566diff --git a/drivers/net/dpaa2/qbman/driver/qbman_sys_decl.h b/drivers/net/dpaa2/qbman/driver/qbman_sys_decl.h
33567new file mode 100644
33568index 0000000..ae7ef97
33569--- /dev/null
33570+++ b/drivers/net/dpaa2/qbman/driver/qbman_sys_decl.h
33571@@ -0,0 +1,68 @@
33572+/* Copyright (C) 2014 Freescale Semiconductor, Inc.
33573+ *
33574+ * Redistribution and use in source and binary forms, with or without
33575+ * modification, are permitted provided that the following conditions are met:
33576+ * * Redistributions of source code must retain the above copyright
33577+ * notice, this list of conditions and the following disclaimer.
33578+ * * Redistributions in binary form must reproduce the above copyright
33579+ * notice, this list of conditions and the following disclaimer in the
33580+ * documentation and/or other materials provided with the distribution.
33581+ * * Neither the name of Freescale Semiconductor nor the
33582+ * names of its contributors may be used to endorse or promote products
33583+ * derived from this software without specific prior written permission.
33584+ *
33585+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
33586+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33587+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33588+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
33589+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
33590+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33591+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
33592+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33593+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33594+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33595+ */
33596+#include <compat.h>
33597+#include <drivers/fsl_qbman_base.h>
33598+
33599+/* Sanity check */
33600+#if (__BYTE_ORDER__ != __ORDER_BIG_ENDIAN__) && \
33601+ (__BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__)
33602+#error "Unknown endianness!"
33603+#endif
33604+
33605+/* The platform-independent code shouldn't need endianness, except for
33606+ * weird/fast-path cases like qbman_result_has_token(), which needs to
33607+ * perform a passive and endianness-specific test on a read-only data structure
33608+ * very quickly. It's an exception, and this symbol is used for that case. */
33609+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
33610+#define DQRR_TOK_OFFSET 0
33611+#define QBMAN_RESULT_VERB_OFFSET_IN_MEM 24
33612+#define SCN_STATE_OFFSET_IN_MEM 8
33613+#define SCN_RID_OFFSET_IN_MEM 8
33614+#else
33615+#define DQRR_TOK_OFFSET 24
33616+#define QBMAN_RESULT_VERB_OFFSET_IN_MEM 0
33617+#define SCN_STATE_OFFSET_IN_MEM 16
33618+#define SCN_RID_OFFSET_IN_MEM 0
33619+#endif
33620+
33621+/* Similarly-named functions */
33622+#define upper32(a) upper_32_bits(a)
33623+#define lower32(a) lower_32_bits(a)
33624+
33625+ /****************/
33626+ /* arch assists */
33627+ /****************/
33628+#define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); }
33629+#define lwsync() { asm volatile("dmb st" : : : "memory"); }
33630+#define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
33631+#define dccivac(p) { asm volatile("dc civac, %0" : : "r"(p) : "memory"); }
33632+static inline void prefetch_for_load(void *p)
33633+{
33634+ asm volatile("prfm pldl1keep, [%0, #64]" : : "r" (p));
33635+}
33636+static inline void prefetch_for_store(void *p)
33637+{
33638+ asm volatile("prfm pstl1keep, [%0, #64]" : : "r" (p));
33639+}
33640diff --git a/drivers/net/dpaa2/qbman/include/compat.h b/drivers/net/dpaa2/qbman/include/compat.h
33641new file mode 100644
33642index 0000000..0d14b58
33643--- /dev/null
33644+++ b/drivers/net/dpaa2/qbman/include/compat.h
33645@@ -0,0 +1,597 @@
33646+/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
33647+ * All rights reserved.
33648+ *
33649+ * Redistribution and use in source and binary forms, with or without
33650+ * modification, are permitted provided that the following conditions are met:
33651+ * * Redistributions of source code must retain the above copyright
33652+ * notice, this list of conditions and the following disclaimer.
33653+ * * Redistributions in binary form must reproduce the above copyright
33654+ * notice, this list of conditions and the following disclaimer in the
33655+ * documentation and/or other materials provided with the distribution.
33656+ * * Neither the name of Freescale Semiconductor nor the
33657+ * names of its contributors may be used to endorse or promote products
33658+ * derived from this software without specific prior written permission.
33659+ *
33660+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
33661+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33662+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33663+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
33664+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
33665+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33666+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
33667+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33668+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33669+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33670+ */
33671+
33672+#ifndef HEADER_COMPAT_H
33673+#define HEADER_COMPAT_H
33674+
33675+#include <sched.h>
33676+
33677+#ifndef _GNU_SOURCE
33678+#define _GNU_SOURCE
33679+#endif
33680+#include <stdint.h>
33681+#include <stdlib.h>
33682+#include <stddef.h>
33683+#include <errno.h>
33684+#include <string.h>
33685+#include <pthread.h>
33686+#include <net/ethernet.h>
33687+#include <stdio.h>
33688+#include <stdbool.h>
33689+#include <ctype.h>
33690+#include <malloc.h>
33691+#include <sys/types.h>
33692+#include <sys/stat.h>
33693+#include <fcntl.h>
33694+#include <unistd.h>
33695+#include <sys/mman.h>
33696+#include <limits.h>
33697+#include <assert.h>
33698+#include <dirent.h>
33699+#include <inttypes.h>
33700+#include <error.h>
33701+
33702+/* The following definitions are primarily to allow the single-source driver
33703+ * interfaces to be included by arbitrary program code. Ie. for interfaces that
33704+ * are also available in kernel-space, these definitions provide compatibility
33705+ * with certain attributes and types used in those interfaces. */
33706+
33707+/* Required compiler attributes */
33708+#define __maybe_unused __attribute__((unused))
33709+#define __always_unused __attribute__((unused))
33710+#define __packed __attribute__((__packed__))
33711+#define __user
33712+#define likely(x) __builtin_expect(!!(x), 1)
33713+#define unlikely(x) __builtin_expect(!!(x), 0)
33714+#define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES)))
33715+#define container_of(p, t, f) (t *)((void *)p - offsetof(t, f))
33716+#define __stringify_1(x) #x
33717+#define __stringify(x) __stringify_1(x)
33718+#define panic(x) \
33719+do { \
33720+ printf("panic: %s", x); \
33721+ abort(); \
33722+} while (0)
33723+
33724+#ifdef ARRAY_SIZE
33725+#undef ARRAY_SIZE
33726+#endif
33727+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
33728+
33729+/* Required types */
33730+typedef uint8_t u8;
33731+typedef uint16_t u16;
33732+typedef uint32_t u32;
33733+typedef uint64_t u64;
33734+typedef uint64_t dma_addr_t;
33735+typedef cpu_set_t cpumask_t;
33736+#define spinlock_t pthread_mutex_t
33737+typedef u32 compat_uptr_t;
33738+static inline void __user *compat_ptr(compat_uptr_t uptr)
33739+{
33740+ return (void __user *)(unsigned long)uptr;
33741+}
33742+
33743+static inline compat_uptr_t ptr_to_compat(void __user *uptr)
33744+{
33745+ return (u32)(unsigned long)uptr;
33746+}
33747+
33748+/* I/O operations */
33749+static inline u32 in_be32(volatile void *__p)
33750+{
33751+ volatile u32 *p = __p;
33752+ return *p;
33753+}
33754+static inline void out_be32(volatile void *__p, u32 val)
33755+{
33756+ volatile u32 *p = __p;
33757+ *p = val;
33758+}
33759+
33760+/* Debugging */
33761+#define prflush(fmt, args...) \
33762+ do { \
33763+ printf(fmt, ##args); \
33764+ fflush(stdout); \
33765+ } while (0)
33766+#define pr_crit(fmt, args...) prflush("CRIT:" fmt, ##args)
33767+#define pr_err(fmt, args...) prflush("ERR:" fmt, ##args)
33768+#define pr_warning(fmt, args...) prflush("WARN:" fmt, ##args)
33769+#define pr_info(fmt, args...) prflush(fmt, ##args)
33770+
33771+#define BUG() abort()
33772+#ifdef CONFIG_BUGON
33773+#ifdef pr_debug
33774+#undef pr_debug
33775+#endif
33776+#define pr_debug(fmt, args...) printf(fmt, ##args)
33777+#define BUG_ON(c) \
33778+do { \
33779+ if (c) { \
33780+ pr_crit("BUG: %s:%d\n", __FILE__, __LINE__); \
33781+ abort(); \
33782+ } \
33783+} while(0)
33784+#define might_sleep_if(c) BUG_ON(c)
33785+#define msleep(x) \
33786+do { \
33787+ pr_crit("BUG: illegal call %s:%d\n", __FILE__, __LINE__); \
33788+ exit(EXIT_FAILURE); \
33789+} while(0)
33790+#else
33791+#ifdef pr_debug
33792+#undef pr_debug
33793+#endif
33794+#define pr_debug(fmt, args...) do { ; } while(0)
33795+#define BUG_ON(c) do { ; } while(0)
33796+#define might_sleep_if(c) do { ; } while(0)
33797+#define msleep(x) do { ; } while(0)
33798+#endif
33799+#define WARN_ON(c, str) \
33800+do { \
33801+ static int warned_##__LINE__; \
33802+ if ((c) && !warned_##__LINE__) { \
33803+ pr_warning("%s\n", str); \
33804+ pr_warning("(%s:%d)\n", __FILE__, __LINE__); \
33805+ warned_##__LINE__ = 1; \
33806+ } \
33807+} while (0)
33808+
33809+#define ALIGN(x, a) (((x) + ((typeof(x))(a) - 1)) & ~((typeof(x))(a) - 1))
33810+
33811+/****************/
33812+/* Linked-lists */
33813+/****************/
33814+
33815+struct list_head {
33816+ struct list_head *prev;
33817+ struct list_head *next;
33818+};
33819+
33820+#define LIST_HEAD(n) \
33821+struct list_head n = { \
33822+ .prev = &n, \
33823+ .next = &n \
33824+}
33825+#define INIT_LIST_HEAD(p) \
33826+do { \
33827+ struct list_head *__p298 = (p); \
33828+ __p298->prev = __p298->next =__p298; \
33829+} while(0)
33830+#define list_entry(node, type, member) \
33831+ (type *)((void *)node - offsetof(type, member))
33832+#define list_empty(p) \
33833+({ \
33834+ const struct list_head *__p298 = (p); \
33835+ ((__p298->next == __p298) && (__p298->prev == __p298)); \
33836+})
33837+#define list_add(p,l) \
33838+do { \
33839+ struct list_head *__p298 = (p); \
33840+ struct list_head *__l298 = (l); \
33841+ __p298->next = __l298->next; \
33842+ __p298->prev = __l298; \
33843+ __l298->next->prev = __p298; \
33844+ __l298->next = __p298; \
33845+} while(0)
33846+#define list_add_tail(p,l) \
33847+do { \
33848+ struct list_head *__p298 = (p); \
33849+ struct list_head *__l298 = (l); \
33850+ __p298->prev = __l298->prev; \
33851+ __p298->next = __l298; \
33852+ __l298->prev->next = __p298; \
33853+ __l298->prev = __p298; \
33854+} while(0)
33855+#define list_for_each(i, l) \
33856+ for (i = (l)->next; i != (l); i = i->next)
33857+#define list_for_each_safe(i, j, l) \
33858+ for (i = (l)->next, j = i->next; i != (l); \
33859+ i = j, j = i->next)
33860+#define list_for_each_entry(i, l, name) \
33861+ for (i = list_entry((l)->next, typeof(*i), name); &i->name != (l); \
33862+ i = list_entry(i->name.next, typeof(*i), name))
33863+#define list_for_each_entry_safe(i, j, l, name) \
33864+ for (i = list_entry((l)->next, typeof(*i), name), \
33865+ j = list_entry(i->name.next, typeof(*j), name); \
33866+ &i->name != (l); \
33867+ i = j, j = list_entry(j->name.next, typeof(*j), name))
33868+#define list_del(i) \
33869+do { \
33870+ (i)->next->prev = (i)->prev; \
33871+ (i)->prev->next = (i)->next; \
33872+} while(0)
33873+
33874+/* Other miscellaneous interfaces our APIs depend on; */
33875+
33876+#define lower_32_bits(x) ((u32)(x))
33877+#define upper_32_bits(x) ((u32)(((x) >> 16) >> 16))
33878+
33879+/* Compiler/type stuff */
33880+typedef unsigned int gfp_t;
33881+typedef uint32_t phandle;
33882+
33883+#define noinline __attribute__((noinline))
33884+#define __iomem
33885+#define EINTR 4
33886+#define ENODEV 19
33887+#define MODULE_AUTHOR(s)
33888+#define MODULE_LICENSE(s)
33889+#define MODULE_DESCRIPTION(s)
33890+#define MODULE_PARM_DESC(x, y)
33891+#define EXPORT_SYMBOL(x)
33892+#define module_init(fn) int m_##fn(void) { return fn(); }
33893+#define module_exit(fn) void m_##fn(void) { fn(); }
33894+#define module_param(x, y, z)
33895+#define module_param_string(w, x, y, z)
33896+#define GFP_KERNEL 0
33897+#define __KERNEL__
33898+#define __init
33899+#define __raw_readb(p) *(const volatile unsigned char *)(p)
33900+#define __raw_readl(p) *(const volatile unsigned int *)(p)
33901+#define __raw_writel(v, p) \
33902+do { \
33903+ *(volatile unsigned int *)(p) = (v); \
33904+} while (0)
33905+
33906+/* printk() stuff */
33907+#define printk(fmt, args...) do_not_use_printk
33908+#define nada(fmt, args...) do { ; } while(0)
33909+
33910+/* Interrupt stuff */
33911+typedef uint32_t irqreturn_t;
33912+#define IRQ_HANDLED 0
33913+
33914+/* memcpy() stuff - when you know alignments in advance */
33915+#ifdef CONFIG_TRY_BETTER_MEMCPY
33916+static inline void copy_words(void *dest, const void *src, size_t sz)
33917+{
33918+ u32 *__dest = dest;
33919+ const u32 *__src = src;
33920+ size_t __sz = sz >> 2;
33921+ BUG_ON((unsigned long)dest & 0x3);
33922+ BUG_ON((unsigned long)src & 0x3);
33923+ BUG_ON(sz & 0x3);
33924+ while (__sz--)
33925+ *(__dest++) = *(__src++);
33926+}
33927+static inline void copy_shorts(void *dest, const void *src, size_t sz)
33928+{
33929+ u16 *__dest = dest;
33930+ const u16 *__src = src;
33931+ size_t __sz = sz >> 1;
33932+ BUG_ON((unsigned long)dest & 0x1);
33933+ BUG_ON((unsigned long)src & 0x1);
33934+ BUG_ON(sz & 0x1);
33935+ while (__sz--)
33936+ *(__dest++) = *(__src++);
33937+}
33938+static inline void copy_bytes(void *dest, const void *src, size_t sz)
33939+{
33940+ u8 *__dest = dest;
33941+ const u8 *__src = src;
33942+ while (sz--)
33943+ *(__dest++) = *(__src++);
33944+}
33945+#else
33946+#define copy_words memcpy
33947+#define copy_shorts memcpy
33948+#define copy_bytes memcpy
33949+#endif
33950+
33951+/* Spinlock stuff */
33952+#define spinlock_t pthread_mutex_t
33953+#define __SPIN_LOCK_UNLOCKED(x) PTHREAD_ADAPTIVE_MUTEX_INITIALIZER_NP
33954+#define DEFINE_SPINLOCK(x) spinlock_t x = __SPIN_LOCK_UNLOCKED(x)
33955+#define spin_lock_init(x) \
33956+ do { \
33957+ __maybe_unused int __foo; \
33958+ pthread_mutexattr_t __foo_attr; \
33959+ __foo = pthread_mutexattr_init(&__foo_attr); \
33960+ BUG_ON(__foo); \
33961+ __foo = pthread_mutexattr_settype(&__foo_attr, \
33962+ PTHREAD_MUTEX_ADAPTIVE_NP); \
33963+ BUG_ON(__foo); \
33964+ __foo = pthread_mutex_init(x, &__foo_attr); \
33965+ BUG_ON(__foo); \
33966+ } while (0)
33967+#define spin_lock(x) \
33968+ do { \
33969+ __maybe_unused int __foo = pthread_mutex_lock(x); \
33970+ BUG_ON(__foo); \
33971+ } while (0)
33972+#define spin_unlock(x) \
33973+ do { \
33974+ __maybe_unused int __foo = pthread_mutex_unlock(x); \
33975+ BUG_ON(__foo); \
33976+ } while (0)
33977+#define spin_lock_irq(x) do { \
33978+ local_irq_disable(); \
33979+ spin_lock(x); \
33980+ } while (0)
33981+#define spin_unlock_irq(x) do { \
33982+ spin_unlock(x); \
33983+ local_irq_enable(); \
33984+ } while (0)
33985+#define spin_lock_irqsave(x, f) do { spin_lock_irq(x); } while (0)
33986+#define spin_unlock_irqrestore(x, f) do { spin_unlock_irq(x); } while (0)
33987+
33988+#define raw_spinlock_t spinlock_t
33989+#define raw_spin_lock_init(x) spin_lock_init(x)
33990+#define raw_spin_lock_irqsave(x, f) spin_lock(x)
33991+#define raw_spin_unlock_irqrestore(x, f) spin_unlock(x)
33992+
33993+/* Completion stuff */
33994+#define DECLARE_COMPLETION(n) int n = 0;
33995+#define complete(n) \
33996+do { \
33997+ *n = 1; \
33998+} while(0)
33999+#define wait_for_completion(n) \
34000+do { \
34001+ while (!*n) { \
34002+ bman_poll(); \
34003+ qman_poll(); \
34004+ } \
34005+ *n = 0; \
34006+} while(0)
34007+
34008+/* Platform device stuff */
34009+struct platform_device { void *dev; };
34010+static inline struct
34011+platform_device *platform_device_alloc(const char *name __always_unused,
34012+ int id __always_unused)
34013+{
34014+ struct platform_device *ret = malloc(sizeof(*ret));
34015+ if (ret)
34016+ ret->dev = NULL;
34017+ return ret;
34018+}
34019+#define platform_device_add(pdev) 0
34020+#define platform_device_del(pdev) do { ; } while(0)
34021+static inline void platform_device_put(struct platform_device *pdev)
34022+{
34023+ free(pdev);
34024+}
34025+struct resource {
34026+ int unused;
34027+};
34028+
34029+/* Allocator stuff */
34030+#define kmalloc(sz, t) malloc(sz)
34031+#define vmalloc(sz) malloc(sz)
34032+#define kfree(p) do { if (p) free(p); } while (0)
34033+static inline void *kzalloc(size_t sz, gfp_t __foo __always_unused)
34034+{
34035+ void *ptr = malloc(sz);
34036+ if (ptr)
34037+ memset(ptr, 0, sz);
34038+ return ptr;
34039+}
34040+static inline unsigned long get_zeroed_page(gfp_t __foo __always_unused)
34041+{
34042+ void *p;
34043+ if (posix_memalign(&p, 4096, 4096))
34044+ return 0;
34045+ memset(p, 0, 4096);
34046+ return (unsigned long)p;
34047+}
34048+static inline void free_page(unsigned long p)
34049+{
34050+ free((void *)p);
34051+}
34052+struct kmem_cache {
34053+ size_t sz;
34054+ size_t align;
34055+};
34056+#define SLAB_HWCACHE_ALIGN 0
34057+static inline struct kmem_cache *kmem_cache_create(const char *n __always_unused,
34058+ size_t sz, size_t align, unsigned long flags __always_unused,
34059+ void (*c)(void *) __always_unused)
34060+{
34061+ struct kmem_cache *ret = malloc(sizeof(*ret));
34062+ if (ret) {
34063+ ret->sz = sz;
34064+ ret->align = align;
34065+ }
34066+ return ret;
34067+}
34068+static inline void kmem_cache_destroy(struct kmem_cache *c)
34069+{
34070+ free(c);
34071+}
34072+static inline void *kmem_cache_alloc(struct kmem_cache *c, gfp_t f __always_unused)
34073+{
34074+ void *p;
34075+ if (posix_memalign(&p, c->align, c->sz))
34076+ return NULL;
34077+ return p;
34078+}
34079+static inline void kmem_cache_free(struct kmem_cache *c __always_unused, void *p)
34080+{
34081+ free(p);
34082+}
34083+static inline void *kmem_cache_zalloc(struct kmem_cache *c, gfp_t f)
34084+{
34085+ void *ret = kmem_cache_alloc(c, f);
34086+ if (ret)
34087+ memset(ret, 0, c->sz);
34088+ return ret;
34089+}
34090+
34091+/* Bitfield stuff. */
34092+#define BITS_PER_ULONG (sizeof(unsigned long) << 3)
34093+#define SHIFT_PER_ULONG (((1 << 5) == BITS_PER_ULONG) ? 5 : 6)
34094+#define BITS_MASK(idx) ((unsigned long)1 << ((idx) & (BITS_PER_ULONG - 1)))
34095+#define BITS_IDX(idx) ((idx) >> SHIFT_PER_ULONG)
34096+static inline unsigned long test_bits(unsigned long mask,
34097+ volatile unsigned long *p)
34098+{
34099+ return *p & mask;
34100+}
34101+static inline int test_bit(int idx, volatile unsigned long *bits)
34102+{
34103+ return test_bits(BITS_MASK(idx), bits + BITS_IDX(idx));
34104+}
34105+static inline void set_bits(unsigned long mask, volatile unsigned long *p)
34106+{
34107+ *p |= mask;
34108+}
34109+static inline void set_bit(int idx, volatile unsigned long *bits)
34110+{
34111+ set_bits(BITS_MASK(idx), bits + BITS_IDX(idx));
34112+}
34113+static inline void clear_bits(unsigned long mask, volatile unsigned long *p)
34114+{
34115+ *p &= ~mask;
34116+}
34117+static inline void clear_bit(int idx, volatile unsigned long *bits)
34118+{
34119+ clear_bits(BITS_MASK(idx), bits + BITS_IDX(idx));
34120+}
34121+static inline unsigned long test_and_set_bits(unsigned long mask,
34122+ volatile unsigned long *p)
34123+{
34124+ unsigned long ret = test_bits(mask, p);
34125+ set_bits(mask, p);
34126+ return ret;
34127+}
34128+static inline int test_and_set_bit(int idx, volatile unsigned long *bits)
34129+{
34130+ int ret = test_bit(idx, bits);
34131+ set_bit(idx, bits);
34132+ return ret;
34133+}
34134+static inline int test_and_clear_bit(int idx, volatile unsigned long *bits)
34135+{
34136+ int ret = test_bit(idx, bits);
34137+ clear_bit(idx, bits);
34138+ return ret;
34139+}
34140+static inline int find_next_zero_bit(unsigned long *bits, int limit, int idx)
34141+{
34142+ while ((++idx < limit) && test_bit(idx, bits))
34143+ ;
34144+ return idx;
34145+}
34146+static inline int find_first_zero_bit(unsigned long *bits, int limit)
34147+{
34148+ int idx = 0;
34149+ while (test_bit(idx, bits) && (++idx < limit))
34150+ ;
34151+ return idx;
34152+}
34153+
34154+static inline u64 div64_u64(u64 n, u64 d)
34155+{
34156+ return n / d;
34157+}
34158+
34159+#define dmb(opt) { asm volatile("dmb " #opt : : : "memory"); }
34160+#define smp_mb() dmb(ish)
34161+
34162+/* Atomic stuff */
34163+typedef struct {
34164+ int counter;
34165+} atomic_t;
34166+
34167+#define atomic_read(v) (*(volatile int *)&(v)->counter)
34168+#define atomic_set(v, i) (((v)->counter) = (i))
34169+static inline void atomic_add(int i, atomic_t *v)
34170+{
34171+ unsigned long tmp;
34172+ int result;
34173+
34174+ asm volatile("// atomic_add\n"
34175+ "1: ldxr %w0, %2\n"
34176+ " add %w0, %w0, %w3\n"
34177+ " stxr %w1, %w0, %2\n"
34178+ " cbnz %w1, 1b"
34179+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
34180+ : "Ir" (i));
34181+}
34182+
34183+static inline int atomic_add_return(int i, atomic_t *v)
34184+{
34185+ unsigned long tmp;
34186+ int result;
34187+
34188+ asm volatile("// atomic_add_return\n"
34189+ "1: ldxr %w0, %2\n"
34190+ " add %w0, %w0, %w3\n"
34191+ " stlxr %w1, %w0, %2\n"
34192+ " cbnz %w1, 1b"
34193+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
34194+ : "Ir" (i)
34195+ : "memory");
34196+
34197+ smp_mb();
34198+ return result;
34199+}
34200+
34201+static inline void atomic_sub(int i, atomic_t *v)
34202+{
34203+ unsigned long tmp;
34204+ int result;
34205+
34206+ asm volatile("// atomic_sub\n"
34207+ "1: ldxr %w0, %2\n"
34208+ " sub %w0, %w0, %w3\n"
34209+ " stxr %w1, %w0, %2\n"
34210+ " cbnz %w1, 1b"
34211+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
34212+ : "Ir" (i));
34213+}
34214+
34215+static inline int atomic_sub_return(int i, atomic_t *v)
34216+{
34217+ unsigned long tmp;
34218+ int result;
34219+
34220+ asm volatile("// atomic_sub_return\n"
34221+ "1: ldxr %w0, %2\n"
34222+ " sub %w0, %w0, %w3\n"
34223+ " stlxr %w1, %w0, %2\n"
34224+ " cbnz %w1, 1b"
34225+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
34226+ : "Ir" (i)
34227+ : "memory");
34228+
34229+ smp_mb();
34230+ return result;
34231+}
34232+
34233+#define atomic_inc(v) atomic_add(1, v)
34234+#define atomic_dec(v) atomic_sub(1, v)
34235+
34236+#define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
34237+#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
34238+#define atomic_inc_return(v) (atomic_add_return(1, v))
34239+#define atomic_dec_return(v) (atomic_sub_return(1, v))
34240+#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
34241+
34242+#endif /* HEADER_COMPAT_H */
34243diff --git a/drivers/net/dpaa2/qbman/include/drivers/fsl_qbman_base.h b/drivers/net/dpaa2/qbman/include/drivers/fsl_qbman_base.h
34244new file mode 100644
34245index 0000000..4cb784c
34246--- /dev/null
34247+++ b/drivers/net/dpaa2/qbman/include/drivers/fsl_qbman_base.h
34248@@ -0,0 +1,151 @@
34249+/* Copyright (C) 2014 Freescale Semiconductor, Inc.
34250+ *
34251+ * Redistribution and use in source and binary forms, with or without
34252+ * modification, are permitted provided that the following conditions are met:
34253+ * * Redistributions of source code must retain the above copyright
34254+ * notice, this list of conditions and the following disclaimer.
34255+ * * Redistributions in binary form must reproduce the above copyright
34256+ * notice, this list of conditions and the following disclaimer in the
34257+ * documentation and/or other materials provided with the distribution.
34258+ * * Neither the name of Freescale Semiconductor nor the
34259+ * names of its contributors may be used to endorse or promote products
34260+ * derived from this software without specific prior written permission.
34261+ *
34262+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
34263+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34264+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34265+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
34266+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34267+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34268+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
34269+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34270+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34271+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34272+ */
34273+#ifndef _FSL_QBMAN_BASE_H
34274+#define _FSL_QBMAN_BASE_H
34275+
34276+/**
34277+ * DOC: QBMan basic structures
34278+ *
34279+ * The QBMan block descriptor, software portal descriptor and Frame descriptor
34280+ * are defined here.
34281+ *
34282+ */
34283+
34284+/**
34285+ * struct qbman_block_desc - qbman block descriptor structure
34286+ * @ccsr_reg_bar: CCSR register map.
34287+ * @irq_rerr: Recoverable error interrupt line.
34288+ * @irq_nrerr: Non-recoverable error interrupt line
34289+ *
34290+ * Descriptor for a QBMan instance on the SoC. On partitions/targets that do not
34291+ * control this QBMan instance, these values may simply be place-holders. The
34292+ * idea is simply that we be able to distinguish between them, eg. so that SWP
34293+ * descriptors can identify which QBMan instance they belong to.
34294+ */
34295+struct qbman_block_desc {
34296+ void *ccsr_reg_bar;
34297+ int irq_rerr;
34298+ int irq_nrerr;
34299+};
34300+
34301+enum qbman_eqcr_mode {
34302+ qman_eqcr_vb_ring = 2, /* Valid bit, with eqcr in ring mode */
34303+ qman_eqcr_vb_array, /* Valid bit, with eqcr in array mode */
34304+};
34305+
34306+/**
34307+ * struct qbman_swp_desc - qbman software portal descriptor structure
34308+ * @block: The QBMan instance.
34309+ * @cena_bar: Cache-enabled portal register map.
34310+ * @cinh_bar: Cache-inhibited portal register map.
34311+ * @irq: -1 if unused (or unassigned)
34312+ * @idx: SWPs within a QBMan are indexed. -1 if opaque to the user.
34313+ * @qman_version: the qman version.
34314+ * @eqcr_mode: Select the eqcr mode, currently only valid bit ring mode and
34315+ * valid bit array mode are supported.
34316+ *
34317+ * Descriptor for a QBMan software portal, expressed in terms that make sense to
34318+ * the user context. Ie. on MC, this information is likely to be true-physical,
34319+ * and instantiated statically at compile-time. On GPP, this information is
34320+ * likely to be obtained via "discovery" over a partition's "MC bus"
34321+ * (ie. in response to a MC portal command), and would take into account any
34322+ * virtualisation of the GPP user's address space and/or interrupt numbering.
34323+ */
34324+struct qbman_swp_desc {
34325+ const struct qbman_block_desc *block;
34326+ uint8_t *cena_bar;
34327+ uint8_t *cinh_bar;
34328+ int irq;
34329+ int idx;
34330+ uint32_t qman_version;
34331+ enum qbman_eqcr_mode eqcr_mode;
34332+};
34333+
34334+/* Driver object for managing a QBMan portal */
34335+struct qbman_swp;
34336+
34337+/**
34338+ * struct qbman_fd - basci structure for qbman frame descriptor
34339+ * @words: for easier/faster copying the whole FD structure.
34340+ * @addr_lo: the lower 32 bits of the address in FD.
34341+ * @addr_hi: the upper 32 bits of the address in FD.
34342+ * @len: the length field in FD.
34343+ * @bpid_offset: represent the bpid and offset fields in FD. offset in
34344+ * the MS 16 bits, BPID in the LS 16 bits.
34345+ * @frc: frame context
34346+ * @ctrl: the 32bit control bits including dd, sc,... va, err.
34347+ * @flc_lo: the lower 32bit of flow context.
34348+ * @flc_hi: the upper 32bits of flow context.
34349+ *
34350+ * Place-holder for FDs, we represent it via the simplest form that we need for
34351+ * now. Different overlays may be needed to support different options, etc. (It
34352+ * is impractical to define One True Struct, because the resulting encoding
34353+ * routines (lots of read-modify-writes) would be worst-case performance whether
34354+ * or not circumstances required them.)
34355+ *
34356+ * Note, as with all data-structures exchanged between software and hardware (be
34357+ * they located in the portal register map or DMA'd to and from main-memory),
34358+ * the driver ensures that the caller of the driver API sees the data-structures
34359+ * in host-endianness. "struct qbman_fd" is no exception. The 32-bit words
34360+ * contained within this structure are represented in host-endianness, even if
34361+ * hardware always treats them as little-endian. As such, if any of these fields
34362+ * are interpreted in a binary (rather than numerical) fashion by hardware
34363+ * blocks (eg. accelerators), then the user should be careful. We illustrate
34364+ * with an example;
34365+ *
34366+ * Suppose the desired behaviour of an accelerator is controlled by the "frc"
34367+ * field of the FDs that are sent to it. Suppose also that the behaviour desired
34368+ * by the user corresponds to an "frc" value which is expressed as the literal
34369+ * sequence of bytes 0xfe, 0xed, 0xab, and 0xba. So "frc" should be the 32-bit
34370+ * value in which 0xfe is the first byte and 0xba is the last byte, and as
34371+ * hardware is little-endian, this amounts to a 32-bit "value" of 0xbaabedfe. If
34372+ * the software is little-endian also, this can simply be achieved by setting
34373+ * frc=0xbaabedfe. On the other hand, if software is big-endian, it should set
34374+ * frc=0xfeedabba! The best away of avoiding trouble with this sort of thing is
34375+ * to treat the 32-bit words as numerical values, in which the offset of a field
34376+ * from the beginning of the first byte (as required or generated by hardware)
34377+ * is numerically encoded by a left-shift (ie. by raising the field to a
34378+ * corresponding power of 2). Ie. in the current example, software could set
34379+ * "frc" in the following way, and it would work correctly on both little-endian
34380+ * and big-endian operation;
34381+ * fd.frc = (0xfe << 0) | (0xed << 8) | (0xab << 16) | (0xba << 24);
34382+ */
34383+struct qbman_fd {
34384+ union {
34385+ uint32_t words[8];
34386+ struct qbman_fd_simple {
34387+ uint32_t addr_lo;
34388+ uint32_t addr_hi;
34389+ uint32_t len;
34390+ uint32_t bpid_offset;
34391+ uint32_t frc;
34392+ uint32_t ctrl;
34393+ uint32_t flc_lo;
34394+ uint32_t flc_hi;
34395+ } simple;
34396+ };
34397+};
34398+
34399+#endif /* !_FSL_QBMAN_BASE_H */
34400diff --git a/drivers/net/dpaa2/qbman/include/drivers/fsl_qbman_portal.h b/drivers/net/dpaa2/qbman/include/drivers/fsl_qbman_portal.h
34401new file mode 100644
34402index 0000000..ddcabcf
34403--- /dev/null
34404+++ b/drivers/net/dpaa2/qbman/include/drivers/fsl_qbman_portal.h
34405@@ -0,0 +1,1089 @@
34406+/* Copyright (C) 2014 Freescale Semiconductor, Inc.
34407+ *
34408+ * Redistribution and use in source and binary forms, with or without
34409+ * modification, are permitted provided that the following conditions are met:
34410+ * * Redistributions of source code must retain the above copyright
34411+ * notice, this list of conditions and the following disclaimer.
34412+ * * Redistributions in binary form must reproduce the above copyright
34413+ * notice, this list of conditions and the following disclaimer in the
34414+ * documentation and/or other materials provided with the distribution.
34415+ * * Neither the name of Freescale Semiconductor nor the
34416+ * names of its contributors may be used to endorse or promote products
34417+ * derived from this software without specific prior written permission.
34418+ *
34419+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
34420+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34421+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34422+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
34423+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34424+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34425+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
34426+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34427+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34428+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34429+ */
34430+#ifndef _FSL_QBMAN_PORTAL_H
34431+#define _FSL_QBMAN_PORTAL_H
34432+
34433+#include <drivers/fsl_qbman_base.h>
34434+
34435+/**
34436+ * DOC - QBMan portal APIs to implement the following functions:
34437+ * - Initialize and destroy Software portal object.
34438+ * - Read and write Software portal interrupt registers.
34439+ * - Enqueue, including setting the enqueue descriptor, and issuing enqueue
34440+ * command etc.
34441+ * - Dequeue, including setting the dequeue descriptor, issuing dequeue command,
34442+ * parsing the dequeue response in DQRR and memeory, parsing the state change
34443+ * notifications etc.
34444+ * - Release, including setting the release descriptor, and issuing the buffer
34445+ * release command.
34446+ * - Acquire, acquire the buffer from the given buffer pool.
34447+ * - FQ management.
34448+ * - Channel management, enable/disable CDAN with or without context.
34449+ */
34450+
34451+/**
34452+ * qbman_swp_init() - Create a functional object representing the given
34453+ * QBMan portal descriptor.
34454+ * @d: the given qbman swp descriptor
34455+ *
34456+ * Return qbman_swp portal object for success, NULL if the object cannot
34457+ * be created.
34458+ */
34459+struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d);
34460+
34461+/**
34462+ * qbman_swp_finish() - Create and destroy a functional object representing
34463+ * the given QBMan portal descriptor.
34464+ * @p: the qbman_swp object to be destroyed.
34465+ *
34466+ */
34467+void qbman_swp_finish(struct qbman_swp *p);
34468+
34469+/**
34470+ * qbman_swp_get_desc() - Get the descriptor of the given portal object.
34471+ * @p: the given portal object.
34472+ *
34473+ * Return the descriptor for this portal.
34474+ */
34475+const struct qbman_swp_desc *qbman_swp_get_desc(struct qbman_swp *);
34476+
34477+ /**************/
34478+ /* Interrupts */
34479+ /**************/
34480+
34481+/* EQCR ring interrupt */
34482+#define QBMAN_SWP_INTERRUPT_EQRI ((uint32_t)0x00000001)
34483+/* Enqueue command dispatched interrupt */
34484+#define QBMAN_SWP_INTERRUPT_EQDI ((uint32_t)0x00000002)
34485+/* DQRR non-empty interrupt */
34486+#define QBMAN_SWP_INTERRUPT_DQRI ((uint32_t)0x00000004)
34487+/* RCR ring interrupt */
34488+#define QBMAN_SWP_INTERRUPT_RCRI ((uint32_t)0x00000008)
34489+/* Release command dispatched interrupt */
34490+#define QBMAN_SWP_INTERRUPT_RCDI ((uint32_t)0x00000010)
34491+/* Volatile dequeue command interrupt */
34492+#define QBMAN_SWP_INTERRUPT_VDCI ((uint32_t)0x00000020)
34493+
34494+/**
34495+ * qbman_swp_interrupt_get_vanish() - Get the data in software portal
34496+ * interrupt status disable register.
34497+ * @p: the given software portal object.
34498+ *
34499+ * Return the settings in SWP_ISDR register.
34500+ */
34501+uint32_t qbman_swp_interrupt_get_vanish(struct qbman_swp *p);
34502+
34503+/**
34504+ * qbman_swp_interrupt_set_vanish() - Set the data in software portal
34505+ * interrupt status disable register.
34506+ * @p: the given software portal object.
34507+ * @mask: The value to set in SWP_IDSR register.
34508+ */
34509+void qbman_swp_interrupt_set_vanish(struct qbman_swp *p, uint32_t mask);
34510+
34511+/**
34512+ * qbman_swp_interrupt_read_status() - Get the data in software portal
34513+ * interrupt status register.
34514+ * @p: the given software portal object.
34515+ *
34516+ * Return the settings in SWP_ISR register.
34517+ */
34518+uint32_t qbman_swp_interrupt_read_status(struct qbman_swp *p);
34519+
34520+/**
34521+ * qbman_swp_interrupt_clear_status() - Set the data in software portal
34522+ * interrupt status register.
34523+ * @p: the given software portal object.
34524+ * @mask: The value to set in SWP_ISR register.
34525+ */
34526+void qbman_swp_interrupt_clear_status(struct qbman_swp *p, uint32_t mask);
34527+
34528+/**
34529+ * qbman_swp_interrupt_get_trigger() - Get the data in software portal
34530+ * interrupt enable register.
34531+ * @p: the given software portal object.
34532+ *
34533+ * Return the settings in SWP_IER register.
34534+ */
34535+uint32_t qbman_swp_interrupt_get_trigger(struct qbman_swp *p);
34536+
34537+/**
34538+ * qbman_swp_interrupt_set_trigger() - Set the data in software portal
34539+ * interrupt enable register.
34540+ * @p: the given software portal object.
34541+ * @mask: The value to set in SWP_IER register.
34542+ */
34543+void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, uint32_t mask);
34544+
34545+/**
34546+ * qbman_swp_interrupt_get_inhibit() - Get the data in software portal
34547+ * interrupt inhibit register.
34548+ * @p: the given software portal object.
34549+ *
34550+ * Return the settings in SWP_IIR register.
34551+ */
34552+int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p);
34553+
34554+/**
34555+ * qbman_swp_interrupt_set_inhibit() - Set the data in software portal
34556+ * interrupt inhibit register.
34557+ * @p: the given software portal object.
34558+ * @mask: The value to set in SWP_IIR register.
34559+ */
34560+void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit);
34561+
34562+ /************/
34563+ /* Dequeues */
34564+ /************/
34565+
34566+/**
34567+ * struct qbman_result - structure for qbman dequeue response and/or
34568+ * notification.
34569+ * @dont_manipulate_directly: the 16 32bit data to represent the whole
34570+ * possible qbman dequeue result.
34571+ */
34572+struct qbman_result {
34573+ uint32_t dont_manipulate_directly[16];
34574+};
34575+
34576+/* TODO:
34577+ *A DQRI interrupt can be generated when there are dequeue results on the
34578+ * portal's DQRR (this mechanism does not deal with "pull" dequeues to
34579+ * user-supplied 'storage' addresses). There are two parameters to this
34580+ * interrupt source, one is a threshold and the other is a timeout. The
34581+ * interrupt will fire if either the fill-level of the ring exceeds 'thresh', or
34582+ * if the ring has been non-empty for been longer than 'timeout' nanoseconds.
34583+ * For timeout, an approximation to the desired nanosecond-granularity value is
34584+ * made, so there are get and set APIs to allow the user to see what actual
34585+ * timeout is set (compared to the timeout that was requested). */
34586+int qbman_swp_dequeue_thresh(struct qbman_swp *s, unsigned int thresh);
34587+int qbman_swp_dequeue_set_timeout(struct qbman_swp *s, unsigned int timeout);
34588+int qbman_swp_dequeue_get_timeout(struct qbman_swp *s, unsigned int *timeout);
34589+
34590+
34591+/* ------------------- */
34592+/* Push-mode dequeuing */
34593+/* ------------------- */
34594+
34595+/* The user of a portal can enable and disable push-mode dequeuing of up to 16
34596+ * channels independently. It does not specify this toggling by channel IDs, but
34597+ * rather by specifing the index (from 0 to 15) that has been mapped to the
34598+ * desired channel.
34599+ */
34600+
34601+/**
34602+ * qbman_swp_push_get() - Get the push dequeue setup.
34603+ * @s: the software portal object.
34604+ * @channel_idx: the channel index to query.
34605+ * @enabled: returned boolean to show whether the push dequeue is enabled for
34606+ * the given channel.
34607+ */
34608+void qbman_swp_push_get(struct qbman_swp *s, uint8_t channel_idx, int *enabled);
34609+
34610+/**
34611+ * qbman_swp_push_set() - Enable or disable push dequeue.
34612+ * @s: the software portal object.
34613+ * @channel_idx: the channel index..
34614+ * @enable: enable or disable push dequeue.
34615+ *
34616+ * The user of a portal can enable and disable push-mode dequeuing of up to 16
34617+ * channels independently. It does not specify this toggling by channel IDs, but
34618+ * rather by specifying the index (from 0 to 15) that has been mapped to the
34619+ * desired channel.
34620+ */
34621+void qbman_swp_push_set(struct qbman_swp *s, uint8_t channel_idx, int enable);
34622+
34623+/* ------------------- */
34624+/* Pull-mode dequeuing */
34625+/* ------------------- */
34626+
34627+/**
34628+ * struct qbman_pull_desc - the structure for pull dequeue descriptor
34629+ * @dont_manipulate_directly: the 6 32bit data to represent the whole
34630+ * possible settings for pull dequeue descriptor.
34631+ */
34632+struct qbman_pull_desc {
34633+ uint32_t dont_manipulate_directly[6];
34634+};
34635+
34636+enum qbman_pull_type_e {
34637+ /* dequeue with priority precedence, respect intra-class scheduling */
34638+ qbman_pull_type_prio = 1,
34639+ /* dequeue with active FQ precedence, respect ICS */
34640+ qbman_pull_type_active,
34641+ /* dequeue with active FQ precedence, no ICS */
34642+ qbman_pull_type_active_noics
34643+};
34644+
34645+/**
34646+ * qbman_pull_desc_clear() - Clear the contents of a descriptor to
34647+ * default/starting state.
34648+ * @d: the pull dequeue descriptor to be cleared.
34649+ */
34650+void qbman_pull_desc_clear(struct qbman_pull_desc *d);
34651+
34652+/**
34653+ * qbman_pull_desc_set_storage()- Set the pull dequeue storage
34654+ * @d: the pull dequeue descriptor to be set.
34655+ * @storage: the pointer of the memory to store the dequeue result.
34656+ * @storage_phys: the physical address of the storage memory.
34657+ * @stash: to indicate whether write allocate is enabled.
34658+ *
34659+ * If not called, or if called with 'storage' as NULL, the result pull dequeues
34660+ * will produce results to DQRR. If 'storage' is non-NULL, then results are
34661+ * produced to the given memory location (using the physical/DMA address which
34662+ * the caller provides in 'storage_phys'), and 'stash' controls whether or not
34663+ * those writes to main-memory express a cache-warming attribute.
34664+ */
34665+void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
34666+ struct qbman_result *storage,
34667+ dma_addr_t storage_phys,
34668+ int stash);
34669+/**
34670+ * qbman_pull_desc_set_numframes() - Set the number of frames to be dequeued.
34671+ * @d: the pull dequeue descriptor to be set.
34672+ * @numframes: number of frames to be set, must be between 1 and 16, inclusive.
34673+ */
34674+void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d,
34675+ uint8_t numframes);
34676+/**
34677+ * qbman_pull_desc_set_token() - Set dequeue token for pull command
34678+ * @d: the dequeue descriptor
34679+ * @token: the token to be set
34680+ *
34681+ * token is the value that shows up in the dequeue response that can be used to
34682+ * detect when the results have been published. The easiest technique is to zero
34683+ * result "storage" before issuing a dequeue, and use any non-zero 'token' value
34684+ */
34685+void qbman_pull_desc_set_token(struct qbman_pull_desc *d, uint8_t token);
34686+
34687+/* Exactly one of the following descriptor "actions" should be set. (Calling any
34688+ * one of these will replace the effect of any prior call to one of these.)
34689+ * - pull dequeue from the given frame queue (FQ)
34690+ * - pull dequeue from any FQ in the given work queue (WQ)
34691+ * - pull dequeue from any FQ in any WQ in the given channel
34692+ */
34693+/**
34694+ * qbman_pull_desc_set_fq() - Set fqid from which the dequeue command dequeues.
34695+ * @fqid: the frame queue index of the given FQ.
34696+ */
34697+void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, uint32_t fqid);
34698+
34699+/**
34700+ * qbman_pull_desc_set_wq() - Set wqid from which the dequeue command dequeues.
34701+ * @wqid: composed of channel id and wqid within the channel.
34702+ * @dct: the dequeue command type.
34703+ */
34704+void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, uint32_t wqid,
34705+ enum qbman_pull_type_e dct);
34706+
34707+/* qbman_pull_desc_set_channel() - Set channelid from which the dequeue command
34708+ * dequeues.
34709+ * @chid: the channel id to be dequeued.
34710+ * @dct: the dequeue command type.
34711+ */
34712+void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, uint32_t chid,
34713+ enum qbman_pull_type_e dct);
34714+
34715+/**
34716+ * qbman_swp_pull() - Issue the pull dequeue command
34717+ * @s: the software portal object.
34718+ * @d: the software portal descriptor which has been configured with
34719+ * the set of qbman_pull_desc_set_*() calls.
34720+ *
34721+ * Return 0 for success, and -EBUSY if the software portal is not ready
34722+ * to do pull dequeue.
34723+ */
34724+int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d);
34725+
34726+/* -------------------------------- */
34727+/* Polling DQRR for dequeue results */
34728+/* -------------------------------- */
34729+
34730+/**
34731+ * qbman_swp_dqrr_next() - Get an valid DQRR entry.
34732+ * @s: the software portal object.
34733+ *
34734+ * Return NULL if there are no unconsumed DQRR entries. Return a DQRR entry
34735+ * only once, so repeated calls can return a sequence of DQRR entries, without
34736+ * requiring they be consumed immediately or in any particular order.
34737+ */
34738+const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *);
34739+
34740+/**
34741+ * qbman_swp_dqrr_consume() - Consume DQRR entries previously returned from
34742+ * qbman_swp_dqrr_next().
34743+ * @s: the software portal object.
34744+ * @dq: the DQRR entry to be consumed.
34745+ */
34746+void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct qbman_result *dq);
34747+
34748+/**
34749+ * qbman_get_dqrr_idx() - Get dqrr index from the given dqrr
34750+ * @dqrr: the given dqrr object.
34751+ *
34752+ * Return dqrr index.
34753+ */
34754+uint8_t qbman_get_dqrr_idx(struct qbman_result *dqrr);
34755+
34756+/**
34757+ * qbman_get_dqrr_from_idx() - Use index to get the dqrr entry from the
34758+ * given portal
34759+ * @s: the given portal.
34760+ * @idx: the dqrr index.
34761+ *
34762+ * Return dqrr entry object.
34763+ */
34764+struct qbman_result *qbman_get_dqrr_from_idx(struct qbman_swp *s, uint8_t idx);
34765+
34766+/* ------------------------------------------------- */
34767+/* Polling user-provided storage for dequeue results */
34768+/* ------------------------------------------------- */
34769+
34770+/**
34771+ * qbman_result_has_new_result() - Check and get the dequeue response from the
34772+ * dq storage memory set in pull dequeue command
34773+ * @s: the software portal object.
34774+ * @dq: the dequeue result read from the memory.
34775+ *
34776+ * Only used for user-provided storage of dequeue results, not DQRR. For
34777+ * efficiency purposes, the driver will perform any required endianness
34778+ * conversion to ensure that the user's dequeue result storage is in host-endian
34779+ * format (whether or not that is the same as the little-endian format that
34780+ * hardware DMA'd to the user's storage). As such, once the user has called
34781+ * qbman_result_has_new_result() and been returned a valid dequeue result,
34782+ * they should not call it again on the same memory location (except of course
34783+ * if another dequeue command has been executed to produce a new result to that
34784+ * location).
34785+ *
34786+ * Return 1 for getting a valid dequeue result, or 0 for not getting a valid
34787+ * dequeue result.
34788+ */
34789+int qbman_result_has_new_result(struct qbman_swp *s,
34790+ const struct qbman_result *dq);
34791+
34792+/* -------------------------------------------------------- */
34793+/* Parsing dequeue entries (DQRR and user-provided storage) */
34794+/* -------------------------------------------------------- */
34795+
34796+/**
34797+ * qbman_result_is_DQ() - check the dequeue result is a dequeue response or not
34798+ * @dq: the dequeue result to be checked.
34799+ *
34800+ * DQRR entries may contain non-dequeue results, ie. notifications
34801+ */
34802+int qbman_result_is_DQ(const struct qbman_result *);
34803+
34804+/**
34805+ * qbman_result_is_SCN() - Check the dequeue result is notification or not
34806+ * @dq: the dequeue result to be checked.
34807+ *
34808+ * All the non-dequeue results (FQDAN/CDAN/CSCN/...) are "state change
34809+ * notifications" of one type or another. Some APIs apply to all of them, of the
34810+ * form qbman_result_SCN_***().
34811+ */
34812+static inline int qbman_result_is_SCN(const struct qbman_result *dq)
34813+{
34814+ return !qbman_result_is_DQ(dq);
34815+}
34816+
34817+/* Recognise different notification types, only required if the user allows for
34818+ * these to occur, and cares about them when they do.
34819+ */
34820+
34821+/**
34822+ * qbman_result_is_FQDAN() - Check for FQ Data Availability
34823+ * @dq: the qbman_result object.
34824+ *
34825+ * Return 1 if this is FQDAN.
34826+ */
34827+int qbman_result_is_FQDAN(const struct qbman_result *dq);
34828+
34829+/**
34830+ * qbman_result_is_CDAN() - Check for Channel Data Availability
34831+ * @dq: the qbman_result object to check.
34832+ *
34833+ * Return 1 if this is CDAN.
34834+ */
34835+int qbman_result_is_CDAN(const struct qbman_result *dq);
34836+
34837+/**
34838+ * qbman_result_is_CSCN() - Check for Congestion State Change
34839+ * @dq: the qbman_result object to check.
34840+ *
34841+ * Return 1 if this is CSCN.
34842+ */
34843+int qbman_result_is_CSCN(const struct qbman_result *dq);
34844+
34845+/**
34846+ * qbman_result_is_BPSCN() - Check for Buffer Pool State Change.
34847+ * @dq: the qbman_result object to check.
34848+ *
34849+ * Return 1 if this is BPSCN.
34850+ */
34851+int qbman_result_is_BPSCN(const struct qbman_result *dq);
34852+
34853+/**
34854+ * qbman_result_is_CGCU() - Check for Congestion Group Count Update.
34855+ * @dq: the qbman_result object to check.
34856+ *
34857+ * Return 1 if this is CGCU.
34858+ */
34859+int qbman_result_is_CGCU(const struct qbman_result *dq);
34860+
34861+/* Frame queue state change notifications; (FQDAN in theory counts too as it
34862+ * leaves a FQ parked, but it is primarily a data availability notification)
34863+ */
34864+
34865+/**
34866+ * qbman_result_is_FQRN() - Check for FQ Retirement Notification.
34867+ * @dq: the qbman_result object to check.
34868+ *
34869+ * Return 1 if this is FQRN.
34870+ */
34871+int qbman_result_is_FQRN(const struct qbman_result *);
34872+
34873+/**
34874+ * qbman_result_is_FQRNI() - Check for FQ Retirement Immediate
34875+ * @dq: the qbman_result object to check.
34876+ *
34877+ * Return 1 if this is FQRNI.
34878+ */
34879+int qbman_result_is_FQRNI(const struct qbman_result *);
34880+
34881+/**
34882+ * qbman_result_is_FQPN() - Check for FQ Park Notification
34883+ * @dq: the qbman_result object to check.
34884+ *
34885+ * Return 1 if this is FQPN.
34886+ */
34887+int qbman_result_is_FQPN(const struct qbman_result *dq);
34888+
34889+/* Parsing frame dequeue results (qbman_result_is_DQ() must be TRUE)
34890+ */
34891+/* FQ empty */
34892+#define QBMAN_DQ_STAT_FQEMPTY 0x80
34893+/* FQ held active */
34894+#define QBMAN_DQ_STAT_HELDACTIVE 0x40
34895+/* FQ force eligible */
34896+#define QBMAN_DQ_STAT_FORCEELIGIBLE 0x20
34897+/* Valid frame */
34898+#define QBMAN_DQ_STAT_VALIDFRAME 0x10
34899+/* FQ ODP enable */
34900+#define QBMAN_DQ_STAT_ODPVALID 0x04
34901+/* Volatile dequeue */
34902+#define QBMAN_DQ_STAT_VOLATILE 0x02
34903+/* volatile dequeue command is expired */
34904+#define QBMAN_DQ_STAT_EXPIRED 0x01
34905+
34906+/**
34907+ * qbman_result_DQ_flags() - Get the STAT field of dequeue response
34908+ * @dq: the dequeue result.
34909+ *
34910+ * Return the state field.
34911+ */
34912+uint32_t qbman_result_DQ_flags(const struct qbman_result *dq);
34913+
34914+/**
34915+ * qbman_result_DQ_is_pull() - Check whether the dq response is from a pull
34916+ * command.
34917+ * @dq: the dequeue result.
34918+ *
34919+ * Return 1 for volatile(pull) dequeue, 0 for static dequeue.
34920+ */
34921+static inline int qbman_result_DQ_is_pull(const struct qbman_result *dq)
34922+{
34923+ return (int)(qbman_result_DQ_flags(dq) & QBMAN_DQ_STAT_VOLATILE);
34924+}
34925+
34926+/**
34927+ * qbman_result_DQ_is_pull_complete() - Check whether the pull command is
34928+ * completed.
34929+ * @dq: the dequeue result.
34930+ *
34931+ * Return boolean.
34932+ */
34933+static inline int qbman_result_DQ_is_pull_complete(
34934+ const struct qbman_result *dq)
34935+{
34936+ return (int)(qbman_result_DQ_flags(dq) & QBMAN_DQ_STAT_EXPIRED);
34937+}
34938+
34939+/**
34940+ * qbman_result_DQ_seqnum() - Get the seqnum field in dequeue response
34941+ * seqnum is valid only if VALIDFRAME flag is TRUE
34942+ * @dq: the dequeue result.
34943+ *
34944+ * Return seqnum.
34945+ */
34946+uint16_t qbman_result_DQ_seqnum(const struct qbman_result *dq);
34947+
34948+/**
34949+ * qbman_result_DQ_odpid() - Get the seqnum field in dequeue response
34950+ * odpid is valid only if ODPVAILD flag is TRUE.
34951+ * @dq: the dequeue result.
34952+ *
34953+ * Return odpid.
34954+ */
34955+uint16_t qbman_result_DQ_odpid(const struct qbman_result *dq);
34956+
34957+/**
34958+ * qbman_result_DQ_fqid() - Get the fqid in dequeue response
34959+ * @dq: the dequeue result.
34960+ *
34961+ * Return fqid.
34962+ */
34963+uint32_t qbman_result_DQ_fqid(const struct qbman_result *dq);
34964+
34965+/**
34966+ * qbman_result_DQ_byte_count() - Get the byte count in dequeue response
34967+ * @dq: the dequeue result.
34968+ *
34969+ * Return the byte count remaining in the FQ.
34970+ */
34971+uint32_t qbman_result_DQ_byte_count(const struct qbman_result *dq);
34972+
34973+/**
34974+ * qbman_result_DQ_frame_count - Get the frame count in dequeue response
34975+ * @dq: the dequeue result.
34976+ *
34977+ * Return the frame count remaining in the FQ.
34978+ */
34979+uint32_t qbman_result_DQ_frame_count(const struct qbman_result *dq);
34980+
34981+/**
34982+ * qbman_result_DQ_fqd_ctx() - Get the frame queue context in dequeue response
34983+ * @dq: the dequeue result.
34984+ *
34985+ * Return the frame queue context.
34986+ */
34987+uint64_t qbman_result_DQ_fqd_ctx(const struct qbman_result *dq);
34988+
34989+/**
34990+ * qbman_result_DQ_fd() - Get the frame descriptor in dequeue response
34991+ * @dq: the dequeue result.
34992+ *
34993+ * Return the frame descriptor.
34994+ */
34995+const struct qbman_fd *qbman_result_DQ_fd(const struct qbman_result *dq);
34996+
34997+/* State-change notifications (FQDAN/CDAN/CSCN/...). */
34998+
34999+/**
35000+ * qbman_result_SCN_state() - Get the state field in State-change notification
35001+ * @scn: the state change notification.
35002+ *
35003+ * Return the state in the notifiation.
35004+ */
35005+uint8_t qbman_result_SCN_state(const struct qbman_result *scn);
35006+
35007+/**
35008+ * qbman_result_SCN_rid() - Get the resource id from the notification
35009+ * @scn: the state change notification.
35010+ *
35011+ * Return the resource id.
35012+ */
35013+uint32_t qbman_result_SCN_rid(const struct qbman_result *scn);
35014+
35015+/**
35016+ * qbman_result_SCN_ctx() - get the context from the notification
35017+ * @scn: the state change notification.
35018+ *
35019+ * Return the context.
35020+ */
35021+uint64_t qbman_result_SCN_ctx(const struct qbman_result *scn);
35022+
35023+/**
35024+ * qbman_result_SCN_state_in_mem() - Get the state in notification written
35025+ * in memory
35026+ * @scn: the state change notification.
35027+ *
35028+ * Return the state.
35029+ */
35030+uint8_t qbman_result_SCN_state_in_mem(const struct qbman_result *scn);
35031+
35032+/**
35033+ * qbman_result_SCN_rid_in_mem() - Get the resource id in notification written
35034+ * in memory.
35035+ * @scn: the state change notification.
35036+ *
35037+ * Return the resource id.
35038+ */
35039+uint32_t qbman_result_SCN_rid_in_mem(const struct qbman_result *scn);
35040+
35041+
35042+/* Type-specific "resource IDs". Mainly for illustration purposes, though it
35043+ * also gives the appropriate type widths.
35044+ */
35045+/* Get the FQID from the FQDAN */
35046+#define qbman_result_FQDAN_fqid(dq) qbman_result_SCN_rid(dq)
35047+/* Get the FQID from the FQRN */
35048+#define qbman_result_FQRN_fqid(dq) qbman_result_SCN_rid(dq)
35049+/* Get the FQID from the FQRNI */
35050+#define qbman_result_FQRNI_fqid(dq) qbman_result_SCN_rid(dq)
35051+/* Get the FQID from the FQPN */
35052+#define qbman_result_FQPN_fqid(dq) qbman_result_SCN_rid(dq)
35053+/* Get the channel ID from the CDAN */
35054+#define qbman_result_CDAN_cid(dq) ((uint16_t)qbman_result_SCN_rid(dq))
35055+/* Get the CGID from the CSCN */
35056+#define qbman_result_CSCN_cgid(dq) ((uint16_t)qbman_result_SCN_rid(dq))
35057+
35058+/**
35059+ * qbman_result_bpscn_bpid() - Get the bpid from BPSCN
35060+ * @scn: the state change notification.
35061+ *
35062+ * Return the buffer pool id.
35063+ */
35064+uint16_t qbman_result_bpscn_bpid(const struct qbman_result *scn);
35065+
35066+/**
35067+ * qbman_result_bpscn_has_free_bufs() - Check whether there are free
35068+ * buffers in the pool from BPSCN.
35069+ * @scn: the state change notification.
35070+ *
35071+ * Return the number of free buffers.
35072+ */
35073+int qbman_result_bpscn_has_free_bufs(const struct qbman_result *scn);
35074+
35075+/**
35076+ * qbman_result_bpscn_is_depleted() - Check BPSCN to see whether the
35077+ * buffer pool is depleted.
35078+ * @scn: the state change notification.
35079+ *
35080+ * Return the status of buffer pool depletion.
35081+ */
35082+int qbman_result_bpscn_is_depleted(const struct qbman_result *scn);
35083+
35084+/**
35085+ * qbman_result_bpscn_is_surplus() - Check BPSCN to see whether the buffer
35086+ * pool is surplus or not.
35087+ * @scn: the state change notification.
35088+ *
35089+ * Return the status of buffer pool surplus.
35090+ */
35091+int qbman_result_bpscn_is_surplus(const struct qbman_result *scn);
35092+
35093+/**
35094+ * qbman_result_bpscn_ctx() - Get the BPSCN CTX from BPSCN message
35095+ * @scn: the state change notification.
35096+ *
35097+ * Return the BPSCN context.
35098+ */
35099+uint64_t qbman_result_bpscn_ctx(const struct qbman_result *scn);
35100+
35101+/* Parsing CGCU */
35102+/**
35103+ * qbman_result_cgcu_cgid() - Check CGCU resouce id, i.e. cgid
35104+ * @scn: the state change notification.
35105+ *
35106+ * Return the CGCU resource id.
35107+ */
35108+uint16_t qbman_result_cgcu_cgid(const struct qbman_result *scn);
35109+
35110+/**
35111+ * qbman_result_cgcu_icnt() - Get the I_CNT from CGCU
35112+ * @scn: the state change notification.
35113+ *
35114+ * Return instantaneous count in the CGCU notification.
35115+ */
35116+uint64_t qbman_result_cgcu_icnt(const struct qbman_result *scn);
35117+
35118+ /************/
35119+ /* Enqueues */
35120+ /************/
35121+
35122+/**
35123+ * struct qbman_eq_desc - structure of enqueue descriptor
35124+ * @dont_manipulate_directly: the 8 32bit data to represent the whole
35125+ * possible qbman enqueue setting in enqueue descriptor.
35126+ */
35127+struct qbman_eq_desc {
35128+ uint32_t dont_manipulate_directly[8];
35129+};
35130+
35131+/**
35132+ * struct qbman_eq_response - structure of enqueue response
35133+ * @dont_manipulate_directly: the 16 32bit data to represent the whole
35134+ * enqueue response.
35135+ */
35136+struct qbman_eq_response {
35137+ uint32_t dont_manipulate_directly[16];
35138+};
35139+
35140+/**
35141+ * qbman_eq_desc_clear() - Clear the contents of a descriptor to
35142+ * default/starting state.
35143+ * @d: the given enqueue descriptor.
35144+ */
35145+void qbman_eq_desc_clear(struct qbman_eq_desc *d);
35146+
35147+/* Exactly one of the following descriptor "actions" should be set. (Calling
35148+ * any one of these will replace the effect of any prior call to one of these.)
35149+ * - enqueue without order-restoration
35150+ * - enqueue with order-restoration
35151+ * - fill a hole in the order-restoration sequence, without any enqueue
35152+ * - advance NESN (Next Expected Sequence Number), without any enqueue
35153+ * 'respond_success' indicates whether an enqueue response should be DMA'd
35154+ * after success (otherwise a response is DMA'd only after failure).
35155+ * 'incomplete' indicates that other fragments of the same 'seqnum' are yet to
35156+ * be enqueued.
35157+ */
35158+
35159+/**
35160+ * qbman_eq_desc_set_no_orp() - Set enqueue descriptor without orp
35161+ * @d: the enqueue descriptor.
35162+ * @response_success: 1 = enqueue with response always; 0 = enqueue with
35163+ * rejections returned on a FQ.
35164+ */
35165+void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success);
35166+/**
35167+ * qbman_eq_desc_set_orp() - Set order-resotration in the enqueue descriptor
35168+ * @d: the enqueue descriptor.
35169+ * @response_success: 1 = enqueue with response always; 0 = enqueue with
35170+ * rejections returned on a FQ.
35171+ * @opr_id: the order point record id.
35172+ * @seqnum: the order restoration sequence number.
35173+ * @incomplete: indiates whether this is the last fragments using the same
35174+ * sequeue number.
35175+ */
35176+void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success,
35177+ uint32_t opr_id, uint32_t seqnum, int incomplete);
35178+
35179+/**
35180+ * qbman_eq_desc_set_orp_hole() - fill a hole in the order-restoration sequence
35181+ * without any enqueue
35182+ * @d: the enqueue descriptor.
35183+ * @opr_id: the order point record id.
35184+ * @seqnum: the order restoration sequence number.
35185+ */
35186+void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, uint32_t opr_id,
35187+ uint32_t seqnum);
35188+
35189+/**
35190+ * qbman_eq_desc_set_orp_nesn() - advance NESN (Next Expected Sequence Number)
35191+ * without any enqueue
35192+ * @d: the enqueue descriptor.
35193+ * @opr_id: the order point record id.
35194+ * @seqnum: the order restoration sequence number.
35195+ */
35196+void qbman_eq_desc_set_orp_nesn(struct qbman_eq_desc *d, uint32_t opr_id,
35197+ uint32_t seqnum);
35198+/**
35199+ * qbman_eq_desc_set_response() - Set the enqueue response info.
35200+ * @d: the enqueue descriptor
35201+ * @storage_phys: the physical address of the enqueue response in memory.
35202+ * @stash: indicate that the write allocation enabled or not.
35203+ *
35204+ * In the case where an enqueue response is DMA'd, this determines where that
35205+ * response should go. (The physical/DMA address is given for hardware's
35206+ * benefit, but software should interpret it as a "struct qbman_eq_response"
35207+ * data structure.) 'stash' controls whether or not the write to main-memory
35208+ * expresses a cache-warming attribute.
35209+ */
35210+void qbman_eq_desc_set_response(struct qbman_eq_desc *d,
35211+ dma_addr_t storage_phys,
35212+ int stash);
35213+
35214+/**
35215+ * qbman_eq_desc_set_token() - Set token for the enqueue command
35216+ * @d: the enqueue descriptor
35217+ * @token: the token to be set.
35218+ *
35219+ * token is the value that shows up in an enqueue response that can be used to
35220+ * detect when the results have been published. The easiest technique is to zero
35221+ * result "storage" before issuing an enqueue, and use any non-zero 'token'
35222+ * value.
35223+ */
35224+void qbman_eq_desc_set_token(struct qbman_eq_desc *d, uint8_t token);
35225+
35226+/**
35227+ * Exactly one of the following descriptor "targets" should be set. (Calling any
35228+ * one of these will replace the effect of any prior call to one of these.)
35229+ * - enqueue to a frame queue
35230+ * - enqueue to a queuing destination
35231+ * Note, that none of these will have any affect if the "action" type has been
35232+ * set to "orp_hole" or "orp_nesn".
35233+ */
35234+/**
35235+ * qbman_eq_desc_set_fq() - Set Frame Queue id for the enqueue command
35236+ * @d: the enqueue descriptor
35237+ * @fqid: the id of the frame queue to be enqueued.
35238+ */
35239+void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, uint32_t fqid);
35240+
35241+/**
35242+ * qbman_eq_desc_set_qd() - Set Queuing Destination for the enqueue command.
35243+ * @d: the enqueue descriptor
35244+ * @qdid: the id of the queuing destination to be enqueued.
35245+ * @qd_bin: the queuing destination bin
35246+ * @qd_prio: the queuing destination priority.
35247+ */
35248+void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid,
35249+ uint32_t qd_bin, uint32_t qd_prio);
35250+
35251+/**
35252+ * qbman_eq_desc_set_eqdi() - enable/disable EQDI interrupt
35253+ * @d: the enqueue descriptor
35254+ * @enable: boolean to enable/disable EQDI
35255+ *
35256+ * Determines whether or not the portal's EQDI interrupt source should be
35257+ * asserted after the enqueue command is completed.
35258+ */
35259+void qbman_eq_desc_set_eqdi(struct qbman_eq_desc *d, int enable);
35260+
35261+/**
35262+ * qbman_eq_desc_set_dca() - Set DCA mode in the enqueue command.
35263+ * @d: the enqueue descriptor.
35264+ * @enable: enabled/disable DCA mode.
35265+ * @dqrr_idx: DCAP_CI, the DCAP consumer index.
35266+ * @park: determine the whether park the FQ or not
35267+ *
35268+ * Determines whether or not a portal DQRR entry should be consumed once the
35269+ * enqueue command is completed. (And if so, and the DQRR entry corresponds to a
35270+ * held-active (order-preserving) FQ, whether the FQ should be parked instead of
35271+ * being rescheduled.)
35272+ */
35273+void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable,
35274+ uint32_t dqrr_idx, int park);
35275+
35276+/**
35277+ * qbman_swp_enqueue() - Issue an enqueue command.
35278+ * @s: the software portal used for enqueue.
35279+ * @d: the enqueue descriptor.
35280+ * @fd: the frame descriptor to be enqueued.
35281+ *
35282+ * Please note that 'fd' should only be NULL if the "action" of the
35283+ * descriptor is "orp_hole" or "orp_nesn".
35284+ *
35285+ * Return 0 for a successful enqueue, -EBUSY if the EQCR is not ready.
35286+ */
35287+int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
35288+ const struct qbman_fd *fd);
35289+
35290+/* TODO:
35291+ * qbman_swp_enqueue_thresh() - Set threshold for EQRI interrupt.
35292+ * @s: the software portal.
35293+ * @thresh: the threshold to trigger the EQRI interrupt.
35294+ *
35295+ * An EQRI interrupt can be generated when the fill-level of EQCR falls below
35296+ * the 'thresh' value set here. Setting thresh==0 (the default) disables.
35297+ */
35298+int qbman_swp_enqueue_thresh(struct qbman_swp *s, unsigned int thresh);
35299+
35300+ /*******************/
35301+ /* Buffer releases */
35302+ /*******************/
35303+/**
35304+ * struct qbman_release_desc - The structure for buffer release descriptor
35305+ * @dont_manipulate_directly: the 32bit data to represent the whole
35306+ * possible settings of qbman release descriptor.
35307+ */
35308+struct qbman_release_desc {
35309+ uint32_t dont_manipulate_directly[1];
35310+};
35311+
35312+/**
35313+ * qbman_release_desc_clear() - Clear the contents of a descriptor to
35314+ * default/starting state.
35315+ * @d: the qbman release descriptor.
35316+ */
35317+void qbman_release_desc_clear(struct qbman_release_desc *d);
35318+
35319+/**
35320+ * qbman_release_desc_set_bpid() - Set the ID of the buffer pool to release to
35321+ * @d: the qbman release descriptor.
35322+ */
35323+void qbman_release_desc_set_bpid(struct qbman_release_desc *d, uint32_t bpid);
35324+
35325+/**
35326+ * qbman_release_desc_set_rcdi() - Determines whether or not the portal's RCDI
35327+ * interrupt source should be asserted after the release command is completed.
35328+ * @d: the qbman release descriptor.
35329+ */
35330+void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable);
35331+
35332+/**
35333+ * qbman_swp_release() - Issue a buffer release command.
35334+ * @s: the software portal object.
35335+ * @d: the release descriptor.
35336+ * @buffers: a pointer pointing to the buffer address to be released.
35337+ * @num_buffers: number of buffers to be released, must be less than 8.
35338+ *
35339+ * Return 0 for success, -EBUSY if the release command ring is not ready.
35340+ */
35341+int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
35342+ const uint64_t *buffers, unsigned int num_buffers);
35343+
35344+/* TODO:
35345+ * qbman_swp_release_thresh() - Set threshold for RCRI interrupt
35346+ * @s: the software portal.
35347+ * @thresh: the threshold.
35348+ * An RCRI interrupt can be generated when the fill-level of RCR falls below
35349+ * the 'thresh' value set here. Setting thresh==0 (the default) disables.
35350+ */
35351+int qbman_swp_release_thresh(struct qbman_swp *s, unsigned int thresh);
35352+
35353+ /*******************/
35354+ /* Buffer acquires */
35355+ /*******************/
35356+/**
35357+ * qbman_swp_acquire() - Issue a buffer acquire command.
35358+ * @s: the software portal object.
35359+ * @bpid: the buffer pool index.
35360+ * @buffers: a pointer pointing to the acquired buffer address|es.
35361+ * @num_buffers: number of buffers to be acquired, must be less than 8.
35362+ *
35363+ * Return 0 for success, or negative error code if the acquire command
35364+ * fails.
35365+ */
35366+int qbman_swp_acquire(struct qbman_swp *s, uint32_t bpid, uint64_t *buffers,
35367+ unsigned int num_buffers);
35368+
35369+ /*****************/
35370+ /* FQ management */
35371+ /*****************/
35372+/**
35373+ * qbman_swp_fq_schedule() - Move the fq to the scheduled state.
35374+ * @s: the software portal object.
35375+ * @fqid: the index of frame queue to be scheduled.
35376+ *
35377+ * There are a couple of different ways that a FQ can end up parked state,
35378+ * This schedules it.
35379+ *
35380+ * Return 0 for success, or negative error code for failure.
35381+ */
35382+int qbman_swp_fq_schedule(struct qbman_swp *s, uint32_t fqid);
35383+
35384+/**
35385+ * qbman_swp_fq_force() - Force the FQ to fully scheduled state.
35386+ * @s: the software portal object.
35387+ * @fqid: the index of frame queue to be forced.
35388+ *
35389+ * Force eligible will force a tentatively-scheduled FQ to be fully-scheduled
35390+ * and thus be available for selection by any channel-dequeuing behaviour (push
35391+ * or pull). If the FQ is subsequently "dequeued" from the channel and is still
35392+ * empty at the time this happens, the resulting dq_entry will have no FD.
35393+ * (qbman_result_DQ_fd() will return NULL.)
35394+ *
35395+ * Return 0 for success, or negative error code for failure.
35396+ */
35397+int qbman_swp_fq_force(struct qbman_swp *s, uint32_t fqid);
35398+
35399+/**
35400+ * These functions change the FQ flow-control stuff between XON/XOFF. (The
35401+ * default is XON.) This setting doesn't affect enqueues to the FQ, just
35402+ * dequeues. XOFF FQs will remain in the tenatively-scheduled state, even when
35403+ * non-empty, meaning they won't be selected for scheduled dequeuing. If a FQ is
35404+ * changed to XOFF after it had already become truly-scheduled to a channel, and
35405+ * a pull dequeue of that channel occurs that selects that FQ for dequeuing,
35406+ * then the resulting dq_entry will have no FD. (qbman_result_DQ_fd() will
35407+ * return NULL.)
35408+ */
35409+/**
35410+ * qbman_swp_fq_xon() - XON the frame queue.
35411+ * @s: the software portal object.
35412+ * @fqid: the index of frame queue.
35413+ *
35414+ * Return 0 for success, or negative error code for failure.
35415+ */
35416+int qbman_swp_fq_xon(struct qbman_swp *s, uint32_t fqid);
35417+/**
35418+ * qbman_swp_fq_xoff() - XOFF the frame queue.
35419+ * @s: the software portal object.
35420+ * @fqid: the index of frame queue.
35421+ *
35422+ * Return 0 for success, or negative error code for failure.
35423+ */
35424+int qbman_swp_fq_xoff(struct qbman_swp *s, uint32_t fqid);
35425+
35426+ /**********************/
35427+ /* Channel management */
35428+ /**********************/
35429+
35430+/**
35431+ * If the user has been allocated a channel object that is going to generate
35432+ * CDANs to another channel, then these functions will be necessary.
35433+ * CDAN-enabled channels only generate a single CDAN notification, after which
35434+ * it they need to be reenabled before they'll generate another. (The idea is
35435+ * that pull dequeuing will occur in reaction to the CDAN, followed by a
35436+ * reenable step.) Each function generates a distinct command to hardware, so a
35437+ * combination function is provided if the user wishes to modify the "context"
35438+ * (which shows up in each CDAN message) each time they reenable, as a single
35439+ * command to hardware.
35440+ */
35441+
35442+/**
35443+ * qbman_swp_CDAN_set_context() - Set CDAN context
35444+ * @s: the software portal object.
35445+ * @channelid: the channel index.
35446+ * @ctx: the context to be set in CDAN.
35447+ *
35448+ * Return 0 for success, or negative error code for failure.
35449+ */
35450+int qbman_swp_CDAN_set_context(struct qbman_swp *s, uint16_t channelid,
35451+ uint64_t ctx);
35452+
35453+/**
35454+ * qbman_swp_CDAN_enable() - Enable CDAN for the channel.
35455+ * @s: the software portal object.
35456+ * @channelid: the index of the channel to generate CDAN.
35457+ *
35458+ * Return 0 for success, or negative error code for failure.
35459+ */
35460+int qbman_swp_CDAN_enable(struct qbman_swp *s, uint16_t channelid);
35461+
35462+/**
35463+ * qbman_swp_CDAN_disable() - disable CDAN for the channel.
35464+ * @s: the software portal object.
35465+ * @channelid: the index of the channel to generate CDAN.
35466+ *
35467+ * Return 0 for success, or negative error code for failure.
35468+ */
35469+int qbman_swp_CDAN_disable(struct qbman_swp *s, uint16_t channelid);
35470+
35471+/**
35472+ * qbman_swp_CDAN_set_context_enable() - Set CDAN contest and enable CDAN
35473+ * @s: the software portal object.
35474+ * @channelid: the index of the channel to generate CDAN.
35475+ * @ctx: the context set in CDAN.
35476+ *
35477+ * Return 0 for success, or negative error code for failure.
35478+ */
35479+int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s, uint16_t channelid,
35480+ uint64_t ctx);
35481+int qbman_swp_fill_ring(struct qbman_swp *s,
35482+ const struct qbman_eq_desc *d,
35483+ const struct qbman_fd *fd,
35484+ uint8_t burst_index);
35485+int qbman_swp_flush_ring(struct qbman_swp *s);
35486+void qbman_sync(void);
35487+int qbman_swp_send_multiple(struct qbman_swp *s,
35488+ const struct qbman_eq_desc *d,
35489+ const struct qbman_fd *fd,
35490+ int frames_to_send);
35491+
35492+int qbman_check_command_complete(struct qbman_swp *s,
35493+ const struct qbman_result *dq);
35494+#endif /* !_FSL_QBMAN_PORTAL_H */
35495diff --git a/drivers/net/dpaa2/rte_eth_dpaa2_pvt.h b/drivers/net/dpaa2/rte_eth_dpaa2_pvt.h
35496new file mode 100644
35497index 0000000..b35c3ee
35498--- /dev/null
35499+++ b/drivers/net/dpaa2/rte_eth_dpaa2_pvt.h
35500@@ -0,0 +1,313 @@
35501+/*-
35502+ * BSD LICENSE
35503+ *
35504+ * Copyright(c) 2014 Freescale Semiconductor. All rights reserved.
35505+ * All rights reserved.
35506+ *
35507+ * Redistribution and use in source and binary forms, with or without
35508+ * modification, are permitted provided that the following conditions
35509+ * are met:
35510+ *
35511+ * * Redistributions of source code must retain the above copyright
35512+ * notice, this list of conditions and the following disclaimer.
35513+ * * Redistributions in binary form must reproduce the above copyright
35514+ * notice, this list of conditions and the following disclaimer in
35515+ * the documentation and/or other materials provided with the
35516+ * distribution.
35517+ * * Neither the name of Freescale Semiconductor nor the names of its
35518+ * contributors may be used to endorse or promote products derived
35519+ * from this software without specific prior written permission.
35520+ *
35521+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35522+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35523+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
35524+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35525+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35526+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35527+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35528+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35529+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35530+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35531+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35532+ */
35533+
35534+#ifndef _RTE_ETH_DPAA2_PVT_H_
35535+#define _RTE_ETH_DPAA2_PVT_H_
35536+
35537+#include <rte_memory.h>
35538+#include <rte_mbuf.h>
35539+#include <rte_atomic.h>
35540+#include <fsl_mc_sys.h>
35541+#include <eal_vfio.h>
35542+#include <eal_vfio_fsl_mc.h>
35543+
35544+typedef uint64_t dma_addr_t;
35545+
35546+#define FALSE 0
35547+#define TRUE 1
35548+#ifndef false
35549+#define false FALSE
35550+#endif
35551+#ifndef true
35552+#define true TRUE
35553+#endif
35554+#define lower_32_bits(x) ((uint32_t)(x))
35555+#define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
35556+
35557+#ifndef ETH_ADDR_LEN
35558+#define ETH_ADDR_LEN 6
35559+#endif
35560+#ifndef ETH_VLAN_HLEN
35561+#define ETH_VLAN_HLEN 4 /** < Vlan Header Length */
35562+#endif
35563+
35564+#define NUM_MAX_RECV_FRAMES 16
35565+
35566+#define MC_PORTAL_INDEX 0
35567+#define NUM_DPIO_REGIONS 2
35568+#define NUM_DQS_PER_QUEUE 2
35569+#define MC_PORTALS_BASE_PADDR 0x00080C000000ULL
35570+#define MC_PORTAL_STRIDE 0x10000
35571+#define MC_PORTAL_SIZE 64
35572+#define MC_PORTAL_ID_TO_PADDR(portal_id) \
35573+(MC_PORTALS_BASE_PADDR + (portal_id) * MC_PORTAL_STRIDE)
35574+
35575+struct dpaa2_dpio_dev {
35576+ TAILQ_ENTRY(dpaa2_dpio_dev) next; /**< Pointer to Next device instance */
35577+ uint16_t index; /**< Index of a instance in the list */
35578+ rte_atomic16_t ref_count; /**< How many thread contexts are sharing this.*/
35579+ struct fsl_mc_io *dpio; /** handle to DPIO portal object */
35580+ uint16_t token;
35581+ struct qbman_swp *sw_portal; /** SW portal object */
35582+ const struct qbman_result *dqrr[4]; /**< DQRR Entry for this SW portal */
35583+ pthread_mutex_t lock; /** Required when Portal is shared */
35584+ void *mc_portal; /**< MC Portal for configuring this device */
35585+ uintptr_t qbman_portal_ce_paddr; /**< Physical address of Cache Enabled Area */
35586+ uintptr_t ce_size; /**< Size of the CE region */
35587+ uintptr_t qbman_portal_ci_paddr; /**< Physical address of Cache Inhibit Area */
35588+ uintptr_t ci_size; /**< Size of the CI region */
35589+ void *intr_handle;
35590+ int32_t vfio_fd; /**< File descriptor received via VFIO */
35591+ int32_t hw_id; /**< An unique ID of this DPIO device instance */
35592+};
35593+
35594+struct queue_storage_info_t {
35595+ struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
35596+ struct qbman_result *active_dqs;
35597+ int toggle;
35598+};
35599+
35600+struct thread_io_info_t {
35601+ struct dpaa2_dpio_dev *dpio_dev;
35602+ struct dpaa2_dpio_dev *sec_dpio_dev;
35603+ struct qbman_result *global_active_dqs;
35604+};
35605+
35606+/*! Global per thread DPIO portal */
35607+extern __thread struct thread_io_info_t thread_io_info;
35608+/*! Global MCP list */
35609+extern void *(*mcp_ptr_list);
35610+
35611+/* Refer to Table 7-3 in SEC BG */
35612+struct qbman_fle {
35613+ uint32_t addr_lo;
35614+ uint32_t addr_hi;
35615+ uint32_t length;
35616+ /* FMT must be 00, MSB is final bit */
35617+ uint32_t fin_bpid_offset;
35618+ uint32_t frc;
35619+ uint32_t reserved[3]; /* Not used currently */
35620+};
35621+
35622+/* Maximum release/acquire from QBMAN */
35623+#define DPAA2_MBUF_MAX_ACQ_REL 7
35624+
35625+#define MAX_BPID 256
35626+
35627+/*Macros to define operations on FD*/
35628+#define DPAA2_SET_FD_ADDR(fd, addr) \
35629+ fd->simple.addr_lo = lower_32_bits((uint64_t)addr); \
35630+ fd->simple.addr_hi = upper_32_bits((uint64_t)addr);
35631+#define DPAA2_SET_FD_LEN(fd, length) fd->simple.len = length
35632+#define DPAA2_SET_FD_BPID(fd, bpid) fd->simple.bpid_offset |= bpid;
35633+#define DPAA2_SET_FD_IVP(fd) ((fd->simple.bpid_offset |= 0x00004000))
35634+#define DPAA2_SET_FD_OFFSET(fd, offset) (fd->simple.bpid_offset |= (uint32_t)(offset) << 16);
35635+#define DPAA2_SET_FD_FRC(fd, frc) fd->simple.frc = frc;
35636+#define DPAA2_RESET_FD_CTRL(fd) fd->simple.ctrl = 0;
35637+
35638+#define DPAA2_SET_FD_ASAL(fd, asal) (fd->simple.ctrl |= (asal << 16))
35639+#define DPAA2_SET_FD_FLC(fd, addr) \
35640+ fd->simple.flc_lo = lower_32_bits((uint64_t)addr); \
35641+ fd->simple.flc_hi = upper_32_bits((uint64_t)addr);
35642+#define DPAA2_GET_FLE_ADDR(fle) \
35643+ (uint64_t)((((uint64_t)(fle->addr_hi)) << 32) + fle->addr_lo)
35644+#define DPAA2_SET_FLE_ADDR(fle, addr) \
35645+ fle->addr_lo = lower_32_bits((uint64_t)addr); \
35646+ fle->addr_hi = upper_32_bits((uint64_t)addr);
35647+#define DPAA2_SET_FLE_OFFSET(fle, offset) (fle)->fin_bpid_offset |= (uint32_t)(offset) << 16;
35648+#define DPAA2_SET_FLE_BPID(fle, bpid) (fle)->fin_bpid_offset |= (uint64_t)bpid;
35649+#define DPAA2_GET_FLE_BPID(fle, bpid) (fle->fin_bpid_offset & 0x000000ff)
35650+#define DPAA2_SET_FLE_FIN(fle) fle->fin_bpid_offset |= (uint64_t)1 << 31;
35651+#define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))
35652+#define DPAA2_SET_FD_COMPOUND_FMT(fd) \
35653+ fd->simple.bpid_offset |= (uint32_t)1 << 28;
35654+#define DPAA2_GET_FD_ADDR(fd) \
35655+ (uint64_t)((((uint64_t)(fd->simple.addr_hi)) << 32) + fd->simple.addr_lo)
35656+#define DPAA2_GET_FD_LEN(fd) (fd->simple.len)
35657+#define DPAA2_GET_FD_BPID(fd) ((fd->simple.bpid_offset & 0x00003FFF))
35658+#define DPAA2_GET_FD_IVP(fd) ((fd->simple.bpid_offset & 0x00004000) >> 14)
35659+#define DPAA2_GET_FD_OFFSET(fd) ((fd->simple.bpid_offset & 0x0FFF0000) >> 16)
35660+#define DPAA2_GET_FD_FRC(fd) (fd->simple.frc)
35661+#define DPAA2_GET_FD_FLC(fd) \
35662+ (uint64_t)((((uint64_t)(fd->simple.flc_hi)) << 32) + fd->simple.flc_lo)
35663+
35664+#define DPAA2_SET_FLE_SG_EXT(fle) fle->fin_bpid_offset |= (uint64_t)1<<29;
35665+#define DPAA2_IS_SET_FLE_SG_EXT(fle) \
35666+ (fle->fin_bpid_offset & ((uint64_t)1<<29))? 1 : 0
35667+
35668+#define DPAA2_INLINE_MBUF_FROM_BUF(buf) \
35669+ ((struct rte_mbuf *)((uint64_t)buf + DPAA2_FD_PTA_SIZE + DPAA2_MBUF_HW_ANNOTATION + DPAA2_RES))
35670+#define DPAA2_BUF_FROM_INLINE_MBUF(mbuf) \
35671+ ((uint8_t *)((uint64_t)mbuf - (DPAA2_FD_PTA_SIZE + DPAA2_MBUF_HW_ANNOTATION + DPAA2_RES)))
35672+
35673+#define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
35674+
35675+/*Macros to define QBMAN enqueue options */
35676+#define DPAA2_ETH_EQ_DISABLE 0 /*!< Dont Enqueue the Frame */
35677+#define DPAA2_ETH_EQ_RESP_ON_SUCC 1 /*!< Enqueue the Frame with
35678+ response after success*/
35679+#define DPAA2_ETH_EQ_RESP_ON_FAIL 2 /*!< Enqueue the Frame with
35680+ response after failure*/
35681+#define DPAA2_ETH_EQ_NO_RESP 3 /*!< Enqueue the Frame without
35682+ response*/
35683+/* Only Enqueue Error responses will be
35684+ * pushed on FQID_ERR of Enqueue FQ */
35685+#define DPAA2_EQ_RESP_ERR_FQ 0
35686+/* All Enqueue responses will be pushed on address
35687+ * set with qbman_eq_desc_set_response */
35688+#define DPAA2_EQ_RESP_ALWAYS 1
35689+
35690+#define DPAA2_MAX_BUF_POOLS 8
35691+
35692+struct dpbp_node {
35693+ struct dpbp_node *next;
35694+ struct fsl_mc_io dpbp;
35695+ uint16_t token;
35696+ int dpbp_id;
35697+};
35698+
35699+struct buf_pool_cfg {
35700+ void *addr; /*!< The address from where DPAA2 will carve out the
35701+ * buffers. 'addr' should be 'NULL' if user wants
35702+ * to create buffers from the memory which user
35703+ * asked DPAA2 to reserve during 'nadk init' */
35704+ phys_addr_t phys_addr; /*!< corresponding physical address
35705+ * of the memory provided in addr */
35706+ uint32_t num; /*!< number of buffers */
35707+ uint32_t size; /*!< size of each buffer. 'size' should include
35708+ * any headroom to be reserved and alignment */
35709+ uint16_t align; /*!< Buffer alignment (in bytes) */
35710+ uint16_t bpid; /*!< The buffer pool id. This will be filled
35711+ *in by DPAA2 for each buffer pool */
35712+};
35713+
35714+struct buf_pool {
35715+ uint32_t size;
35716+ uint32_t num_bufs;
35717+ uint16_t bpid;
35718+ uint8_t *h_bpool_mem;
35719+ struct rte_mempool *mp;
35720+ struct dpbp_node *dpbp_node;
35721+};
35722+
35723+/*!
35724+ * Buffer pool list configuration structure. User need to give DPAA2 the
35725+ * valid number of 'num_buf_pools'.
35726+ */
35727+struct dpaa2_bp_list_cfg {
35728+ struct buf_pool_cfg buf_pool; /* Configuration
35729+ * of each buffer pool */
35730+};
35731+
35732+struct dpaa2_bp_list {
35733+ struct dpaa2_bp_list *next;
35734+ struct rte_mempool *mp;
35735+ struct buf_pool buf_pool;
35736+};
35737+
35738+struct bp_info {
35739+ uint32_t size;
35740+ uint32_t meta_data_size;
35741+ struct dpaa2_bp_list *bp_list;
35742+};
35743+
35744+extern struct dpaa2_bp_list *h_bp_list;
35745+
35746+//todo - this is costly, need to write a fast coversion routine
35747+static void *dpaa2_mem_ptov(phys_addr_t paddr)
35748+{
35749+ const struct rte_memseg *memseg = rte_eal_get_physmem_layout();
35750+ int i;
35751+
35752+ for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
35753+ if (paddr >= memseg[i].phys_addr &&
35754+ (char *)paddr < (char *)memseg[i].phys_addr + memseg[i].len)
35755+ return (void *)(memseg[i].addr_64 + (paddr - memseg[i].phys_addr));
35756+ }
35757+ return NULL;
35758+}
35759+
35760+static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
35761+{
35762+ const struct rte_memseg *memseg = rte_eal_get_physmem_layout();
35763+ int i;
35764+
35765+ for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
35766+ if (vaddr >= memseg[i].addr_64 &&
35767+ vaddr < memseg[i].addr_64 + memseg[i].len)
35768+ return memseg[i].phys_addr + (vaddr - memseg[i].addr_64);
35769+ }
35770+ return (phys_addr_t)(NULL);
35771+}
35772+
35773+#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
35774+/*
35775+ * When we are using Physical addresses as IO Virtual Addresses,
35776+ * we call conversion routines nadk_mem_vtop & nadk_mem_ptov wherever required.
35777+ * These routines are called with help of below MACRO's
35778+ */
35779+
35780+#define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) (mbuf->buf_physaddr)
35781+
35782+/**
35783+ * macro to convert Virtual address to IOVA
35784+ */
35785+#define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((uint64_t)(_vaddr))
35786+
35787+/**
35788+ * macro to convert IOVA to Virtual address
35789+ */
35790+#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((phys_addr_t)(_iova))
35791+
35792+/**
35793+ * macro to convert modify the memory containing Virtual address to IOVA
35794+ */
35795+#define DPAA2_MODIFY_VADDR_TO_IOVA(_mem, _type) \
35796+ {_mem = (_type)(dpaa2_mem_vtop((uint64_t)(_mem))); }
35797+
35798+/**
35799+ * macro to convert modify the memory containing IOVA to Virtual address
35800+ */
35801+#define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
35802+ {_mem = (_type)(dpaa2_mem_ptov((phys_addr_t)(_mem))); }
35803+
35804+#else
35805+#define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) (mbuf->buf_addr)
35806+
35807+#define DPAA2_VADDR_TO_IOVA(_vaddr) (_vaddr)
35808+#define DPAA2_IOVA_TO_VADDR(_iova) (_iova)
35809+#define DPAA2_MODIFY_VADDR_TO_IOVA(_mem, _type)
35810+#define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type)
35811+#endif
35812+
35813+#endif
35814diff --git a/drivers/net/dpaa2/rte_eth_dpbp.c b/drivers/net/dpaa2/rte_eth_dpbp.c
35815new file mode 100644
35816index 0000000..6a7617d
35817--- /dev/null
35818+++ b/drivers/net/dpaa2/rte_eth_dpbp.c
35819@@ -0,0 +1,430 @@
35820+/*-
35821+ * BSD LICENSE
35822+ *
35823+ * Copyright(c) 2014 Freescale Semiconductor. All rights reserved.
35824+ * All rights reserved.
35825+ *
35826+ * Redistribution and use in source and binary forms, with or without
35827+ * modification, are permitted provided that the following conditions
35828+ * are met:
35829+ *
35830+ * * Redistributions of source code must retain the above copyright
35831+ * notice, this list of conditions and the following disclaimer.
35832+ * * Redistributions in binary form must reproduce the above copyright
35833+ * notice, this list of conditions and the following disclaimer in
35834+ * the documentation and/or other materials provided with the
35835+ * distribution.
35836+ * * Neither the name of Freescale Semiconductor nor the names of its
35837+ * contributors may be used to endorse or promote products derived
35838+ * from this software without specific prior written permission.
35839+ *
35840+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35841+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35842+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
35843+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35844+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35845+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35846+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35847+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35848+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35849+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35850+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35851+ */
35852+
35853+#include <unistd.h>
35854+#include <stdio.h>
35855+#include <sys/types.h>
35856+#include <string.h>
35857+#include <stdlib.h>
35858+#include <fcntl.h>
35859+#include <errno.h>
35860+#include <sys/ioctl.h>
35861+#include <sys/stat.h>
35862+#include <sys/types.h>
35863+#include <sys/mman.h>
35864+#include <sys/vfs.h>
35865+#include <libgen.h>
35866+#include <rte_mbuf.h>
35867+
35868+#include "rte_pci.h"
35869+#include "rte_memzone.h"
35870+
35871+#include "rte_eth_dpaa2_pvt.h"
35872+#include "fsl_qbman_portal.h"
35873+#include <fsl_dpbp.h>
35874+
35875+#include <rte_log.h>
35876+#include "dpaa2_logs.h"
35877+
35878+static struct dpbp_node *g_dpbp_list;
35879+static struct dpbp_node *avail_dpbp;
35880+
35881+struct bp_info bpid_info[MAX_BPID];
35882+
35883+struct dpaa2_bp_list *h_bp_list;
35884+
35885+int
35886+dpaa2_create_dpbp_device(
35887+ int dpbp_id)
35888+{
35889+ struct dpbp_node *dpbp_node;
35890+ int ret;
35891+
35892+ /* Allocate DPAA2 dpbp handle */
35893+ dpbp_node = (struct dpbp_node *)malloc(sizeof(struct dpbp_node));
35894+ if (!dpbp_node) {
35895+ PMD_DRV_LOG(ERR, "Memory allocation failed for DPBP Device\n");
35896+ return -1;
35897+ }
35898+
35899+ /* Open the dpbp object */
35900+ dpbp_node->dpbp.regs = mcp_ptr_list[MC_PORTAL_INDEX];
35901+ ret = dpbp_open(&dpbp_node->dpbp, CMD_PRI_LOW, dpbp_id, &dpbp_node->token);
35902+ if (ret) {
35903+ PMD_DRV_LOG(ERR, "Resource allocation failure with err code: %d",
35904+ ret);
35905+ free(dpbp_node);
35906+ return -1;
35907+ }
35908+
35909+ /* Clean the device first */
35910+ ret = dpbp_reset(&dpbp_node->dpbp, CMD_PRI_LOW, dpbp_node->token);
35911+ if (ret) {
35912+ PMD_DRV_LOG(ERR, "Failure cleaning dpbp device with"
35913+ "error code %d\n", ret);
35914+ return -1;
35915+ }
35916+
35917+ dpbp_node->dpbp_id = dpbp_id;
35918+ /* Add the dpbp handle into the global list */
35919+ dpbp_node->next = g_dpbp_list;
35920+ g_dpbp_list = dpbp_node;
35921+ avail_dpbp = g_dpbp_list;
35922+
35923+ PMD_DRV_LOG(INFO, "Buffer resource initialized\n");
35924+
35925+ return 0;
35926+}
35927+
35928+int hw_mbuf_create_pool(struct rte_mempool *mp)
35929+{
35930+ struct dpaa2_bp_list *bp_list;
35931+ struct dpbp_attr dpbp_attr;
35932+ int ret;
35933+
35934+ if (!avail_dpbp) {
35935+ PMD_DRV_LOG(ERR, "DPAA2 resources not available\n");
35936+ return -1;
35937+ }
35938+
35939+ ret = dpbp_enable(&avail_dpbp->dpbp, CMD_PRI_LOW, avail_dpbp->token);
35940+ if (ret != 0) {
35941+ PMD_DRV_LOG(ERR, "Resource enable failure with"
35942+ "err code: %d\n", ret);
35943+ return -1;
35944+ }
35945+
35946+ ret = dpbp_get_attributes(&avail_dpbp->dpbp, CMD_PRI_LOW,
35947+ avail_dpbp->token, &dpbp_attr);
35948+ if (ret != 0) {
35949+ PMD_DRV_LOG(ERR, "Resource read failure with"
35950+ "err code: %d\n", ret);
35951+ ret = dpbp_disable(&avail_dpbp->dpbp, CMD_PRI_LOW,
35952+ avail_dpbp->token);
35953+ return -1;
35954+ }
35955+
35956+ /* Allocate the bp_list which will be added into global_bp_list */
35957+ bp_list = (struct dpaa2_bp_list *)malloc(sizeof(struct dpaa2_bp_list));
35958+ if (!bp_list) {
35959+ PMD_DRV_LOG(ERR, "No heap memory available\n");
35960+ return -1;
35961+ }
35962+
35963+ /* Set parameters of buffer pool list */
35964+ bp_list->buf_pool.num_bufs = mp->size;
35965+ bp_list->buf_pool.size = mp->elt_size
35966+ - sizeof(struct rte_mbuf) - rte_pktmbuf_priv_size(mp);
35967+ bp_list->buf_pool.bpid = dpbp_attr.bpid;
35968+ bp_list->buf_pool.h_bpool_mem = NULL;
35969+ bp_list->buf_pool.mp = mp;
35970+ bp_list->buf_pool.dpbp_node = avail_dpbp;
35971+ bp_list->next = h_bp_list;
35972+
35973+ mp->offload_ptr = dpbp_attr.bpid;
35974+
35975+ /* Increment the available DPBP */
35976+ avail_dpbp = avail_dpbp->next;
35977+
35978+ bpid_info[dpbp_attr.bpid].size = bp_list->buf_pool.size;
35979+ bpid_info[dpbp_attr.bpid].meta_data_size = sizeof(struct rte_mbuf)
35980+ + rte_pktmbuf_priv_size(mp);
35981+ bpid_info[dpbp_attr.bpid].bp_list = bp_list;
35982+
35983+ PMD_DRV_LOG(INFO, "BP List created for bpid =%d\n", dpbp_attr.bpid);
35984+
35985+ h_bp_list = bp_list;
35986+ return 0;
35987+}
35988+
35989+static inline void dpaa2_mbuf_release(uint64_t buf, uint32_t bpid)
35990+{
35991+ struct qbman_release_desc releasedesc;
35992+ struct qbman_swp *swp;
35993+ int ret;
35994+
35995+ if (!thread_io_info.dpio_dev) {
35996+ ret = dpaa2_affine_qbman_swp();
35997+ if (ret != 0) {
35998+ PMD_DRV_LOG(ERR, "Failed to allocate IO portal");
35999+ return;
36000+ }
36001+ }
36002+ swp = thread_io_info.dpio_dev->sw_portal;
36003+
36004+ /* Create a release descriptor required for releasing
36005+ * buffers into BMAN */
36006+ qbman_release_desc_clear(&releasedesc);
36007+ qbman_release_desc_set_bpid(&releasedesc, bpid);
36008+
36009+ DPAA2_MODIFY_VADDR_TO_IOVA(buf, uint64_t);
36010+ do {
36011+ /* Release buffer into the BMAN */
36012+ ret = qbman_swp_release(swp, &releasedesc, &buf, 1);
36013+ } while (ret == -EBUSY);
36014+ PMD_TX_FREE_LOG(DEBUG, "Released %p address to BMAN\n", buf);
36015+}
36016+
36017+int hw_mbuf_alloc(struct rte_mempool *mp, void **mb)
36018+{
36019+ struct qbman_swp *swp;
36020+ uint16_t bpid;
36021+ uint64_t buf;
36022+ int ret;
36023+ struct rte_mbuf *m;
36024+
36025+ if ((mp->offload_ptr > MAX_BPID) ||
36026+ !(bpid_info[mp->offload_ptr].bp_list)) {
36027+
36028+ PMD_DRV_LOG(INFO, "DPAA2 buffer pool not configured\n");
36029+ return -2;
36030+ }
36031+
36032+ bpid = mp->offload_ptr;
36033+
36034+ if (!thread_io_info.dpio_dev) {
36035+ ret = dpaa2_affine_qbman_swp();
36036+ if (ret != 0) {
36037+ PMD_DRV_LOG(ERR, "Failed to allocate IO portal");
36038+ return -1;
36039+ }
36040+ }
36041+ swp = thread_io_info.dpio_dev->sw_portal;
36042+
36043+ do {
36044+ ret = qbman_swp_acquire(swp, bpid, &buf, 1);
36045+ } while (ret == -EBUSY);
36046+ if (ret <= 0) {
36047+ PMD_DRV_LOG(INFO, "Buffer alloc(bpid %d)fail: err: %x",
36048+ bpid, ret);
36049+ return -1;
36050+ }
36051+ DPAA2_MODIFY_IOVA_TO_VADDR(buf, uint64_t);
36052+
36053+ PMD_DRV_LOG(INFO, "Acquired %p address from BMAN\n", buf);
36054+ m = (struct rte_mbuf *)DPAA2_INLINE_MBUF_FROM_BUF(buf);
36055+ RTE_MBUF_ASSERT(rte_mbuf_refcnt_read(m) == 0);
36056+ rte_mbuf_refcnt_set(m, 1);
36057+ *mb = m;
36058+ return 0;
36059+}
36060+
36061+int hw_mbuf_free(void __rte_unused *m)
36062+{
36063+ struct rte_mbuf *mb = (struct rte_mbuf *)m;
36064+ if ((mb->pool->offload_ptr > MAX_BPID) ||
36065+ !(bpid_info[mb->pool->offload_ptr].bp_list)) {
36066+
36067+ PMD_DRV_LOG(INFO, "DPAA2 buffer pool not configured\n");
36068+ return -1;
36069+ }
36070+
36071+ dpaa2_mbuf_release((uint64_t)DPAA2_BUF_FROM_INLINE_MBUF(m),
36072+ mb->pool->offload_ptr);
36073+ return 0;
36074+}
36075+
36076+int hw_mbuf_alloc_bulk(struct rte_mempool *pool,
36077+ void **obj_table, unsigned count)
36078+{
36079+ static int alloc;
36080+ struct qbman_swp *swp;
36081+ uint32_t mbuf_size;
36082+ uint16_t bpid;
36083+ uint64_t bufs[64];
36084+ int ret;
36085+ unsigned i, n = 0;
36086+ struct rte_mbuf **mt = (struct rte_mbuf **)obj_table;
36087+
36088+ //PMD_DRV_LOG(DEBUG, MBUF, "%s/n", __func__);
36089+ if ((pool->offload_ptr > MAX_BPID) ||
36090+ !(bpid_info[pool->offload_ptr].bp_list)) {
36091+
36092+ printf("\nDPAA2 buffer pool not configured\n");
36093+ return -2;
36094+ }
36095+
36096+ bpid = pool->offload_ptr;
36097+
36098+ if (!thread_io_info.dpio_dev) {
36099+ ret = dpaa2_affine_qbman_swp();
36100+ if (ret != 0) {
36101+ PMD_DRV_LOG(ERR, "Failed to allocate IO portal");
36102+ return -1;
36103+ }
36104+ }
36105+ swp = thread_io_info.dpio_dev->sw_portal;
36106+
36107+ /* if number of buffers requested is less than 7 */
36108+ if (count < DPAA2_MBUF_MAX_ACQ_REL) {
36109+ ret = qbman_swp_acquire(swp, bpid, &bufs[n], count);
36110+ if (ret <= 0){
36111+ PMD_DRV_LOG(ERR, "Failed to allocate buffers %d", ret);
36112+ return -1;
36113+ }
36114+ n = ret;
36115+ goto set_buf;
36116+ }
36117+
36118+ while (n < count) {
36119+ ret = 0;
36120+ /* Acquire is all-or-nothing, so we drain in 7s,
36121+ * then in 1s for the remainder. */
36122+ if ((count - n) > DPAA2_MBUF_MAX_ACQ_REL) {
36123+ ret = qbman_swp_acquire(swp, bpid, &bufs[n],
36124+ DPAA2_MBUF_MAX_ACQ_REL);
36125+ if (ret == DPAA2_MBUF_MAX_ACQ_REL) {
36126+ n += ret;
36127+ }
36128+ }
36129+ if (ret < DPAA2_MBUF_MAX_ACQ_REL) {
36130+ ret = qbman_swp_acquire(swp, bpid, &bufs[n], 1);
36131+ if (ret > 0) {
36132+ PMD_DRV_LOG(DEBUG, "Drained buffer: %x",
36133+ bufs[n]);
36134+ n += ret;
36135+ }
36136+ }
36137+ if (ret < 0) {
36138+ PMD_DRV_LOG(WARNING, "Buffer aquire failed with"
36139+ "err code: %d", ret);
36140+ break;
36141+ }
36142+ }
36143+ if (ret < 0 || n == 0){
36144+ PMD_DRV_LOG(ERR, "Failed to allocate buffers %d", ret);
36145+ return -1;
36146+ }
36147+set_buf:
36148+
36149+ mbuf_size = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(pool);
36150+
36151+ for (i = 0; i < n; i++ ) {
36152+
36153+ DPAA2_MODIFY_IOVA_TO_VADDR(buf[i], uint64_t);
36154+
36155+ mt[i] = (struct rte_mbuf *)(bufs[i] - mbuf_size);
36156+ PMD_DRV_LOG(DEBUG,"Acquired %p address %p from BMAN\n", (void *)bufs[i], (void *)mt[i]);
36157+ if (!bufs[i] || !mt[i]) {
36158+ printf("\n ??????? how come we have a null buffer %p, %p",
36159+ (void *)bufs[i], (void *)mt[i]);
36160+ }
36161+ }
36162+
36163+ alloc +=n;
36164+ PMD_DRV_LOG(DEBUG, "Total = %d , req = %d done = %d",
36165+ alloc, count, n);
36166+ return 0;
36167+}
36168+
36169+int hw_mbuf_free_bulk(struct rte_mempool *pool, void * const *obj_table,
36170+ unsigned n)
36171+{
36172+ unsigned i;
36173+ struct rte_mbuf *m;
36174+ //PMD_DRV_LOG(INFO, "%s/n", __func__);
36175+ if ((pool->offload_ptr > MAX_BPID) ||
36176+ !(bpid_info[pool->offload_ptr].bp_list)) {
36177+
36178+ PMD_DRV_LOG(INFO, "DPAA2 buffer pool not configured\n");
36179+ return -1;
36180+ }
36181+ for (i = 0; i < n; i++) {
36182+ m = (struct rte_mbuf *)(obj_table[i]);
36183+ dpaa2_mbuf_release((uint64_t)m->buf_addr, pool->offload_ptr);
36184+ }
36185+
36186+ return 0;
36187+}
36188+
36189+int hw_mbuf_init(
36190+ struct rte_mempool *mp,
36191+ void *_m)
36192+{
36193+ struct rte_mbuf *m = (struct rte_mbuf *)((unsigned char *)_m + DPAA2_FD_PTA_SIZE +
36194+ DPAA2_MBUF_HW_ANNOTATION + DPAA2_RES);
36195+ uint32_t mbuf_size, buf_len, priv_size, head_size;
36196+ uint32_t bpid;
36197+
36198+ if ((mp->offload_ptr > MAX_BPID) ||
36199+ !(bpid_info[mp->offload_ptr].bp_list)) {
36200+
36201+ PMD_DRV_LOG(WARNING, "DPAA2 buffer pool not configured\n");
36202+ return -1;
36203+ }
36204+ /*todo - assuming that h_bp_list will be at top node*/
36205+ bpid = mp->offload_ptr;
36206+
36207+ priv_size = rte_pktmbuf_priv_size(mp);
36208+ mbuf_size = sizeof(struct rte_mbuf) + priv_size;
36209+
36210+ RTE_MBUF_ASSERT(RTE_ALIGN(priv_size, RTE_MBUF_PRIV_ALIGN) == priv_size);
36211+ RTE_MBUF_ASSERT(mp->elt_size >= mbuf_size);
36212+
36213+ memset(_m, 0, mp->elt_size);
36214+
36215+ /*update it in global list as well */
36216+ bpid_info[bpid].meta_data_size = DPAA2_RES;
36217+
36218+/* head_size = DPAA2_FD_PTA_SIZE + DPAA2_MBUF_HW_ANNOTATION
36219+ + RTE_PKTMBUF_HEADROOM;
36220+ head_size = DPAA2_ALIGN_ROUNDUP(head_size,
36221+ DPAA2_PACKET_LAYOUT_ALIGN);
36222+ head_size -= DPAA2_FD_PTA_SIZE + DPAA2_MBUF_HW_ANNOTATION;
36223+*/
36224+ head_size = RTE_PKTMBUF_HEADROOM;
36225+
36226+ buf_len = rte_pktmbuf_data_room_size(mp)
36227+ - (DPAA2_FD_PTA_SIZE + DPAA2_MBUF_HW_ANNOTATION + DPAA2_RES /* dummy */);
36228+
36229+ RTE_MBUF_ASSERT(buf_len <= UINT16_MAX);
36230+
36231+ /* start of buffer is after mbuf structure and priv data */
36232+ m->priv_size = priv_size;
36233+ m->buf_addr = (char *)m + mbuf_size ;
36234+ m->buf_physaddr = rte_mempool_virt2phy(mp, _m) + DPAA2_FD_PTA_SIZE +
36235+ DPAA2_MBUF_HW_ANNOTATION + DPAA2_RES + mbuf_size;
36236+ m->buf_len = (uint16_t)buf_len;
36237+
36238+ /* keep some headroom between start of buffer and data */
36239+ m->data_off = RTE_MIN(head_size, (uint16_t)m->buf_len);
36240+ /* init some constant fields */
36241+ m->pool = mp;
36242+ m->nb_segs = 1;
36243+ m->port = 0xff;
36244+
36245+ /* Release the mempool buffer to BMAN */
36246+ dpaa2_mbuf_release((uint64_t)_m, bpid);
36247+ return 0;
36248+}
36249+
36250diff --git a/drivers/net/dpaa2/rte_eth_dpio.c b/drivers/net/dpaa2/rte_eth_dpio.c
36251new file mode 100644
36252index 0000000..23f0b08
36253--- /dev/null
36254+++ b/drivers/net/dpaa2/rte_eth_dpio.c
36255@@ -0,0 +1,339 @@
36256+/*-
36257+ * BSD LICENSE
36258+ *
36259+ * Copyright(c) 2014 Freescale Semiconductor. All rights reserved.
36260+ * All rights reserved.
36261+ *
36262+ * Redistribution and use in source and binary forms, with or without
36263+ * modification, are permitted provided that the following conditions
36264+ * are met:
36265+ *
36266+ * * Redistributions of source code must retain the above copyright
36267+ * notice, this list of conditions and the following disclaimer.
36268+ * * Redistributions in binary form must reproduce the above copyright
36269+ * notice, this list of conditions and the following disclaimer in
36270+ * the documentation and/or other materials provided with the
36271+ * distribution.
36272+ * * Neither the name of Freescale Semiconductor nor the names of its
36273+ * contributors may be used to endorse or promote products derived
36274+ * from this software without specific prior written permission.
36275+ *
36276+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36277+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36278+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36279+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
36280+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36281+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36282+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36283+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36284+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36285+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36286+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36287+ */
36288+
36289+#include <unistd.h>
36290+#include <stdio.h>
36291+#include <sys/types.h>
36292+#include <string.h>
36293+#include <stdlib.h>
36294+#include <fcntl.h>
36295+#include <errno.h>
36296+#include <sys/ioctl.h>
36297+#include <sys/stat.h>
36298+#include <sys/types.h>
36299+#include <sys/mman.h>
36300+#include <sys/vfs.h>
36301+#include <libgen.h>
36302+
36303+#include "rte_pci.h"
36304+#include "rte_memzone.h"
36305+#include <rte_malloc.h>
36306+
36307+#include "rte_eth_dpaa2_pvt.h"
36308+#include "fsl_qbman_portal.h"
36309+#include <fsl_dpio.h>
36310+
36311+#include <rte_log.h>
36312+#include "dpaa2_logs.h"
36313+
36314+#define NUM_HOST_CPUS RTE_MAX_LCORE
36315+
36316+__thread struct thread_io_info_t thread_io_info;
36317+
36318+TAILQ_HEAD(dpio_device_list, dpaa2_dpio_dev);
36319+static struct dpio_device_list *dpio_dev_list; /*!< DPIO device list */
36320+static uint32_t io_space_count;
36321+
36322+/*Stashing Macros*/
36323+#define DPAA2_CORE_CLUSTER_BASE 0x04
36324+#define DPAA2_CORE_CLUSTER_FIRST (DPAA2_CORE_CLUSTER_BASE + 0)
36325+#define DPAA2_CORE_CLUSTER_SECOND (DPAA2_CORE_CLUSTER_BASE + 1)
36326+#define DPAA2_CORE_CLUSTER_THIRD (DPAA2_CORE_CLUSTER_BASE + 2)
36327+#define DPAA2_CORE_CLUSTER_FOURTH (DPAA2_CORE_CLUSTER_BASE + 3)
36328+
36329+#define DPAA2_CORE_CLUSTER_GET(sdest, cpu_id) \
36330+do { \
36331+ if (cpu_id == 0 || cpu_id == 1) \
36332+ sdest = DPAA2_CORE_CLUSTER_FIRST; \
36333+ else if (cpu_id == 2 || cpu_id == 3) \
36334+ sdest = DPAA2_CORE_CLUSTER_SECOND; \
36335+ else if (cpu_id == 4 || cpu_id == 5) \
36336+ sdest = DPAA2_CORE_CLUSTER_THIRD; \
36337+ else \
36338+ sdest = DPAA2_CORE_CLUSTER_FOURTH; \
36339+} while (0)
36340+
36341+static int
36342+configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
36343+{
36344+ struct qbman_swp_desc p_des;
36345+ struct dpio_attr attr;
36346+
36347+ dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));
36348+ if (!dpio_dev->dpio) {
36349+ PMD_DRV_LOG(ERR, "Memory allocation failure\n");
36350+ return -1;
36351+ }
36352+
36353+ PMD_DRV_LOG(INFO, "\t Alocated DPIO[%p]\n", dpio_dev->dpio);
36354+ dpio_dev->dpio->regs = dpio_dev->mc_portal;
36355+ if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
36356+ &dpio_dev->token)) {
36357+ PMD_DRV_LOG(ERR, "Failed to allocate IO space\n");
36358+ free(dpio_dev->dpio);
36359+ return -1;
36360+ }
36361+
36362+ if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
36363+ PMD_DRV_LOG(ERR, "Failed to Enable dpio\n");
36364+ dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
36365+ free(dpio_dev->dpio);
36366+ return -1;
36367+ }
36368+
36369+ if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
36370+ dpio_dev->token, &attr)) {
36371+ PMD_DRV_LOG(ERR, "DPIO Get attribute failed\n");
36372+ dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
36373+ dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
36374+ free(dpio_dev->dpio);
36375+ return -1;
36376+ }
36377+
36378+ PMD_DRV_LOG(INFO, "Qbman Portal ID %d\n", attr.qbman_portal_id);
36379+ PMD_DRV_LOG(INFO, "Portal CE addr 0x%lX\n", attr.qbman_portal_ce_offset);
36380+ PMD_DRV_LOG(INFO, "Portal CI addr 0x%lX\n", attr.qbman_portal_ci_offset);
36381+
36382+ /* Configure & setup SW portal */
36383+ p_des.block = NULL;
36384+ p_des.idx = attr.qbman_portal_id;
36385+ p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
36386+ p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
36387+ p_des.irq = -1;
36388+ p_des.qman_version = attr.qbman_version;
36389+
36390+ PMD_DRV_LOG(INFO, "Portal CE addr 0x%p\n", p_des.cena_bar);
36391+ PMD_DRV_LOG(INFO, "Portal CI addr 0x%p\n", p_des.cinh_bar);
36392+
36393+ dpio_dev->sw_portal = qbman_swp_init(&p_des);
36394+ if (dpio_dev->sw_portal == NULL) {
36395+ PMD_DRV_LOG(ERR, " QBMan SW Portal Init failed\n");
36396+ dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
36397+ free(dpio_dev->dpio);
36398+ return -1;
36399+ }
36400+
36401+ PMD_DRV_LOG(INFO, "QBMan SW Portal 0x%p\n", dpio_dev->sw_portal);
36402+
36403+ return 0;
36404+}
36405+
36406+int dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev)
36407+{
36408+ int sdest;
36409+ int cpu_id, ret;
36410+
36411+ /* Set the Stashing Destination */
36412+ cpu_id = rte_lcore_id();
36413+ if (cpu_id < 0) {
36414+ cpu_id = rte_get_master_lcore();
36415+ if (cpu_id < 0) {
36416+ PMD_DRV_LOG(ERR, "\tGetting CPU Index failed\n");
36417+ return -1;
36418+ }
36419+ }
36420+
36421+ /*
36422+ * In case of running DPDK on the Virtual Machine the Stashing
36423+ * Destination gets set in the H/W w.r.t. the Virtual CPU ID's.
36424+ * As a W.A. environment variable HOST_START_CPU tells which
36425+ * the offset of the host start core of the Virtual Machine threads.
36426+ */
36427+ if (getenv("HOST_START_CPU")) {
36428+ cpu_id +=
36429+ atoi(getenv("HOST_START_CPU"));
36430+ cpu_id = cpu_id % NUM_HOST_CPUS;
36431+ }
36432+
36433+ /* Set the STASH Destination depending on Current CPU ID.
36434+ Valid values of SDEST are 4,5,6,7. Where,
36435+ CPU 0-1 will have SDEST 4
36436+ CPU 2-3 will have SDEST 5.....and so on.
36437+ */
36438+ DPAA2_CORE_CLUSTER_GET(sdest, cpu_id);
36439+ PMD_DRV_LOG(INFO, "Portal= %d CPU= %u SDEST= %d\n",
36440+ dpio_dev->index, cpu_id, sdest);
36441+
36442+ ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
36443+ dpio_dev->token, sdest);
36444+ if (ret) {
36445+ PMD_DRV_LOG(ERR, "%d ERROR in SDEST\n", ret);
36446+ return -1;
36447+ }
36448+
36449+ return 0;
36450+}
36451+
36452+int
36453+dpaa2_affine_qbman_swp(void)
36454+{
36455+ struct dpaa2_dpio_dev *dpio_dev = NULL;
36456+ int ret;
36457+
36458+ if (thread_io_info.dpio_dev)
36459+ return 0;
36460+
36461+ /* Get DPIO dev handle from list using index */
36462+ TAILQ_FOREACH(dpio_dev, dpio_dev_list, next) {
36463+ if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
36464+ break;
36465+ }
36466+ if (!dpio_dev)
36467+ return -1;
36468+
36469+ /* Populate the thread_io_info structure */
36470+ thread_io_info.dpio_dev = dpio_dev;
36471+
36472+ ret = dpaa2_configure_stashing(dpio_dev);
36473+ if (ret) {
36474+ RTE_LOG(ERR, EAL, "dpaa2_configure_stashing failed");
36475+ }
36476+ return ret;
36477+}
36478+
36479+int
36480+dpaa2_affine_qbman_swp_sec(void)
36481+{
36482+ struct dpaa2_dpio_dev *dpio_dev = NULL;
36483+ int ret;
36484+
36485+ if (thread_io_info.sec_dpio_dev)
36486+ return 0;
36487+
36488+ /* Get DPIO dev handle from list using index */
36489+ TAILQ_FOREACH(dpio_dev, dpio_dev_list, next) {
36490+ if (dpio_dev && rte_atomic16_read(&dpio_dev->ref_count) == 0) {
36491+ rte_atomic16_inc(&dpio_dev->ref_count);
36492+ break;
36493+ }
36494+ }
36495+ if (!dpio_dev)
36496+ return -1;
36497+
36498+ /* Populate the thread_io_info structure */
36499+ thread_io_info.sec_dpio_dev = dpio_dev;
36500+
36501+ ret = dpaa2_configure_stashing(dpio_dev);
36502+ if (ret) {
36503+ RTE_LOG(ERR, EAL, "dpaa2_configure_stashing failed");
36504+ }
36505+ return ret;
36506+}
36507+
36508+int
36509+dpaa2_create_dpio_device(struct vfio_device *vdev,
36510+ struct vfio_device_info *obj_info,
36511+ int object_id)
36512+{
36513+ struct dpaa2_dpio_dev *dpio_dev;
36514+ struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
36515+
36516+ if (obj_info->num_regions < NUM_DPIO_REGIONS) {
36517+ PMD_DRV_LOG(ERR, "ERROR, Not sufficient number "
36518+ "of DPIO regions.\n");
36519+ return -1;
36520+ }
36521+
36522+ if (!dpio_dev_list) {
36523+ dpio_dev_list = malloc(sizeof(struct dpio_device_list));
36524+ if (NULL == dpio_dev_list) {
36525+ PMD_DRV_LOG(ERR, "Memory allocation failed for DPIO list\n");
36526+ return -1;
36527+ }
36528+
36529+ /* Initialize the DPIO List */
36530+ TAILQ_INIT(dpio_dev_list);
36531+ }
36532+
36533+ dpio_dev = malloc(sizeof(struct dpaa2_dpio_dev));
36534+ if (!dpio_dev) {
36535+ PMD_DRV_LOG(ERR, "Memory allocation failed for DPIO Device\n");
36536+ return -1;
36537+ }
36538+
36539+ PMD_DRV_LOG(INFO, "\t Aloocated DPIO [%p]\n", dpio_dev);
36540+ dpio_dev->dpio = NULL;
36541+ dpio_dev->hw_id = object_id;
36542+ dpio_dev->vfio_fd = vdev->fd;
36543+ rte_atomic16_init(&dpio_dev->ref_count);
36544+ /* Using single portal for all devices */
36545+ dpio_dev->mc_portal = mcp_ptr_list[MC_PORTAL_INDEX];
36546+
36547+ reg_info.index = 0;
36548+ if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, &reg_info)) {
36549+ printf("vfio: error getting region info\n");
36550+ return -1;
36551+ }
36552+
36553+ PMD_DRV_LOG(INFO, "\t Region Offset = %llx\n", reg_info.offset);
36554+ PMD_DRV_LOG(INFO, "\t Region Size = %llx\n", reg_info.size);
36555+ dpio_dev->ce_size = reg_info.size;
36556+ dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
36557+ PROT_WRITE | PROT_READ, MAP_SHARED,
36558+ dpio_dev->vfio_fd, reg_info.offset);
36559+
36560+ /* Create Mapping for QBMan Cache Enabled area. This is a fix for
36561+ SMMU fault for DQRR statshing transaction. */
36562+ if (vfio_dmamap_mem_region(dpio_dev->qbman_portal_ce_paddr,
36563+ reg_info.offset, reg_info.size)) {
36564+ PMD_DRV_LOG(ERR, "DMAMAP for Portal CE area failed.\n");
36565+ return -1;
36566+ }
36567+
36568+ reg_info.index = 1;
36569+ if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, &reg_info)) {
36570+ printf("vfio: error getting region info\n");
36571+ return -1;
36572+ }
36573+
36574+ PMD_DRV_LOG(INFO, "\t Region Offset = %llx\n", reg_info.offset);
36575+ PMD_DRV_LOG(INFO, "\t Region Size = %llx\n", reg_info.size);
36576+ dpio_dev->ci_size = reg_info.size;
36577+ dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
36578+ PROT_WRITE | PROT_READ, MAP_SHARED,
36579+ dpio_dev->vfio_fd, reg_info.offset);
36580+
36581+ if (configure_dpio_qbman_swp(dpio_dev)) {
36582+ PMD_DRV_LOG(ERR,
36583+ "Failed in configuring the qbman portal for dpio %d\n",
36584+ dpio_dev->hw_id);
36585+ return -1;
36586+ }
36587+
36588+ io_space_count++;
36589+ dpio_dev->index = io_space_count;
36590+ TAILQ_INSERT_HEAD(dpio_dev_list, dpio_dev, next);
36591+
36592+ return 0;
36593+}
36594+
36595diff --git a/drivers/net/dpaa2/rte_eth_dpni.c b/drivers/net/dpaa2/rte_eth_dpni.c
36596new file mode 100644
36597index 0000000..62baf03
36598--- /dev/null
36599+++ b/drivers/net/dpaa2/rte_eth_dpni.c
36600@@ -0,0 +1,2230 @@
36601+/*-
36602+ * BSD LICENSE
36603+ *
36604+ * Copyright (c) 2014 Freescale Semiconductor, Inc. All rights reserved.
36605+ *
36606+ * Redistribution and use in source and binary forms, with or without
36607+ * modification, are permitted provided that the following conditions
36608+ * are met:
36609+ *
36610+ * * Redistributions of source code must retain the above copyright
36611+ * notice, this list of conditions and the following disclaimer.
36612+ * * Redistributions in binary form must reproduce the above copyright
36613+ * notice, this list of conditions and the following disclaimer in
36614+ * the documentation and/or other materials provided with the
36615+ * distribution.
36616+ * * Neither the name of Freescale Semiconductor, Inc nor the names of its
36617+ * contributors may be used to endorse or promote products derived
36618+ * from this software without specific prior written permission.
36619+ *
36620+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36621+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36622+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36623+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
36624+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36625+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36626+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36627+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36628+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36629+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36630+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36631+ */
36632+
36633+#include <time.h>
36634+#include <rte_mbuf.h>
36635+#include <rte_ethdev.h>
36636+#include <rte_malloc.h>
36637+#include <rte_memcpy.h>
36638+#include <rte_string_fns.h>
36639+#include <rte_cycles.h>
36640+#include <rte_kvargs.h>
36641+#include <rte_dev.h>
36642+
36643+#include <net/if.h>
36644+/* MC header files */
36645+#include <fsl_dpbp.h>
36646+#include <fsl_dpni.h>
36647+#include "rte_eth_dpaa2_pvt.h"
36648+#include "rte_eth_dpni_annot.h"
36649+#include "dpaa2_logs.h"
36650+
36651+#include <fsl_qbman_portal.h>
36652+#include <fsl_dpio.h>
36653+
36654+#define DPAA2_STASHING
36655+
36656+/* tx fd send batching */
36657+#define QBMAN_MULTI_TX
36658+
36659+#define RTE_ETH_DPAA2_SNAPSHOT_LEN 65535
36660+#define RTE_ETH_DPAA2_SNAPLEN 4096
36661+#define RTE_ETH_DPAA2_PROMISC 1
36662+#define RTE_ETH_DPAA2_TIMEOUT -1
36663+#define ETH_DPAA2_RX_IFACE_ARG "rx_iface"
36664+#define ETH_DPAA2_TX_IFACE_ARG "tx_iface"
36665+#define ETH_DPAA2_IFACE_ARG "iface"
36666+
36667+static const char *drivername = "DPNI PMD";
36668+
36669+#define MAX_TCS DPNI_MAX_TC
36670+#define MAX_RX_QUEUES 64
36671+#define MAX_TX_QUEUES 64
36672+
36673+/*Maximum number of slots available in TX ring*/
36674+#define MAX_SLOTS 8
36675+
36676+/*Threshold for a queue to *Enter* Congestion state.
36677+ It is set to 128 frames of size 64 bytes.*/
36678+#define CONG_ENTER_THRESHOLD 128*64
36679+
36680+/*Threshold for a queue to *Exit* Congestion state.
36681+ It is set to 98 frames of size 64 bytes*/
36682+#define CONG_EXIT_THRESHOLD 98*64
36683+
36684+/*! Maximum number of flow distributions per traffic class */
36685+#define MAX_DIST_PER_TC 16
36686+
36687+/* Size of the input SMMU mapped memory required by MC */
36688+#define DIST_PARAM_IOVA_SIZE 256
36689+
36690+struct dpaa2_queue {
36691+ void *dev;
36692+ int32_t eventfd; /*!< Event Fd of this queue */
36693+ uint32_t fqid; /*!< Unique ID of this queue */
36694+ uint8_t tc_index; /*!< traffic class identifier */
36695+ uint16_t flow_id; /*!< To be used by DPAA2 frmework */
36696+ uint64_t rx_pkts;
36697+ uint64_t tx_pkts;
36698+ uint64_t err_pkts;
36699+ union {
36700+ struct queue_storage_info_t *q_storage;
36701+ struct qbman_result *cscn;
36702+ };
36703+};
36704+
36705+struct dpaa2_dev_priv {
36706+ void *hw;
36707+ int32_t hw_id;
36708+ int32_t qdid;
36709+ uint16_t token;
36710+ uint8_t nb_tx_queues;
36711+ uint8_t nb_rx_queues;
36712+ void *rx_vq[MAX_RX_QUEUES];
36713+ void *tx_vq[MAX_TX_QUEUES];
36714+
36715+ struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
36716+ uint16_t num_dist_per_tc[MAX_TCS];
36717+
36718+ uint8_t max_unicast_filters;
36719+ uint8_t max_multicast_filters;
36720+ uint8_t max_vlan_filters;
36721+ uint8_t num_tc;
36722+ uint32_t options;
36723+};
36724+
36725+static struct rte_pci_id pci_id_dpaa2_map[] = {
36726+ {RTE_PCI_DEVICE(FSL_VENDOR_ID, FSL_MC_DPNI_DEVID)},
36727+};
36728+
36729+extern struct bp_info bpid_info[MAX_BPID];
36730+
36731+static void dpaa2_print_stats(struct rte_eth_dev *dev)
36732+{
36733+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
36734+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
36735+ uint64_t value;
36736+
36737+ dpni_get_counter(dpni, CMD_PRI_LOW, priv->token, DPNI_CNT_ING_FRAME, &value);
36738+ printf("Rx packets: %ld\n", value);
36739+ dpni_get_counter(dpni, CMD_PRI_LOW, priv->token, DPNI_CNT_ING_BYTE, &value);
36740+ printf("Rx bytes: %ld\n", value);
36741+ dpni_get_counter(dpni, CMD_PRI_LOW, priv->token, DPNI_CNT_ING_MCAST_FRAME, &value);
36742+ printf("Rx Multicast: %ld\n", value);
36743+ dpni_get_counter(dpni, CMD_PRI_LOW, priv->token, DPNI_CNT_ING_FRAME_DROP, &value);
36744+ printf("Rx dropped: %ld\n", value);
36745+ dpni_get_counter(dpni, CMD_PRI_LOW, priv->token, DPNI_CNT_ING_FRAME_DISCARD, &value);
36746+ printf("Rx discarded: %ld\n", value);
36747+ dpni_get_counter(dpni, CMD_PRI_LOW, priv->token, DPNI_CNT_EGR_FRAME, &value);
36748+ printf("Tx packets: %ld\n", value);
36749+ dpni_get_counter(dpni, CMD_PRI_LOW, priv->token, DPNI_CNT_EGR_BYTE, &value);
36750+ printf("Tx bytes: %ld\n", value);
36751+ dpni_get_counter(dpni, CMD_PRI_LOW, priv->token, DPNI_CNT_EGR_FRAME_DISCARD, &value);
36752+ printf("Tx dropped: %ld\n", value);
36753+}
36754+
36755+/**
36756+ * Atomically reads the link status information from global
36757+ * structure rte_eth_dev.
36758+ *
36759+ * @param dev
36760+ * - Pointer to the structure rte_eth_dev to read from.
36761+ * - Pointer to the buffer to be saved with the link status.
36762+ *
36763+ * @return
36764+ * - On success, zero.
36765+ * - On failure, negative value.
36766+ */
36767+static inline int
36768+rte_dpni_dev_atomic_read_link_status(struct rte_eth_dev *dev,
36769+ struct rte_eth_link *link)
36770+{
36771+ struct rte_eth_link *dst = link;
36772+ struct rte_eth_link *src = &dev->data->dev_link;
36773+
36774+ if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
36775+ *(uint64_t *)src) == 0)
36776+ return -1;
36777+
36778+ return 0;
36779+}
36780+
36781+/**
36782+ * Atomically writes the link status information into global
36783+ * structure rte_eth_dev.
36784+ *
36785+ * @param dev
36786+ * - Pointer to the structure rte_eth_dev to read from.
36787+ * - Pointer to the buffer to be saved with the link status.
36788+ *
36789+ * @return
36790+ * - On success, zero.
36791+ * - On failure, negative value.
36792+ */
36793+static inline int
36794+rte_dpni_dev_atomic_write_link_status(struct rte_eth_dev *dev,
36795+ struct rte_eth_link *link)
36796+{
36797+ struct rte_eth_link *dst = &dev->data->dev_link;
36798+ struct rte_eth_link *src = link;
36799+
36800+ if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
36801+ *(uint64_t *)src) == 0)
36802+ return -1;
36803+
36804+ return 0;
36805+}
36806+
36807+static inline void
36808+dpaa2_eth_parse_packet(struct rte_mbuf *mbuf)
36809+{
36810+ uint32_t pkt_type = 0;
36811+ struct pkt_annotation *annotation = (struct pkt_annotation *)
36812+ ((uint8_t *)mbuf - (DPAA2_MBUF_HW_ANNOTATION + DPAA2_RES));
36813+
36814+ PMD_DRV_LOG(DEBUG, "\n 1 annotation = 0x%x ", annotation->word4);
36815+
36816+ if (BIT_ISSET_AT_POS(annotation->word3, L2_ETH_MAC_PRESENT))
36817+ pkt_type/* mbuf->packet_type */ |= RTE_PTYPE_L2_ETHER;
36818+
36819+ if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV4_1_PRESENT))
36820+ pkt_type/* mbuf->packet_type */ |= RTE_PTYPE_L3_IPV4;
36821+
36822+ if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV6_1_PRESENT))
36823+ pkt_type /* mbuf->packet_type */ |= RTE_PTYPE_L3_IPV6;
36824+
36825+ if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT))
36826+ pkt_type/* mbuf->packet_type */ |= RTE_PTYPE_L3_IPV4_EXT;
36827+
36828+ if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_UDP_PRESENT))
36829+ pkt_type/* mbuf->packet_type */ |= RTE_PTYPE_L4_UDP;
36830+
36831+ if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_TCP_PRESENT))
36832+ pkt_type/* mbuf->packet_type */ |= RTE_PTYPE_L4_TCP;
36833+
36834+ if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_SCTP_PRESENT))
36835+ pkt_type/* mbuf->packet_type */ |= RTE_PTYPE_L4_SCTP;
36836+
36837+ if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_ICMP_PRESENT))
36838+ pkt_type/* mbuf->packet_type */ |= RTE_PTYPE_L4_ICMP;
36839+
36840+ if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_UNKNOWN_PROTOCOL))
36841+ pkt_type/* mbuf->packet_type */ |= RTE_PTYPE_UNKNOWN;
36842+
36843+ mbuf->packet_type = pkt_type;
36844+}
36845+
36846+static inline
36847+struct rte_mbuf *eth_fd_to_mbuf(const struct qbman_fd *fd)
36848+{
36849+ struct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF(DPAA2_GET_FD_ADDR(fd));
36850+
36851+ PMD_DRV_LOG(DEBUG, "\nmbuf %p BMAN buf addr %p",
36852+ (void *)mbuf, mbuf->buf_addr);
36853+
36854+ PMD_DRV_LOG(DEBUG, "\nfdaddr =%lx bpid =%d meta =%d off =%d, len =%d\n",
36855+ DPAA2_GET_FD_ADDR(fd),
36856+ DPAA2_GET_FD_BPID(fd),
36857+ bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
36858+ DPAA2_GET_FD_OFFSET(fd),
36859+ DPAA2_GET_FD_LEN(fd));
36860+
36861+// mbuf->data_off = DPAA2_GET_FD_OFFSET(fd);
36862+ mbuf->data_len = DPAA2_GET_FD_LEN(fd);
36863+ mbuf->pkt_len = mbuf->data_len;
36864+ mbuf->next = NULL;
36865+ rte_mbuf_refcnt_set(mbuf, 1);
36866+
36867+ /* Parse the packet */
36868+ dpaa2_eth_parse_packet(mbuf);
36869+
36870+ mbuf->nb_segs = 1;
36871+ mbuf->ol_flags = 0;
36872+
36873+ return mbuf;
36874+}
36875+
36876+static void __attribute__ ((noinline)) eth_mbuf_to_fd(struct rte_mbuf *mbuf,
36877+ struct qbman_fd *fd, uint16_t bpid)
36878+{
36879+ /*Resetting the buffer pool id and offset field*/
36880+ fd->simple.bpid_offset = 0;
36881+
36882+ DPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(DPAA2_BUF_FROM_INLINE_MBUF(mbuf)));
36883+ DPAA2_SET_FD_LEN(fd, mbuf->data_len);
36884+ DPAA2_SET_FD_BPID(fd, bpid);
36885+ DPAA2_SET_FD_OFFSET(fd, DPAA2_FD_PTA_SIZE + DPAA2_MBUF_HW_ANNOTATION +
36886+ DPAA2_RES /* dummy */+ 128 + mbuf->priv_size + mbuf->data_off);
36887+ DPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL);
36888+
36889+ PMD_DRV_LOG(DEBUG, "\nmbuf %p BMAN buf addr %p",
36890+ (void *)mbuf, mbuf->buf_addr);
36891+
36892+ PMD_DRV_LOG(DEBUG, "\nfdaddr =%lx bpid =%d meta =%d off =%d, len =%d\n",
36893+ DPAA2_GET_FD_ADDR(fd),
36894+ DPAA2_GET_FD_BPID(fd),
36895+ bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
36896+ DPAA2_GET_FD_OFFSET(fd),
36897+ DPAA2_GET_FD_LEN(fd));
36898+
36899+ return;
36900+}
36901+
36902+static int eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf,
36903+ struct qbman_fd *fd, uint16_t bpid)
36904+{
36905+ struct rte_mbuf *m;
36906+ void *mb = NULL;
36907+
36908+ if (hw_mbuf_alloc(bpid_info[bpid].bp_list->buf_pool.mp, &mb)) {
36909+ PMD_DRV_LOG(WARNING, "Unable to allocated DPAA2 buffer");
36910+ rte_pktmbuf_free(mbuf);
36911+ return -1;
36912+ }
36913+ m = (struct rte_mbuf *)mb;
36914+ memcpy((char *)m->buf_addr + mbuf->data_off,
36915+ (void *)((char *)mbuf->buf_addr + mbuf->data_off),
36916+ mbuf->pkt_len);
36917+
36918+ /*Resetting the buffer pool id and offset field*/
36919+ fd->simple.bpid_offset = 0;
36920+
36921+ DPAA2_SET_FD_ADDR(fd, m->buf_addr);
36922+ DPAA2_SET_FD_LEN(fd, mbuf->data_len);
36923+ DPAA2_SET_FD_BPID(fd, bpid);
36924+ DPAA2_SET_FD_OFFSET(fd, mbuf->data_off);
36925+ DPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL);
36926+
36927+ PMD_DRV_LOG(DEBUG, "\nmbuf %p BMAN buf addr %p",
36928+ (void *)mbuf, mbuf->buf_addr);
36929+
36930+ PMD_DRV_LOG(DEBUG, "\nfdaddr =%lx bpid =%d meta =%d off =%d, len =%d\n",
36931+ DPAA2_GET_FD_ADDR(fd),
36932+ DPAA2_GET_FD_BPID(fd),
36933+ bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
36934+ DPAA2_GET_FD_OFFSET(fd),
36935+ DPAA2_GET_FD_LEN(fd));
36936+ /*free the original packet */
36937+ rte_pktmbuf_free(mbuf);
36938+
36939+ return 0;
36940+}
36941+
36942+static uint16_t
36943+eth_dpaa2_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
36944+{
36945+ /* Function is responsible to receive frames for a given device and VQ*/
36946+ struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
36947+ struct qbman_result *dq_storage;
36948+ uint32_t fqid = dpaa2_q->fqid;
36949+ int ret, num_rx = 0;
36950+ uint8_t is_last = 0, status;
36951+ struct qbman_swp *swp;
36952+ const struct qbman_fd *fd;
36953+ struct qbman_pull_desc pulldesc;
36954+ struct rte_eth_dev *dev = dpaa2_q->dev;
36955+
36956+ if (!thread_io_info.dpio_dev) {
36957+ ret = dpaa2_affine_qbman_swp();
36958+ if (ret) {
36959+ PMD_DRV_LOG(ERR, "Failure in affining portal\n");
36960+ return 0;
36961+ }
36962+ }
36963+ swp = thread_io_info.dpio_dev->sw_portal;
36964+ dq_storage = dpaa2_q->q_storage->dq_storage[0];
36965+
36966+ qbman_pull_desc_clear(&pulldesc);
36967+ qbman_pull_desc_set_numframes(&pulldesc, nb_pkts);
36968+ qbman_pull_desc_set_fq(&pulldesc, fqid);
36969+ /* todo optimization - we can have dq_storage_phys available*/
36970+ qbman_pull_desc_set_storage(&pulldesc, dq_storage,
36971+ (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
36972+
36973+ /*Issue a volatile dequeue command. */
36974+ while (1) {
36975+ if (qbman_swp_pull(swp, &pulldesc)) {
36976+ PMD_DRV_LOG(ERR, "VDQ command is not issued."
36977+ "QBMAN is busy\n");
36978+ /* Portal was busy, try again */
36979+ continue;
36980+ }
36981+ break;
36982+ };
36983+
36984+ /* Receive the packets till Last Dequeue entry is found with
36985+ respect to the above issues PULL command.
36986+ */
36987+ while (!is_last) {
36988+ /*Check if the previous issued command is completed.
36989+ *Also seems like the SWP is shared between the Ethernet Driver
36990+ *and the SEC driver.*/
36991+ while(!qbman_check_command_complete(swp, dq_storage))
36992+ ;
36993+ /* Loop until the dq_storage is updated with
36994+ * new token by QBMAN */
36995+ while (!qbman_result_has_new_result(swp, dq_storage))
36996+ ;
36997+ /* Check whether Last Pull command is Expired and
36998+ setting Condition for Loop termination */
36999+ if (qbman_result_DQ_is_pull_complete(dq_storage)) {
37000+ is_last = 1;
37001+ /* Check for valid frame. */
37002+ status = (uint8_t)qbman_result_DQ_flags(dq_storage);
37003+ if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0)) {
37004+ PMD_DRV_LOG(DEBUG, "No frame is delivered\n");
37005+ continue;
37006+ }
37007+ }
37008+
37009+ fd = qbman_result_DQ_fd(dq_storage);
37010+ bufs[num_rx] = eth_fd_to_mbuf(fd);
37011+ bufs[num_rx]->port = dev->data->port_id;
37012+
37013+ num_rx++;
37014+ dq_storage++;
37015+ } /* End of Packet Rx loop */
37016+
37017+ dpaa2_q->rx_pkts += num_rx;
37018+
37019+ PMD_DRV_LOG(INFO, "Ethernet Received %d Packets\n", num_rx);
37020+ /*Return the total number of packets received to DPAA2 app*/
37021+ return num_rx;
37022+}
37023+
37024+static uint16_t
37025+eth_dpaa2_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
37026+{
37027+ /* Function is responsible to receive frames for a given device and VQ*/
37028+ struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
37029+ struct qbman_result *dq_storage;
37030+ uint32_t fqid = dpaa2_q->fqid;
37031+ int ret, i, num_rx = 0;
37032+ uint8_t is_last = 0, status;
37033+ struct qbman_swp *swp;
37034+ const struct qbman_fd *fd[16];
37035+ struct qbman_pull_desc pulldesc;
37036+ struct queue_storage_info_t *q_storage = dpaa2_q->q_storage;
37037+ struct rte_eth_dev *dev = dpaa2_q->dev;
37038+
37039+ if(!thread_io_info.dpio_dev) {
37040+ ret = dpaa2_affine_qbman_swp();
37041+ if (ret) {
37042+ PMD_DRV_LOG(ERR, "Failure in affining portal\n");
37043+ return 0;
37044+ }
37045+ }
37046+ swp = thread_io_info.dpio_dev->sw_portal;
37047+
37048+ if(!q_storage->active_dqs) {
37049+ q_storage->toggle = 0;
37050+ dq_storage = q_storage->dq_storage[q_storage->toggle];
37051+ qbman_pull_desc_clear(&pulldesc);
37052+ qbman_pull_desc_set_numframes(&pulldesc, nb_pkts);
37053+ qbman_pull_desc_set_fq(&pulldesc, fqid);
37054+ qbman_pull_desc_set_storage(&pulldesc, dq_storage,
37055+ (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
37056+ if(thread_io_info.global_active_dqs) {
37057+ while(!qbman_check_command_complete(swp, thread_io_info.global_active_dqs))
37058+ ;
37059+ }
37060+ while (1) {
37061+ if (qbman_swp_pull(swp, &pulldesc)) {
37062+ PMD_DRV_LOG(WARNING, "VDQ command is not issued."
37063+ "QBMAN is busy\n");
37064+ /* Portal was busy, try again */
37065+ continue;
37066+ }
37067+ break;
37068+ }
37069+ q_storage->active_dqs = dq_storage;
37070+ thread_io_info.global_active_dqs = dq_storage;
37071+ }
37072+ while(!qbman_check_command_complete(swp, thread_io_info.global_active_dqs))
37073+ ;
37074+ dq_storage = q_storage->active_dqs;
37075+ while (!is_last) {
37076+ /* Loop until the dq_storage is updated with
37077+ * new token by QBMAN */
37078+ struct rte_mbuf *mbuf;
37079+
37080+ while (!qbman_result_has_new_result(swp, dq_storage))
37081+ ;
37082+ rte_prefetch0((void *)((uint64_t)(dq_storage + 1)));
37083+ /* Check whether Last Pull command is Expired and
37084+ setting Condition for Loop termination */
37085+ if (qbman_result_DQ_is_pull_complete(dq_storage)) {
37086+ is_last = 1;
37087+ /* Check for valid frame. */
37088+ status = (uint8_t)qbman_result_DQ_flags(dq_storage);
37089+ if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0)) {
37090+ PMD_DRV_LOG(DEBUG, "No frame is delivered\n");
37091+ continue;
37092+ }
37093+ }
37094+ fd[num_rx] = qbman_result_DQ_fd(dq_storage);
37095+ mbuf = DPAA2_INLINE_MBUF_FROM_BUF(DPAA2_GET_FD_ADDR(fd[num_rx]));
37096+ /* Prefeth mbuf */
37097+ rte_prefetch0(mbuf);
37098+ /* Prefetch Annotation address from where we get parse results */
37099+ rte_prefetch0((void *)((uint64_t)DPAA2_GET_FD_ADDR(fd[num_rx]) + DPAA2_FD_PTA_SIZE + 16));
37100+ /*Prefetch Data buffer*/
37101+ /* rte_prefetch0((void *)((uint64_t)DPAA2_GET_FD_ADDR(fd[num_rx]) + DPAA2_GET_FD_OFFSET(fd[num_rx]))); */
37102+ dq_storage++;
37103+ num_rx++;
37104+
37105+ } /* End of Packet Rx loop */
37106+
37107+ for (i = 0; i < num_rx; i++) {
37108+ bufs[i] = eth_fd_to_mbuf(fd[i]);
37109+ bufs[i]->port = dev->data->port_id;
37110+ }
37111+
37112+ q_storage->toggle ^= 1;
37113+ dq_storage = q_storage->dq_storage[q_storage->toggle];
37114+ qbman_pull_desc_clear(&pulldesc);
37115+ qbman_pull_desc_set_numframes(&pulldesc, nb_pkts);
37116+ qbman_pull_desc_set_fq(&pulldesc, fqid);
37117+ qbman_pull_desc_set_storage(&pulldesc, dq_storage,
37118+ (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
37119+ /*Issue a volatile dequeue command. */
37120+
37121+ while (1) {
37122+ if (qbman_swp_pull(swp, &pulldesc)) {
37123+ PMD_DRV_LOG(WARNING, "VDQ command is not issued."
37124+ "QBMAN is busy\n");
37125+ continue;
37126+ }
37127+ break;
37128+ }
37129+ q_storage->active_dqs = dq_storage;
37130+ thread_io_info.global_active_dqs = dq_storage;
37131+
37132+ dpaa2_q->rx_pkts += num_rx;
37133+
37134+ PMD_DRV_LOG(INFO, "Ethernet Received %d Packets\n", num_rx);
37135+ /*Return the total number of packets received to DPAA2 app*/
37136+ return num_rx;
37137+}
37138+
37139+/*
37140+ * Callback to handle sending packets through a real NIC.
37141+ */
37142+static uint16_t
37143+eth_dpaa2_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
37144+{
37145+ /* Function to transmit the frames to given device and VQ*/
37146+ uint32_t loop;
37147+ int32_t ret;
37148+#ifdef QBMAN_MULTI_TX
37149+ struct qbman_fd fd_arr[8];
37150+ uint32_t frames_to_send;
37151+#else
37152+ struct qbman_fd fd;
37153+#endif
37154+ struct rte_mempool *mp;
37155+ struct qbman_eq_desc eqdesc;
37156+ struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
37157+ struct qbman_swp *swp;
37158+ uint16_t num_tx = 0;
37159+ /*todo - need to support multiple buffer pools */
37160+ uint16_t bpid;
37161+ struct rte_eth_dev *dev = dpaa2_q->dev;
37162+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
37163+
37164+ if (!thread_io_info.dpio_dev) {
37165+ ret = dpaa2_affine_qbman_swp();
37166+ if (ret) {
37167+ PMD_DRV_LOG(ERR, "Failure in affining portal\n");
37168+ return 0;
37169+ }
37170+ }
37171+ swp = thread_io_info.dpio_dev->sw_portal;
37172+
37173+ /*Prepare enqueue descriptor*/
37174+ qbman_eq_desc_clear(&eqdesc);
37175+ qbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);
37176+ qbman_eq_desc_set_response(&eqdesc, 0, 0);
37177+ qbman_eq_desc_set_qd(&eqdesc, priv->qdid,
37178+ dpaa2_q->flow_id, dpaa2_q->tc_index);
37179+
37180+ /*Clear the unused FD fields before sending*/
37181+#ifdef QBMAN_MULTI_TX
37182+ while(nb_pkts) {
37183+ /*Check if the queue is congested*/
37184+ if(qbman_result_is_CSCN(dpaa2_q->cscn))
37185+ goto skip_tx;
37186+
37187+ frames_to_send = (nb_pkts >> 3) ? MAX_SLOTS : nb_pkts;
37188+
37189+ for(loop = 0; loop < frames_to_send; loop++) {
37190+ fd_arr[loop].simple.frc = 0;
37191+ DPAA2_RESET_FD_CTRL((&fd_arr[loop]));
37192+ DPAA2_SET_FD_FLC((&fd_arr[loop]), NULL);
37193+ mp = (*bufs)->pool;
37194+ /* Not a hw_pkt pool allocated frame */
37195+ if (mp && !(mp->flags & MEMPOOL_F_HW_PKT_POOL)) {
37196+ printf ("\n non hw offload bufffer ");
37197+ /* alloc should be from the default buffer pool
37198+ attached to this interface */
37199+ bpid = priv->bp_list->buf_pool.bpid;
37200+ if (eth_copy_mbuf_to_fd(*bufs, &fd_arr[loop], bpid)) {
37201+ bufs++;
37202+ continue;
37203+ }
37204+ } else {
37205+ bpid = mp->offload_ptr;
37206+ eth_mbuf_to_fd(*bufs, &fd_arr[loop], bpid);
37207+ }
37208+ bufs++;
37209+ }
37210+ loop = 0;
37211+ while(loop < frames_to_send) {
37212+ loop += qbman_swp_send_multiple(swp, &eqdesc,
37213+ &fd_arr[loop], frames_to_send - loop);
37214+ }
37215+
37216+ num_tx += frames_to_send;
37217+ dpaa2_q->tx_pkts += frames_to_send;
37218+ nb_pkts -= frames_to_send;
37219+ }
37220+#else
37221+ /*Check if the queue is congested*/
37222+// if(qbman_result_is_CSCN(dpaa2_q->cscn))
37223+// goto skip_tx;
37224+
37225+ fd.simple.frc = 0;
37226+ DPAA2_RESET_FD_CTRL((&fd));
37227+ DPAA2_SET_FD_FLC((&fd), NULL);
37228+ loop = 0;
37229+
37230+ while (loop < nb_pkts) {
37231+ /*Prepare each packet which is to be sent*/
37232+ mp = bufs[loop]->pool;
37233+ /* Not a hw_pkt pool allocated frame */
37234+ if (mp && !(mp->flags & MEMPOOL_F_HW_PKT_POOL)) {
37235+ printf ("\n non hw offload bufffer ");
37236+ /* alloc should be from the default buffer pool
37237+ attached to this interface */
37238+ if (priv->bp_list)
37239+ bpid = priv->bp_list->buf_pool.bpid;
37240+ else
37241+ printf("\n ??? why no bpool attached");
37242+
37243+ if (eth_copy_mbuf_to_fd(bufs[loop], &fd, bpid)) {
37244+ loop++;
37245+ continue;
37246+ }
37247+ } else {
37248+ bpid = mp->offload_ptr;
37249+ eth_mbuf_to_fd(bufs[loop], &fd, bpid);
37250+ }
37251+ /*Enqueue a single packet to the QBMAN*/
37252+ do {
37253+ ret = qbman_swp_enqueue(swp, &eqdesc, &fd);
37254+ if (ret != 0) {
37255+ PMD_DRV_LOG(DEBUG, "Error in transmiting the frame\n");
37256+ }
37257+ } while (ret != 0);
37258+
37259+ /* Free the buffer shell */
37260+ /* rte_pktmbuf_free(bufs[loop]); */
37261+ num_tx++; loop++;
37262+ }
37263+ dpaa2_q->tx_pkts += num_tx;
37264+ dpaa2_q->err_pkts += nb_pkts - num_tx;
37265+#endif
37266+ skip_tx:
37267+ return num_tx;
37268+}
37269+
37270+static int
37271+dpaa2_vlan_stripping_set(struct rte_eth_dev *dev, int on)
37272+{
37273+ int ret;
37274+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
37275+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
37276+
37277+ PMD_INIT_FUNC_TRACE();
37278+
37279+ if (dpni == NULL) {
37280+ PMD_DRV_LOG(ERR, "dpni is NULL");
37281+ return -1;
37282+ }
37283+
37284+ ret = dpni_set_vlan_removal(dpni, CMD_PRI_LOW, priv->token, on);
37285+ if (ret < 0)
37286+ PMD_DRV_LOG(ERR, "Unable to dpni_set_vlan_removal hwid =%d",
37287+ priv->hw_id);
37288+ return ret;
37289+}
37290+
37291+static int
37292+dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
37293+{
37294+ int ret;
37295+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
37296+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
37297+
37298+ if (dpni == NULL) {
37299+ PMD_DRV_LOG(ERR, "dpni is NULL");
37300+ return -1;
37301+ }
37302+
37303+ if (on)
37304+ ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token, vlan_id);
37305+ else
37306+ ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, priv->token, vlan_id);
37307+
37308+ if (ret < 0)
37309+ PMD_DRV_LOG(ERR, "ret = %d Unable to add/rem vlan %d hwid =%d",
37310+ ret, vlan_id, priv->hw_id);
37311+
37312+ /*todo this should on global basis */
37313+/* ret = dpni_set_vlan_filters(dpni, CMD_PRI_LOW, priv->token, on);
37314+ if (ret < 0)
37315+ PMD_DRV_LOG(ERR, "Unable to set vlan filter");
37316+*/ return ret;
37317+}
37318+
37319+static void
37320+dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
37321+{
37322+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
37323+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
37324+ int ret;
37325+ if (mask & ETH_VLAN_FILTER_MASK) {
37326+ if (dev->data->dev_conf.rxmode.hw_vlan_filter)
37327+ ret = dpni_set_vlan_filters(dpni, CMD_PRI_LOW, priv->token, TRUE);
37328+ else
37329+ ret = dpni_set_vlan_filters(dpni, CMD_PRI_LOW, priv->token, FALSE);
37330+ if (ret < 0)
37331+ PMD_DRV_LOG(ERR, "ret = %d Unable to set vlan filter", ret);
37332+ }
37333+
37334+ if (mask & ETH_VLAN_STRIP_MASK) {
37335+ /* Enable or disable VLAN stripping */
37336+ if (dev->data->dev_conf.rxmode.hw_vlan_strip)
37337+ dpaa2_vlan_stripping_set(dev, TRUE);
37338+ else
37339+ dpaa2_vlan_stripping_set(dev, FALSE);
37340+ }
37341+
37342+ if (mask & ETH_VLAN_EXTEND_MASK) {
37343+ PMD_INIT_FUNC_TRACE();
37344+/* if (dev->data->dev_conf.rxmode.hw_vlan_extend)
37345+ i40e_vsi_config_double_vlan(vsi, TRUE);
37346+ else
37347+ i40e_vsi_config_double_vlan(vsi, FALSE);
37348+*/ }
37349+}
37350+
37351+static void
37352+dpaa2_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
37353+{
37354+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
37355+
37356+ dev_info->driver_name = drivername;
37357+ dev_info->if_index = priv->hw_id;
37358+ dev_info->max_mac_addrs = priv->max_unicast_filters;
37359+ dev_info->max_rx_pktlen = (uint32_t)-1;
37360+ dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
37361+ dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
37362+ dev_info->min_rx_bufsize = 0;
37363+ dev_info->pci_dev = dev->pci_dev;
37364+/* dev_info->rx_offload_capa =
37365+ DEV_RX_OFFLOAD_IPV4_CKSUM |
37366+ DEV_RX_OFFLOAD_UDP_CKSUM |
37367+ DEV_RX_OFFLOAD_TCP_CKSUM;
37368+ dev_info->tx_offload_capa =
37369+ DEV_TX_OFFLOAD_IPV4_CKSUM |
37370+ DEV_TX_OFFLOAD_UDP_CKSUM |
37371+ DEV_TX_OFFLOAD_TCP_CKSUM |
37372+ DEV_TX_OFFLOAD_SCTP_CKSUM;
37373+*/
37374+}
37375+
37376+static int
37377+dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
37378+{
37379+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
37380+ uint8_t tc_idx;
37381+ uint16_t dist_idx;
37382+ uint32_t vq_id;
37383+ struct dpaa2_queue *mc_q, *mcq;
37384+ uint32_t tot_queues;
37385+ int i;
37386+ struct dpaa2_queue *dpaa2_q;
37387+ tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
37388+ mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
37389+ RTE_CACHE_LINE_SIZE);
37390+ if (!mc_q) {
37391+ PMD_DRV_LOG(ERR, "malloc failed for rx/tx queues\n");
37392+ return -1;
37393+ }
37394+
37395+ for (i = 0; i < priv->nb_rx_queues; i++) {
37396+ mc_q->dev = dev;
37397+ priv->rx_vq[i] = mc_q++;
37398+ dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
37399+ dpaa2_q->q_storage = rte_malloc("dq_storage",
37400+ sizeof(struct queue_storage_info_t),
37401+ RTE_CACHE_LINE_SIZE);
37402+ if(!dpaa2_q->q_storage)
37403+ goto fail;
37404+
37405+ memset(dpaa2_q->q_storage, 0, sizeof(struct queue_storage_info_t));
37406+ }
37407+
37408+ for (i = 0; i < priv->nb_tx_queues; i++) {
37409+ mc_q->dev = dev;
37410+ priv->tx_vq[i] = mc_q++;
37411+ }
37412+
37413+ vq_id = 0;
37414+ for (tc_idx = 0; tc_idx < priv->num_tc; tc_idx++) {
37415+ for (dist_idx = 0; dist_idx < priv->num_dist_per_tc[tc_idx]; dist_idx++) {
37416+ mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
37417+ mcq->tc_index = tc_idx;
37418+ mcq->flow_id = dist_idx;
37419+ vq_id++;
37420+ }
37421+ }
37422+
37423+ return 0;
37424+fail:
37425+ i -= 1;
37426+ while(i >= 0)
37427+ {
37428+ dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
37429+ rte_free(dpaa2_q->q_storage);
37430+ }
37431+ return -1;
37432+}
37433+
37434+static void dpaa2_distset_to_dpkg_profile_cfg(
37435+ uint32_t req_dist_set,
37436+ struct dpkg_profile_cfg *kg_cfg)
37437+{
37438+ uint32_t loop = 0, i = 0, dist_field = 0;
37439+ int l2_configured = 0, l3_configured = 0;
37440+ int l4_configured = 0, sctp_configured = 0;
37441+
37442+ memset(kg_cfg, 0, sizeof(struct dpkg_profile_cfg));
37443+ while (req_dist_set) {
37444+ if (req_dist_set % 2 != 0) {
37445+ dist_field = 1U << loop;
37446+ switch (dist_field) {
37447+ case ETH_RSS_L2_PAYLOAD:
37448+
37449+ if (l2_configured)
37450+ break;
37451+ l2_configured = 1;
37452+
37453+ kg_cfg->extracts[i].extract.from_hdr.prot =
37454+ NET_PROT_ETH;
37455+ kg_cfg->extracts[i].extract.from_hdr.field =
37456+ NH_FLD_ETH_TYPE;
37457+ kg_cfg->extracts[i].type = DPKG_EXTRACT_FROM_HDR;
37458+ kg_cfg->extracts[i].extract.from_hdr.type =
37459+ DPKG_FULL_FIELD;
37460+ i++;
37461+ break;
37462+
37463+ case ETH_RSS_IPV4:
37464+ case ETH_RSS_FRAG_IPV4:
37465+ case ETH_RSS_NONFRAG_IPV4_OTHER:
37466+ case ETH_RSS_IPV6:
37467+ case ETH_RSS_FRAG_IPV6:
37468+ case ETH_RSS_NONFRAG_IPV6_OTHER:
37469+ case ETH_RSS_IPV6_EX:
37470+
37471+ if (l3_configured)
37472+ break;
37473+ l3_configured = 1;
37474+
37475+ kg_cfg->extracts[i].extract.from_hdr.prot =
37476+ NET_PROT_IP;
37477+ kg_cfg->extracts[i].extract.from_hdr.field =
37478+ NH_FLD_IP_SRC;
37479+ kg_cfg->extracts[i].type = DPKG_EXTRACT_FROM_HDR;
37480+ kg_cfg->extracts[i].extract.from_hdr.type =
37481+ DPKG_FULL_FIELD;
37482+ i++;
37483+
37484+ kg_cfg->extracts[i].extract.from_hdr.prot =
37485+ NET_PROT_IP;
37486+ kg_cfg->extracts[i].extract.from_hdr.field =
37487+ NH_FLD_IP_DST;
37488+ kg_cfg->extracts[i].type = DPKG_EXTRACT_FROM_HDR;
37489+ kg_cfg->extracts[i].extract.from_hdr.type =
37490+ DPKG_FULL_FIELD;
37491+ i++;
37492+
37493+ kg_cfg->extracts[i].extract.from_hdr.prot =
37494+ NET_PROT_IP;
37495+ kg_cfg->extracts[i].extract.from_hdr.field =
37496+ NH_FLD_IP_PROTO;
37497+ kg_cfg->extracts[i].type = DPKG_EXTRACT_FROM_HDR;
37498+ kg_cfg->extracts[i].extract.from_hdr.type =
37499+ DPKG_FULL_FIELD;
37500+ kg_cfg->num_extracts++;
37501+ i++;
37502+ break;
37503+
37504+ case ETH_RSS_NONFRAG_IPV4_TCP:
37505+ case ETH_RSS_NONFRAG_IPV6_TCP:
37506+ case ETH_RSS_NONFRAG_IPV4_UDP:
37507+ case ETH_RSS_NONFRAG_IPV6_UDP:
37508+
37509+ if (l4_configured)
37510+ break;
37511+ l4_configured = 1;
37512+
37513+ kg_cfg->extracts[i].extract.from_hdr.prot =
37514+ NET_PROT_TCP;
37515+ kg_cfg->extracts[i].extract.from_hdr.field =
37516+ NH_FLD_TCP_PORT_SRC;
37517+ kg_cfg->extracts[i].type = DPKG_EXTRACT_FROM_HDR;
37518+ kg_cfg->extracts[i].extract.from_hdr.type =
37519+ DPKG_FULL_FIELD;
37520+ i++;
37521+
37522+ kg_cfg->extracts[i].extract.from_hdr.prot =
37523+ NET_PROT_TCP;
37524+ kg_cfg->extracts[i].extract.from_hdr.field =
37525+ NH_FLD_TCP_PORT_SRC;
37526+ kg_cfg->extracts[i].type = DPKG_EXTRACT_FROM_HDR;
37527+ kg_cfg->extracts[i].extract.from_hdr.type =
37528+ DPKG_FULL_FIELD;
37529+ i++;
37530+ break;
37531+
37532+ case ETH_RSS_NONFRAG_IPV4_SCTP:
37533+ case ETH_RSS_NONFRAG_IPV6_SCTP:
37534+
37535+ if (sctp_configured)
37536+ break;
37537+ sctp_configured = 1;
37538+
37539+ kg_cfg->extracts[i].extract.from_hdr.prot =
37540+ NET_PROT_SCTP;
37541+ kg_cfg->extracts[i].extract.from_hdr.field =
37542+ NH_FLD_SCTP_PORT_SRC;
37543+ kg_cfg->extracts[i].type = DPKG_EXTRACT_FROM_HDR;
37544+ kg_cfg->extracts[i].extract.from_hdr.type =
37545+ DPKG_FULL_FIELD;
37546+ i++;
37547+
37548+ kg_cfg->extracts[i].extract.from_hdr.prot =
37549+ NET_PROT_SCTP;
37550+ kg_cfg->extracts[i].extract.from_hdr.field =
37551+ NH_FLD_SCTP_PORT_DST;
37552+ kg_cfg->extracts[i].type = DPKG_EXTRACT_FROM_HDR;
37553+ kg_cfg->extracts[i].extract.from_hdr.type =
37554+ DPKG_FULL_FIELD;
37555+ i++;
37556+ break;
37557+
37558+ default:
37559+ PMD_DRV_LOG(WARNING, "Bad flow distribution option %x\n", dist_field);
37560+ }
37561+ }
37562+ req_dist_set = req_dist_set >> 1;
37563+ loop++;
37564+ }
37565+ kg_cfg->num_extracts = i;
37566+}
37567+
37568+static int dpaa2_setup_flow_distribution(struct rte_eth_dev *eth_dev,
37569+ uint32_t req_dist_set)
37570+{
37571+ struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
37572+ struct fsl_mc_io *dpni = priv->hw;
37573+ struct dpni_rx_tc_dist_cfg tc_cfg;
37574+ struct dpkg_profile_cfg kg_cfg;
37575+ void *p_params;
37576+ int ret, tc_index = 0;
37577+
37578+ p_params = rte_malloc(
37579+ NULL, DIST_PARAM_IOVA_SIZE, RTE_CACHE_LINE_SIZE);
37580+ if (!p_params) {
37581+ PMD_DRV_LOG(ERR, "Memory unavaialble\n");
37582+ return -ENOMEM;
37583+ }
37584+ memset(p_params, 0, DIST_PARAM_IOVA_SIZE);
37585+ memset(&tc_cfg, 0, sizeof(struct dpni_rx_tc_dist_cfg));
37586+
37587+ dpaa2_distset_to_dpkg_profile_cfg(req_dist_set, &kg_cfg);
37588+ tc_cfg.key_cfg_iova = (uint64_t)(DPAA2_VADDR_TO_IOVA(p_params));
37589+ tc_cfg.dist_size = eth_dev->data->nb_rx_queues;
37590+ tc_cfg.dist_mode = DPNI_DIST_MODE_HASH;
37591+
37592+ ret = dpni_prepare_key_cfg(&kg_cfg, p_params);
37593+ if (ret) {
37594+ PMD_DRV_LOG(ERR, "Unable to prepare extract parameters\n");
37595+ rte_free(p_params);
37596+ return ret;
37597+ }
37598+
37599+ ret = dpni_set_rx_tc_dist(dpni, CMD_PRI_LOW, priv->token, tc_index,
37600+ &tc_cfg);
37601+ rte_free(p_params);
37602+ if (ret) {
37603+ PMD_DRV_LOG(ERR, "Setting distribution for Rx failed with"
37604+ "err code: %d\n", ret);
37605+ return ret;
37606+ }
37607+
37608+ return 0;
37609+}
37610+
37611+static int
37612+dpaa2_remove_flow_distribution(struct rte_eth_dev *eth_dev, uint8_t tc_index)
37613+{
37614+ struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
37615+ struct fsl_mc_io *dpni = priv->hw;
37616+ struct dpni_rx_tc_dist_cfg tc_cfg;
37617+ struct dpkg_profile_cfg kg_cfg;
37618+ void *p_params;
37619+ int ret;
37620+
37621+ p_params = rte_malloc(
37622+ NULL, DIST_PARAM_IOVA_SIZE, RTE_CACHE_LINE_SIZE);
37623+ if (!p_params) {
37624+ PMD_DRV_LOG(ERR, "Memory unavaialble\n");
37625+ return -ENOMEM;
37626+ }
37627+ memset(p_params, 0, DIST_PARAM_IOVA_SIZE);
37628+ memset(&tc_cfg, 0, sizeof(struct dpni_rx_tc_dist_cfg));
37629+
37630+ tc_cfg.key_cfg_iova = (uint64_t)(DPAA2_VADDR_TO_IOVA(p_params));
37631+ tc_cfg.dist_size = 0;
37632+ tc_cfg.dist_mode = DPNI_DIST_MODE_NONE;
37633+
37634+ ret = dpni_prepare_key_cfg(&kg_cfg, p_params);
37635+ if (ret) {
37636+ PMD_DRV_LOG(ERR, "Unable to prepare extract parameters\n");
37637+ rte_free(p_params);
37638+ return ret;
37639+ }
37640+
37641+ ret = dpni_set_rx_tc_dist(dpni, CMD_PRI_LOW, priv->token, tc_index,
37642+ &tc_cfg);
37643+ rte_free(p_params);
37644+ if (ret) {
37645+ PMD_DRV_LOG(ERR, "Setting distribution for Rx failed with"
37646+ "err code: %d\n", ret);
37647+ return ret;
37648+ }
37649+ return ret;
37650+}
37651+
37652+static int
37653+dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
37654+{
37655+ int i=0;
37656+
37657+ for(i = 0;i < NUM_DQS_PER_QUEUE; i++) {
37658+ q_storage->dq_storage[i] = rte_malloc(NULL,
37659+ NUM_MAX_RECV_FRAMES * sizeof(struct qbman_result),
37660+ RTE_CACHE_LINE_SIZE);
37661+ if(!q_storage->dq_storage[i])
37662+ goto fail;
37663+ /*setting toggle for initial condition*/
37664+ q_storage->toggle = -1;
37665+ }
37666+ return 0;
37667+fail:
37668+ i -= 1;
37669+ while(i >= 0)
37670+ {
37671+ rte_free(q_storage->dq_storage[i]);
37672+ }
37673+ return -1;
37674+}
37675+
37676+static int
37677+dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
37678+{
37679+ struct rte_eth_dev_data *data = dev->data;
37680+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
37681+ struct rte_eth_conf *eth_conf = &data->dev_conf;
37682+ struct dpaa2_queue *dpaa2_q;
37683+ int i, ret;
37684+
37685+ for (i = 0; i < data->nb_rx_queues; i++) {
37686+ data->rx_queues[i] = priv->rx_vq[i];
37687+ dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
37688+ if(dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
37689+ return -1;
37690+ }
37691+
37692+ for (i = 0; i < data->nb_tx_queues; i++) {
37693+ data->tx_queues[i] = priv->tx_vq[i];
37694+ dpaa2_q = (struct dpaa2_queue *)data->tx_queues[i];
37695+ dpaa2_q->cscn = rte_malloc(NULL, sizeof(struct qbman_result), 16);
37696+ if(!dpaa2_q->cscn)
37697+ goto fail_tx_queue;
37698+ }
37699+
37700+ /* Check for correct configuration */
37701+ if (eth_conf->rxmode.mq_mode != ETH_MQ_RX_RSS &&
37702+ data->nb_rx_queues > 1) {
37703+ PMD_DRV_LOG(ERR, "Distribution is not enabled, "
37704+ "but Rx queues more than 1\n");
37705+ return -1;
37706+ }
37707+
37708+ if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
37709+ /* Return in case number of Rx queues is 1 */
37710+ if (data->nb_rx_queues == 1)
37711+ return 0;
37712+ ret = dpaa2_setup_flow_distribution(dev,
37713+ eth_conf->rx_adv_conf.rss_conf.rss_hf);
37714+ if (ret) {
37715+ PMD_DRV_LOG(ERR, "dpaa2_setup_flow_distribution failed\n");
37716+ return ret;
37717+ }
37718+ }
37719+
37720+ return 0;
37721+ fail_tx_queue:
37722+ i -= 1;
37723+ while(i >= 0) {
37724+ dpaa2_q = (struct dpaa2_queue *)data->tx_queues[i];
37725+ rte_free(dpaa2_q->cscn);
37726+ }
37727+ return -1;
37728+}
37729+
37730+static int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv,
37731+ void *blist)
37732+{
37733+ /* Function to attach a DPNI with a buffer pool list. Buffer pool list
37734+ * handle is passed in blist.
37735+ */
37736+ int32_t retcode;
37737+ struct fsl_mc_io *dpni = priv->hw;
37738+ struct dpni_pools_cfg bpool_cfg;
37739+ struct dpaa2_bp_list *bp_list = (struct dpaa2_bp_list *)blist;
37740+
37741+ /*Attach buffer pool to the network interface as described by the user*/
37742+ bpool_cfg.num_dpbp = 1;
37743+ bpool_cfg.pools[0].dpbp_id = bp_list->buf_pool.dpbp_node->dpbp_id;
37744+ bpool_cfg.pools[0].backup_pool = 0;
37745+ bpool_cfg.pools[0].buffer_size =
37746+ DPAA2_ALIGN_ROUNDUP(bp_list->buf_pool.size,
37747+ DPAA2_PACKET_LAYOUT_ALIGN);;
37748+
37749+ retcode = dpni_set_pools(dpni, CMD_PRI_LOW, priv->token, &bpool_cfg);
37750+ if (retcode != 0) {
37751+ PMD_DRV_LOG(ERR, "Error in attaching the buffer pool list"
37752+ "bpid = %d Error code = %d\n",
37753+ bpool_cfg.pools[0].dpbp_id, retcode);
37754+ return retcode;
37755+ }
37756+
37757+ priv->bp_list = bp_list;
37758+ return 0;
37759+}
37760+
37761+/* Function to setup RX flow information. It contains traffic class ID,
37762+ * flow ID, destination configuration etc.
37763+ */
37764+static int
37765+dpaa2_rx_queue_setup(struct rte_eth_dev *dev,
37766+ uint16_t rx_queue_id,
37767+ uint16_t nb_rx_desc __rte_unused,
37768+ unsigned int socket_id __rte_unused,
37769+ const struct rte_eth_rxconf *rx_conf __rte_unused,
37770+ struct rte_mempool *mb_pool)
37771+{
37772+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
37773+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
37774+ struct dpaa2_queue *dpaa2_q;
37775+ struct dpni_queue_cfg cfg;
37776+ uint8_t tc_id, flow_id;
37777+ int ret;
37778+
37779+ PMD_DRV_LOG(INFO, "\n dev =%p, queue =%d, pool = %p, conf =%p",
37780+ dev, rx_queue_id, mb_pool, rx_conf);
37781+
37782+ if (!priv->bp_list) {
37783+ if (mb_pool->offload_ptr > MAX_BPID) {
37784+ printf ("\n ??? ERR - %s not a offloaded buffer pool",
37785+ __func__);
37786+ return -1;
37787+ }
37788+ ret = dpaa2_attach_bp_list(priv,
37789+ bpid_info[mb_pool->offload_ptr].bp_list);
37790+ if (ret)
37791+ return ret;
37792+ }
37793+ dpaa2_q = (struct dpaa2_queue *)dev->data->rx_queues[rx_queue_id];
37794+
37795+ /*Get the tc id and flow id from given VQ id*/
37796+ tc_id = rx_queue_id / MAX_DIST_PER_TC;
37797+ flow_id = rx_queue_id % MAX_DIST_PER_TC;
37798+ memset(&cfg, 0, sizeof(struct dpni_queue_cfg));
37799+
37800+ cfg.options = cfg.options | DPNI_QUEUE_OPT_USER_CTX;
37801+
37802+#ifdef DPAA2_STASHING
37803+ cfg.options = cfg.options | DPNI_QUEUE_OPT_FLC;
37804+#endif
37805+
37806+ cfg.user_ctx = (uint64_t)(dpaa2_q);
37807+#ifdef DPAA2_STASHING
37808+ cfg.flc_cfg.flc_type = DPNI_FLC_STASH;
37809+ cfg.flc_cfg.frame_data_size = DPNI_STASH_SIZE_64B;
37810+ /* Enabling Annotation stashing */
37811+ cfg.options |= DPNI_FLC_STASH_FRAME_ANNOTATION;
37812+ cfg.flc_cfg.options = DPNI_FLC_STASH_FRAME_ANNOTATION;
37813+#endif
37814+
37815+ cfg.options = cfg.options | DPNI_QUEUE_OPT_TAILDROP_THRESHOLD;
37816+ cfg.tail_drop_threshold = 2048;// 16 packet
37817+
37818+ ret = dpni_set_rx_flow(dpni, CMD_PRI_LOW, priv->token,
37819+ tc_id, flow_id, &cfg);
37820+ if (ret) {
37821+ PMD_DRV_LOG(ERR, "Error in setting the rx flow: = %d\n", ret);
37822+ return -1;
37823+ }
37824+ return 0;
37825+}
37826+
37827+static int
37828+dpaa2_tx_queue_setup(struct rte_eth_dev *dev,
37829+ uint16_t tx_queue_id,
37830+ uint16_t nb_tx_desc __rte_unused,
37831+ unsigned int socket_id __rte_unused,
37832+ const struct rte_eth_txconf *tx_conf __rte_unused)
37833+{
37834+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
37835+ struct dpaa2_queue *dpaa2_q;
37836+ struct fsl_mc_io *dpni = priv->hw;
37837+ struct dpni_tx_flow_cfg cfg;
37838+ struct dpni_tx_conf_cfg tx_conf_cfg;
37839+#ifdef QBMAN_MULTI_TX
37840+ struct dpni_congestion_notification_cfg cong_notif_cfg;
37841+#endif
37842+ uint32_t tc_idx;
37843+ uint16_t flow_id = DPNI_NEW_FLOW_ID;
37844+ int ret;
37845+
37846+ PMD_INIT_FUNC_TRACE();
37847+
37848+ memset(&cfg, 0, sizeof(struct dpni_tx_flow_cfg));
37849+ cfg.l3_chksum_gen = 1;
37850+ cfg.options |= DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN;
37851+ cfg.l4_chksum_gen = 1;
37852+ cfg.options = DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN;
37853+ memset(&tx_conf_cfg, 0, sizeof(struct dpni_tx_conf_cfg));
37854+ tx_conf_cfg.errors_only = TRUE;
37855+
37856+ /*
37857+ if (action & DPAA2BUF_TX_CONF_REQUIRED) {
37858+ cfg.options = DPNI_TX_FLOW_OPT_TX_CONF_ERROR;
37859+ cfg.use_common_tx_conf_queue =
37860+ ((action & DPAA2BUF_TX_CONF_ERR_ON_COMMON_Q) ?
37861+ TRUE : FALSE);
37862+ tx_conf_cfg.errors_only = FALSE;
37863+ }*/
37864+
37865+ if (priv->num_tc == 1)
37866+ tc_idx = 0;
37867+ else
37868+ tc_idx = tx_queue_id;
37869+
37870+ ret = dpni_set_tx_flow(dpni, CMD_PRI_LOW, priv->token, &flow_id, &cfg);
37871+ if (ret) {
37872+ PMD_DRV_LOG(ERR, "Error in setting the tx flow:"
37873+ "ErrorCode = %x\n", ret);
37874+ return -1;
37875+ }
37876+ /*Set tx-conf and error configuration*/
37877+ ret = dpni_set_tx_conf(dpni, CMD_PRI_LOW, priv->token,
37878+ flow_id, &tx_conf_cfg);
37879+ if (ret) {
37880+ PMD_DRV_LOG(ERR, "Error in setting tx conf settings: "
37881+ "ErrorCode = %x", ret);
37882+ return -1;
37883+ }
37884+
37885+ if (tx_queue_id == 0) {
37886+ /*Set tx-conf and error configuration*/
37887+ ret = dpni_set_tx_conf(dpni, CMD_PRI_LOW, priv->token,
37888+ DPNI_COMMON_TX_CONF, &tx_conf_cfg);
37889+ if (ret) {
37890+ PMD_DRV_LOG(ERR, "Error in setting tx conf settings: "
37891+ "ErrorCode = %x", ret);
37892+ return -1;
37893+ }
37894+ }
37895+ /*todo - add the queue id support instead of hard queue id as "0" */
37896+ dpaa2_q = (struct dpaa2_queue *)dev->data->tx_queues[tx_queue_id];
37897+ dpaa2_q->tc_index = tc_idx;
37898+ if (flow_id == DPNI_NEW_FLOW_ID)
37899+ dpaa2_q->flow_id = 0;
37900+ else
37901+ dpaa2_q->flow_id = flow_id;
37902+
37903+#ifdef QBMAN_MULTI_TX
37904+ cong_notif_cfg.units = DPNI_CONGESTION_UNIT_BYTES;
37905+ /*Notify about congestion when the queue size is 128 frames with each \
37906+ frame 64 bytes size*/
37907+ cong_notif_cfg.threshold_entry = CONG_ENTER_THRESHOLD;
37908+ /*Notify that the queue is not congested when the number of frames in \
37909+ the queue is below this thershold.
37910+ TODO: Check if this value is the optimum value for better performance*/
37911+ cong_notif_cfg.threshold_exit = CONG_EXIT_THRESHOLD;
37912+ cong_notif_cfg.message_ctx = 0;
37913+ cong_notif_cfg.message_iova = (uint64_t)dpaa2_q->cscn;
37914+ cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
37915+ cong_notif_cfg.options = DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
37916+ DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | DPNI_CONG_OPT_COHERENT_WRITE;
37917+
37918+ ret = dpni_set_tx_tc_congestion_notification(dpni, CMD_PRI_LOW,
37919+ priv->token,
37920+ tc_idx, &cong_notif_cfg);
37921+ if(ret) {
37922+ PMD_DRV_LOG(ERR, "Error in setting tx congestion notification "
37923+ "settings: ErrorCode = %x", ret);
37924+ return -1;
37925+ }
37926+#endif
37927+ return 0;
37928+}
37929+
37930+static const uint32_t *
37931+dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
37932+{
37933+ static const uint32_t ptypes[] = {
37934+ /*todo -= add more types */
37935+ RTE_PTYPE_L2_ETHER,
37936+ RTE_PTYPE_L3_IPV4,
37937+ RTE_PTYPE_L3_IPV4_EXT,
37938+ RTE_PTYPE_L3_IPV6,
37939+ RTE_PTYPE_L3_IPV6_EXT,
37940+ RTE_PTYPE_L4_TCP,
37941+ RTE_PTYPE_L4_UDP,
37942+ RTE_PTYPE_L4_SCTP,
37943+ RTE_PTYPE_L4_ICMP,
37944+ RTE_PTYPE_UNKNOWN
37945+ };
37946+
37947+ if (dev->rx_pkt_burst == eth_dpaa2_prefetch_rx ||
37948+ dev->rx_pkt_burst == eth_dpaa2_rx)
37949+ return ptypes;
37950+ return NULL;
37951+}
37952+
37953+static int
37954+dpaa2_dev_start(struct rte_eth_dev *dev)
37955+{
37956+ struct rte_eth_dev_data *data = dev->data;
37957+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
37958+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
37959+ struct dpni_queue_attr cfg;
37960+ uint16_t qdid;
37961+ struct dpaa2_queue *dpaa2_q;
37962+ int ret, i, mask = 0;
37963+
37964+ PMD_INIT_FUNC_TRACE();
37965+
37966+ dev->data->dev_link.link_status = 1;
37967+
37968+ ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
37969+ if (ret) {
37970+ PMD_DRV_LOG(ERR, "Failure %d in enabling dpni %d device\n",
37971+ ret, priv->hw_id);
37972+ return ret;
37973+ }
37974+
37975+ ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token, &qdid);
37976+ if (ret) {
37977+ PMD_DRV_LOG(ERR, "Error to get qdid:ErrorCode = %d\n", ret);
37978+ return ret;
37979+ }
37980+ priv->qdid = qdid;
37981+
37982+ for (i = 0; i < data->nb_rx_queues; i++) {
37983+ dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
37984+ ret = dpni_get_rx_flow(dpni, CMD_PRI_LOW, priv->token,
37985+ dpaa2_q->tc_index, dpaa2_q->flow_id, &cfg);
37986+ if (ret) {
37987+ PMD_DRV_LOG(ERR, "Error to get flow "
37988+ "information Error code = %d\n", ret);
37989+ return ret;
37990+ }
37991+ dpaa2_q->fqid = cfg.fqid;
37992+ }
37993+ /*
37994+ * VLAN Offload Settings
37995+ */
37996+ if (priv->options & DPNI_OPT_VLAN_FILTER)
37997+ mask = ETH_VLAN_FILTER_MASK;
37998+
37999+ if (priv->options & DPNI_OPT_VLAN_MANIPULATION)
38000+ mask = ETH_VLAN_STRIP_MASK;
38001+
38002+ if (mask)
38003+ dpaa2_vlan_offload_set(dev, mask);
38004+
38005+ return 0;
38006+}
38007+
38008+/*********************************************************************
38009+ *
38010+ * This routine disables all traffic on the adapter by issuing a
38011+ * global reset on the MAC.
38012+ *
38013+ **********************************************************************/
38014+static void
38015+dpaa2_dev_stop(struct rte_eth_dev *dev)
38016+{
38017+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38018+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38019+ int ret;
38020+ struct rte_eth_link link;
38021+
38022+ dev->data->dev_link.link_status = 0;
38023+
38024+ ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
38025+ if (ret) {
38026+ PMD_DRV_LOG(ERR, "Failure in disabling dpni %d device\n", priv->hw_id);
38027+ return;
38028+ }
38029+
38030+ /* clear the recorded link status */
38031+ memset(&link, 0, sizeof(link));
38032+ rte_dpni_dev_atomic_write_link_status(dev, &link);
38033+}
38034+
38035+static void
38036+dpaa2_dev_close(struct rte_eth_dev *dev)
38037+{
38038+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38039+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38040+ int ret;
38041+ struct rte_eth_link link;
38042+
38043+ /*Function is reverse of dpaa2_dev_init.
38044+ * It does the following:
38045+ * 1. Detach a DPNI from attached resources i.e. buffer pools, dpbp_id.
38046+ * 2. Close the DPNI device
38047+ * 3. Free the allocated reqources.
38048+ */
38049+
38050+ /* Clean the device first */
38051+ ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
38052+ if (ret) {
38053+ PMD_DRV_LOG(ERR, "Failure cleaning dpni device with"
38054+ "error code %d\n", ret);
38055+ return;
38056+ }
38057+
38058+ /*Close the device at underlying layer*/
38059+ ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
38060+ if (ret) {
38061+ PMD_DRV_LOG(ERR, "Failure closing dpni device with"
38062+ "error code %d\n", ret);
38063+ return;
38064+ }
38065+
38066+ /*Free the allocated memory for ethernet private data and dpni*/
38067+ priv->hw = NULL;
38068+ free(dpni);
38069+
38070+ memset(&link, 0, sizeof(link));
38071+ rte_dpni_dev_atomic_write_link_status(dev, &link);
38072+}
38073+
38074+static void
38075+dpaa2_dev_promiscuous_enable(
38076+ struct rte_eth_dev *dev)
38077+{
38078+ int ret;
38079+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38080+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38081+
38082+ if (dpni == NULL) {
38083+ PMD_DRV_LOG(ERR, "dpni is NULL");
38084+ return;
38085+ }
38086+
38087+ ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, TRUE);
38088+ if (ret < 0)
38089+ PMD_DRV_LOG(ERR, "Unable to enable promiscuous mode");
38090+ return;
38091+}
38092+
38093+static void
38094+dpaa2_dev_promiscuous_disable(
38095+ struct rte_eth_dev *dev)
38096+{
38097+ int ret;
38098+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38099+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38100+
38101+ if (dpni == NULL) {
38102+ PMD_DRV_LOG(ERR, "dpni is NULL");
38103+ return;
38104+ }
38105+
38106+ ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, FALSE);
38107+ if (ret < 0)
38108+ PMD_DRV_LOG(ERR, "Unable to disable promiscuous mode");
38109+ return;
38110+}
38111+
38112+static void
38113+dpaa2_dev_allmulticast_enable(
38114+ struct rte_eth_dev *dev)
38115+{
38116+ int ret;
38117+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38118+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38119+
38120+ if (dpni == NULL) {
38121+ PMD_DRV_LOG(ERR, "dpni is NULL");
38122+ return;
38123+ }
38124+
38125+ ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
38126+ if (ret < 0)
38127+ PMD_DRV_LOG(ERR, "Unable to enable promiscuous mode");
38128+ return;
38129+}
38130+
38131+static void
38132+dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
38133+{
38134+ int ret;
38135+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38136+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38137+
38138+ if (dpni == NULL) {
38139+ PMD_DRV_LOG(ERR, "dpni is NULL");
38140+ return;
38141+ }
38142+
38143+ ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
38144+ if (ret < 0)
38145+ PMD_DRV_LOG(ERR, "Unable to enable promiscuous mode");
38146+ return;
38147+}
38148+
38149+static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
38150+{
38151+ int ret;
38152+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38153+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38154+ uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
38155+
38156+ if (dpni == NULL) {
38157+ PMD_DRV_LOG(ERR, "dpni is NULL");
38158+ return -EINVAL;
38159+ }
38160+
38161+ /* check that mtu is within the allowed range */
38162+
38163+ if ((mtu < ETHER_MIN_MTU) || (frame_size > ETHER_MAX_JUMBO_FRAME_LEN))
38164+ return -EINVAL;
38165+
38166+ /* Set the Max Rx frame length as 'mtu' +
38167+ * Maximum Ethernet header length */
38168+ ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
38169+ mtu + ETH_VLAN_HLEN);
38170+ if (ret) {
38171+ PMD_DRV_LOG(ERR, "setting the max frame length failed");
38172+ return -1;
38173+ }
38174+ if (priv->options & DPNI_OPT_IPF) {
38175+ ret = dpni_set_mtu(dpni, CMD_PRI_LOW, priv->token, mtu);
38176+ if (ret) {
38177+ PMD_DRV_LOG(ERR, "Setting the MTU failed");
38178+ return -1;
38179+ }
38180+ }
38181+
38182+ PMD_DRV_LOG(INFO, "MTU is configured %d for the device\n", mtu);
38183+ return 0;
38184+}
38185+
38186+static void
38187+dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
38188+ struct ether_addr *addr,
38189+ __rte_unused uint32_t index,
38190+ __rte_unused uint32_t pool)
38191+{
38192+ int ret;
38193+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38194+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38195+
38196+ if (dpni == NULL) {
38197+ PMD_DRV_LOG(ERR, "dpni is NULL");
38198+ return;
38199+ }
38200+
38201+ ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW,
38202+ priv->token, addr->addr_bytes);
38203+ if (ret) {
38204+ PMD_DRV_LOG(ERR, "Adding the MAC ADDR failed");
38205+ }
38206+
38207+ return;
38208+}
38209+
38210+static void
38211+dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
38212+ uint32_t index)
38213+{
38214+ int ret;
38215+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38216+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38217+ struct rte_eth_dev_data *data = dev->data;
38218+ struct ether_addr *macaddr;
38219+
38220+ macaddr = &data->mac_addrs[index];
38221+
38222+ if (dpni == NULL) {
38223+ PMD_DRV_LOG(ERR, "dpni is NULL");
38224+ return;
38225+ }
38226+
38227+ ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
38228+ priv->token, macaddr->addr_bytes);
38229+ if (ret) {
38230+ PMD_DRV_LOG(ERR, "Removing the MAC ADDR failed");
38231+ }
38232+
38233+ return;
38234+}
38235+
38236+static void
38237+dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
38238+ struct ether_addr *addr)
38239+{
38240+ int ret;
38241+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38242+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38243+
38244+ if (dpni == NULL) {
38245+ PMD_DRV_LOG(ERR, "dpni is NULL");
38246+ return;
38247+ }
38248+
38249+ ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
38250+ priv->token, addr->addr_bytes);
38251+
38252+ if (ret) {
38253+ PMD_DRV_LOG(ERR, "Setting the MAC ADDR failed");
38254+ }
38255+
38256+ return;
38257+}
38258+
38259+int dpaa2_dev_get_mac_addr(struct rte_eth_dev *dev,
38260+ struct ether_addr *addr)
38261+{
38262+ int ret;
38263+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38264+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38265+
38266+ if (dpni == NULL) {
38267+ PMD_DRV_LOG(ERR, "dpni is NULL");
38268+ return -EINVAL;
38269+ }
38270+
38271+ ret = dpni_get_primary_mac_addr(dpni, CMD_PRI_LOW,
38272+ priv->token, addr->addr_bytes);
38273+
38274+ if (ret) {
38275+ PMD_DRV_LOG(ERR, "Getting the MAC ADDR failed");
38276+ }
38277+
38278+ return ret;
38279+}
38280+
38281+/*int dpni_clear_mac_filters(struct fsl_mc_io *mc_io,
38282+ uint32_t cmd_flags,
38283+ uint16_t token,
38284+ int unicast,
38285+ int multicast)
38286+
38287+
38288+int dpni_set_vlan_insertion(struct fsl_mc_io *mc_io,
38289+ uint32_t cmd_flags,
38290+ uint16_t token,
38291+ int en)
38292+
38293+dpni_set_errors_behavior
38294+
38295+int dpni_get_l3_chksum_validation(struct fsl_mc_io *mc_io,
38296+ uint32_t cmd_flags,
38297+ uint16_t token,
38298+ int *en)
38299+
38300+int dpni_set_l3_chksum_validation(struct fsl_mc_io *mc_io,
38301+ uint32_t cmd_flags,
38302+ uint16_t token,
38303+ int en)
38304+
38305+int dpni_get_l4_chksum_validation(struct fsl_mc_io *mc_io,
38306+ uint32_t cmd_flags,
38307+ uint16_t token,
38308+ int *en)
38309+
38310+int dpni_set_l4_chksum_validation(struct fsl_mc_io *mc_io,
38311+ uint32_t cmd_flags,
38312+ uint16_t token,
38313+ int en)
38314+
38315+*/
38316+
38317+static int dpaa2_timestamp_enable(struct rte_eth_dev *dev)
38318+{
38319+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38320+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38321+
38322+ struct dpni_buffer_layout layout;
38323+ int ret;
38324+
38325+ layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
38326+ layout.pass_timestamp = TRUE;
38327+
38328+ ret = dpni_set_rx_buffer_layout(dpni, CMD_PRI_LOW, priv->token, &layout);
38329+ if (ret) {
38330+ PMD_DRV_LOG(ERR, "Enabling timestamp for Rx failed with"
38331+ "err code: %d", ret);
38332+ return ret;
38333+ }
38334+
38335+ ret = dpni_set_tx_buffer_layout(dpni, CMD_PRI_LOW, priv->token, &layout);
38336+ if (ret) {
38337+ PMD_DRV_LOG(ERR, "Enabling timestamp failed for Tx with"
38338+ "err code: %d", ret);
38339+ return ret;
38340+ }
38341+
38342+ ret = dpni_set_tx_conf_buffer_layout(dpni, CMD_PRI_LOW,
38343+ priv->token, &layout);
38344+ if (ret) {
38345+ PMD_DRV_LOG(ERR, "Enabling timestamp failed for Tx-conf with"
38346+ "err code: %d", ret);
38347+ return ret;
38348+ }
38349+
38350+ return 0;
38351+}
38352+
38353+static int dpaa2_timestamp_disable(struct rte_eth_dev *dev)
38354+{
38355+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38356+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38357+ struct dpni_buffer_layout layout;
38358+ int ret;
38359+
38360+ layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
38361+ layout.pass_timestamp = FALSE;
38362+
38363+ ret = dpni_set_rx_buffer_layout(dpni, CMD_PRI_LOW, priv->token, &layout);
38364+ if (ret) {
38365+ PMD_DRV_LOG(ERR, "Disabling timestamp failed for Rx with"
38366+ "err code: %d", ret);
38367+ return ret;
38368+ }
38369+
38370+ ret = dpni_set_tx_buffer_layout(dpni, CMD_PRI_LOW, priv->token, &layout);
38371+ if (ret) {
38372+ PMD_DRV_LOG(ERR, "Disabling timestamp failed for Tx with"
38373+ "err code: %d", ret);
38374+ return ret;
38375+ }
38376+
38377+ ret = dpni_set_tx_conf_buffer_layout(dpni, CMD_PRI_LOW,
38378+ priv->token, &layout);
38379+ if (ret) {
38380+ PMD_DRV_LOG(ERR, "Disabling timestamp failed for Tx-conf with"
38381+ "err code: %d", ret);
38382+ return ret;
38383+ }
38384+
38385+ return ret;
38386+}
38387+
38388+/* return 0 means link status changed, -1 means not changed */
38389+static int
38390+dpaa2_dev_get_link_info(struct rte_eth_dev *dev,
38391+ int wait_to_complete __rte_unused)
38392+{
38393+ int ret;
38394+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38395+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38396+ struct rte_eth_link link, old;
38397+ struct dpni_link_state state = {0};
38398+
38399+ if (dpni == NULL) {
38400+ PMD_DRV_LOG(ERR, "dpni is NULL");
38401+ return 0;
38402+ }
38403+ memset(&old, 0, sizeof(old));
38404+ rte_dpni_dev_atomic_read_link_status(dev, &old);
38405+
38406+ ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
38407+ if (ret < 0) {
38408+ PMD_DRV_LOG(ERR, "dpni_get_link_state");
38409+ return 0;
38410+ }
38411+
38412+ if (state.up == 0) {
38413+ rte_dpni_dev_atomic_write_link_status(dev, &link);
38414+ if (state.up == old.link_status)
38415+ return -1;
38416+ return 0;
38417+ }
38418+ link.link_status = state.up;
38419+ link.link_speed = state.rate;
38420+
38421+ if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
38422+ link.link_duplex = ETH_LINK_HALF_DUPLEX;
38423+ else
38424+ link.link_duplex = ETH_LINK_FULL_DUPLEX;
38425+
38426+ rte_dpni_dev_atomic_write_link_status(dev, &link);
38427+
38428+ if (link.link_status == old.link_status)
38429+ return -1;
38430+
38431+ return 0;
38432+}
38433+
38434+static
38435+void dpaa2_dev_stats_get(struct rte_eth_dev *dev,
38436+ struct rte_eth_stats *stats)
38437+{
38438+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38439+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38440+
38441+ int32_t retcode;
38442+ uint64_t value;
38443+
38444+ if (dpni == NULL) {
38445+ PMD_DRV_LOG(ERR, "dpni is NULL");
38446+ return;
38447+ }
38448+
38449+ if (!stats) {
38450+ PMD_DRV_LOG(ERR, "stats is NULL");
38451+ return;
38452+ }
38453+
38454+ retcode = dpni_get_counter(dpni, CMD_PRI_LOW, priv->token,
38455+ DPNI_CNT_ING_FRAME, &value);
38456+ if (retcode)
38457+ goto error;
38458+ stats->ipackets = value;
38459+ retcode = dpni_get_counter(dpni, CMD_PRI_LOW, priv->token,
38460+ DPNI_CNT_ING_BYTE, &value);
38461+ if (retcode)
38462+ goto error;
38463+ stats->ibytes = value;
38464+ retcode = dpni_get_counter(dpni, CMD_PRI_LOW, priv->token,
38465+ DPNI_CNT_ING_FRAME_DROP, &value);
38466+ if (retcode)
38467+ goto error;
38468+ stats->ierrors = value;
38469+ retcode = dpni_get_counter(dpni, CMD_PRI_LOW, priv->token,
38470+ DPNI_CNT_ING_FRAME_DISCARD, &value);
38471+ if (retcode)
38472+ goto error;
38473+ stats->ierrors = stats->ierrors + value;
38474+ retcode = dpni_get_counter(dpni, CMD_PRI_LOW, priv->token,
38475+ DPNI_CNT_EGR_FRAME, &value);
38476+ if (retcode)
38477+ goto error;
38478+ stats->opackets = value;
38479+ dpni_get_counter(dpni, CMD_PRI_LOW, priv->token,
38480+ DPNI_CNT_EGR_BYTE, &value);
38481+ if (retcode)
38482+ goto error;
38483+ stats->obytes = value;
38484+ retcode = dpni_get_counter(dpni, CMD_PRI_LOW, priv->token,
38485+ DPNI_CNT_EGR_FRAME_DISCARD, &value);
38486+ if (retcode)
38487+ goto error;
38488+ stats->oerrors = value;
38489+
38490+ return;
38491+
38492+error:
38493+ PMD_DRV_LOG(ERR, "Operation not completed:Error Code = %d\n", retcode);
38494+ return;
38495+};
38496+
38497+static
38498+void dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
38499+{
38500+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
38501+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
38502+
38503+ int32_t retcode;
38504+
38505+ if (dpni == NULL) {
38506+ PMD_DRV_LOG(ERR, "dpni is NULL");
38507+ return;
38508+ }
38509+
38510+ retcode = dpni_set_counter(dpni, CMD_PRI_LOW, priv->token,
38511+ DPNI_CNT_ING_FRAME, 0);
38512+ if (retcode)
38513+ goto error;
38514+ retcode = dpni_set_counter(dpni, CMD_PRI_LOW, priv->token,
38515+ DPNI_CNT_ING_BYTE, 0);
38516+ if (retcode)
38517+ goto error;
38518+ retcode = dpni_set_counter(dpni, CMD_PRI_LOW, priv->token,
38519+ DPNI_CNT_ING_BCAST_FRAME, 0);
38520+ if (retcode)
38521+ goto error;
38522+ retcode = dpni_set_counter(dpni, CMD_PRI_LOW, priv->token,
38523+ DPNI_CNT_ING_BCAST_BYTES, 0);
38524+ if (retcode)
38525+ goto error;
38526+ retcode = dpni_set_counter(dpni, CMD_PRI_LOW, priv->token,
38527+ DPNI_CNT_ING_MCAST_FRAME, 0);
38528+ if (retcode)
38529+ goto error;
38530+ retcode = dpni_set_counter(dpni, CMD_PRI_LOW, priv->token,
38531+ DPNI_CNT_ING_MCAST_BYTE, 0);
38532+ if (retcode)
38533+ goto error;
38534+ retcode = dpni_set_counter(dpni, CMD_PRI_LOW, priv->token,
38535+ DPNI_CNT_ING_FRAME_DROP, 0);
38536+ if (retcode)
38537+ goto error;
38538+ retcode = dpni_set_counter(dpni, CMD_PRI_LOW, priv->token,
38539+ DPNI_CNT_ING_FRAME_DISCARD, 0);
38540+ if (retcode)
38541+ goto error;
38542+ retcode = dpni_set_counter(dpni, CMD_PRI_LOW, priv->token,
38543+ DPNI_CNT_EGR_FRAME, 0);
38544+ if (retcode)
38545+ goto error;
38546+ retcode = dpni_set_counter(dpni, CMD_PRI_LOW, priv->token,
38547+ DPNI_CNT_EGR_BYTE, 0);
38548+ if (retcode)
38549+ goto error;
38550+ retcode = dpni_set_counter(dpni, CMD_PRI_LOW, priv->token,
38551+ DPNI_CNT_EGR_FRAME_DISCARD, 0);
38552+ if (retcode)
38553+ goto error;
38554+
38555+ return;
38556+
38557+error:
38558+ PMD_DRV_LOG(ERR, "Operation not completed:Error Code = %d\n", retcode);
38559+ return;
38560+};
38561+
38562+static struct eth_dev_ops ops = {
38563+ .dev_configure = dpaa2_eth_dev_configure,
38564+ .dev_start = dpaa2_dev_start,
38565+ .dev_stop = dpaa2_dev_stop,
38566+ .dev_close = dpaa2_dev_close,
38567+ .promiscuous_enable = dpaa2_dev_promiscuous_enable,
38568+ .promiscuous_disable = dpaa2_dev_promiscuous_disable,
38569+ .allmulticast_enable = dpaa2_dev_allmulticast_enable,
38570+ .allmulticast_disable = dpaa2_dev_allmulticast_disable,
38571+ /* .dev_set_link_up = ixgbe_dev_set_link_up, */
38572+ /* .dev_set_link_down = ixgbe_dev_set_link_down, */
38573+ .link_update = dpaa2_dev_get_link_info,
38574+ .stats_get = dpaa2_dev_stats_get,
38575+ /* .xstats_get = ixgbe_dev_xstats_get, */
38576+ .stats_reset = dpaa2_dev_stats_reset,
38577+ /* .xstats_reset = ixgbe_dev_xstats_reset, */
38578+ /* .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set, */
38579+ .dev_infos_get = dpaa2_eth_dev_info,
38580+ .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
38581+ .mtu_set = dpaa2_dev_mtu_set,
38582+ .vlan_filter_set = dpaa2_vlan_filter_set,
38583+/* .vlan_tpid_set = i40e_vlan_tpid_set, */
38584+ .vlan_offload_set = dpaa2_vlan_offload_set,
38585+/* .vlan_strip_queue_set = i40e_vlan_strip_queue_set, */
38586+/* .vlan_pvid_set = i40e_vlan_pvid_set, */
38587+/* .rx_queue_start = i40e_dev_rx_queue_start, */
38588+/* .rx_queue_stop = i40e_dev_rx_queue_stop, */
38589+/* .tx_queue_start = i40e_dev_tx_queue_start, */
38590+/* .tx_queue_stop = i40e_dev_tx_queue_stop, */
38591+ .rx_queue_setup = dpaa2_rx_queue_setup,
38592+/* .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable, */
38593+/* .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable, */
38594+/* .rx_queue_release = i40e_dev_rx_queue_release, */
38595+/* .rx_queue_count = i40e_dev_rx_queue_count, */
38596+ .tx_queue_setup = dpaa2_tx_queue_setup,
38597+/* .tx_queue_release = i40e_dev_tx_queue_release, */
38598+/* .dev_led_on = i40e_dev_led_on, */
38599+/* .dev_led_off = i40e_dev_led_off, */
38600+/* .flow_ctrl_get = i40e_flow_ctrl_get, */
38601+/* .flow_ctrl_set = i40e_flow_ctrl_set, */
38602+/* .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set, */
38603+ .mac_addr_add = dpaa2_dev_add_mac_addr,
38604+ .mac_addr_remove = dpaa2_dev_remove_mac_addr,
38605+/* .reta_update = i40e_dev_rss_reta_update, */
38606+/* .reta_query = i40e_dev_rss_reta_query, */
38607+/* .rss_hash_update = i40e_dev_rss_hash_update, */
38608+/* .rss_hash_conf_get = i40e_dev_rss_hash_conf_get, */
38609+/* .filter_ctrl = i40e_dev_filter_ctrl, */
38610+/* .rxq_info_get = i40e_rxq_info_get, */
38611+/* .txq_info_get = i40e_txq_info_get, */
38612+/* .mirror_rule_set = i40e_mirror_rule_set, */
38613+/* .mirror_rule_reset = i40e_mirror_rule_reset, */
38614+ .timesync_enable = dpaa2_timestamp_enable,
38615+ .timesync_disable = dpaa2_timestamp_disable,
38616+/* .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp, */
38617+/* .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp, */
38618+/* .get_dcb_info = i40e_dev_get_dcb_info, */
38619+/* .timesync_adjust_time = i40e_timesync_adjust_time, */
38620+/* .timesync_read_time = i40e_timesync_read_time, */
38621+/* .timesync_write_time = i40e_timesync_write_time, */
38622+/* .get_reg_length = i40e_get_reg_length, */
38623+/* .get_reg = i40e_get_regs, */
38624+/* .get_eeprom_length = i40e_get_eeprom_length, */
38625+/* .get_eeprom = i40e_get_eeprom, */
38626+ .mac_addr_set = dpaa2_dev_set_mac_addr,
38627+};
38628+
38629+static int
38630+dpaa2_dev_init(struct rte_eth_dev *eth_dev)
38631+{
38632+ struct rte_eth_dev_data *data = eth_dev->data;
38633+ struct fsl_mc_io *dpni_dev;
38634+ struct dpni_attr attr;
38635+ struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
38636+ struct dpni_buffer_layout layout;
38637+ int i, ret, hw_id = eth_dev->pci_dev->addr.devid;
38638+ struct dpni_extended_cfg *ext_cfg = NULL;
38639+ int tot_size;
38640+
38641+ PMD_INIT_FUNC_TRACE();
38642+
38643+ dpni_dev = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
38644+ if (!dpni_dev) {
38645+ PMD_DRV_LOG(ERR, "malloc failed for dpni device\n");
38646+ return -1;
38647+ }
38648+
38649+ dpni_dev->regs = mcp_ptr_list[0];
38650+ ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
38651+ if (ret) {
38652+ PMD_DRV_LOG(ERR, "Failure in opening dpni@%d device with"
38653+ "error code %d\n", hw_id, ret);
38654+ return -1;
38655+ }
38656+
38657+ /* Clean the device first */
38658+ ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
38659+ if (ret) {
38660+ PMD_DRV_LOG(ERR, "Failure cleaning dpni@%d device with"
38661+ "error code %d\n", hw_id, ret);
38662+ return -1;
38663+ }
38664+
38665+ ext_cfg = (struct dpni_extended_cfg *)rte_malloc(NULL, 256,
38666+ RTE_CACHE_LINE_SIZE);
38667+ if (!ext_cfg) {
38668+ PMD_DRV_LOG(ERR, "No data memory\n");
38669+ return -1;
38670+ }
38671+ attr.ext_cfg_iova = (uint64_t)(DPAA2_VADDR_TO_IOVA(ext_cfg));
38672+
38673+ ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
38674+ if (ret) {
38675+ PMD_DRV_LOG(ERR, "Failure in getting dpni@%d attribute, "
38676+ "error code %d\n", hw_id, ret);
38677+ return -1;
38678+ }
38679+
38680+ priv->num_tc = attr.max_tcs;
38681+ for (i = 0; i < attr.max_tcs; i++) {
38682+ priv->num_dist_per_tc[i] = ext_cfg->tc_cfg[i].max_dist;
38683+ priv->nb_rx_queues += priv->num_dist_per_tc[i];
38684+ /* todo - currently we only support one TC index in RX side */
38685+ break;
38686+ }
38687+ if (attr.max_tcs == 1)
38688+ priv->nb_tx_queues = attr.max_senders;
38689+ else
38690+ priv->nb_tx_queues = attr.max_tcs;
38691+ PMD_DRV_LOG(INFO, "num_tc %d\n", priv->num_tc);
38692+ PMD_DRV_LOG(INFO, "nb_rx_queues %d\n", priv->nb_rx_queues);
38693+
38694+ eth_dev->data->nb_rx_queues = priv->nb_rx_queues;
38695+ eth_dev->data->nb_tx_queues = priv->nb_tx_queues;
38696+
38697+ priv->hw = dpni_dev;
38698+ priv->hw_id = hw_id;
38699+ priv->options = attr.options;
38700+
38701+ priv->max_unicast_filters = attr.max_unicast_filters;
38702+ priv->max_multicast_filters = attr.max_multicast_filters;
38703+
38704+ if (attr.options & DPNI_OPT_VLAN_FILTER)
38705+ priv->max_vlan_filters = attr.max_vlan_filters;
38706+ else
38707+ priv->max_vlan_filters = 0;
38708+
38709+ ret = dpaa2_alloc_rx_tx_queues(eth_dev);
38710+ if (ret) {
38711+ PMD_DRV_LOG(ERR, "dpaa2_alloc_rx_tx_queuesFailed\n");
38712+ return -1;
38713+ }
38714+
38715+ data->mac_addrs = (struct ether_addr *)malloc(sizeof(struct ether_addr));
38716+
38717+ /* Allocate memory for storing MAC addresses */
38718+ eth_dev->data->mac_addrs = rte_zmalloc("dpni",
38719+ ETHER_ADDR_LEN * attr.max_unicast_filters, 0);
38720+ if (eth_dev->data->mac_addrs == NULL) {
38721+ PMD_DRV_LOG(ERR, "Failed to allocate %d bytes needed to "
38722+ "store MAC addresses",
38723+ ETHER_ADDR_LEN * attr.max_unicast_filters);
38724+ return -ENOMEM;
38725+ }
38726+
38727+ ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
38728+ priv->token,
38729+ (uint8_t *)(data->mac_addrs[0].addr_bytes));
38730+ if (ret) {
38731+ PMD_DRV_LOG(ERR, "DPNI get mac address failed:"
38732+ " Error Code = %d\n", ret);
38733+ return -1;
38734+ }
38735+
38736+ PMD_DRV_LOG(INFO, "Adding Broadcast Address...\n");
38737+ memset(data->mac_addrs[1].addr_bytes, 0xff, ETH_ADDR_LEN);
38738+ ret = dpni_add_mac_addr(dpni_dev, CMD_PRI_LOW,
38739+ priv->token,
38740+ (uint8_t *)(data->mac_addrs[1].addr_bytes));
38741+ if (ret) {
38742+ PMD_DRV_LOG(ERR, "DPNI set broadcast mac address failed:"
38743+ " Error Code = %0x\n", ret);
38744+ return -1;
38745+ }
38746+
38747+ /* ... rx buffer layout ... */
38748+ /*Check alignment for buffer layouts first*/
38749+ tot_size = DPAA2_FD_PTA_SIZE + DPAA2_MBUF_HW_ANNOTATION + DPAA2_RES/* dummy */ +
38750+ 128 /*RTE_MUF */ + (128+DPAA2_RES)/*VLIB*/ + RTE_PKTMBUF_HEADROOM;
38751+ tot_size = DPAA2_ALIGN_ROUNDUP(tot_size,
38752+ DPAA2_PACKET_LAYOUT_ALIGN);
38753+
38754+ memset(&layout, 0, sizeof(struct dpni_buffer_layout));
38755+ layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
38756+ DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
38757+ DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM |
38758+ DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
38759+
38760+ layout.pass_frame_status = 1;
38761+ layout.data_head_room =
38762+ (tot_size - (DPAA2_FD_PTA_SIZE + DPAA2_MBUF_HW_ANNOTATION));
38763+ layout.private_data_size = DPAA2_FD_PTA_SIZE;
38764+ layout.pass_parser_result = 1;
38765+
38766+ ret = dpni_set_rx_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
38767+ &layout);
38768+ if (ret) {
38769+ printf("Err(%d) in setting rx buffer layout\n", ret);
38770+ return -1;
38771+ }
38772+
38773+ /* ... tx buffer layout ... */
38774+ memset(&layout, 0, sizeof(struct dpni_buffer_layout));
38775+ layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
38776+ layout.pass_frame_status = 1;
38777+ ret = dpni_set_tx_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, &layout);
38778+ if (ret) {
38779+ printf("Error (%d) in setting tx buffer layout\n", ret);
38780+ return -1;
38781+ }
38782+
38783+ /* ... tx-conf and error buffer layout ... */
38784+ memset(&layout, 0, sizeof(struct dpni_buffer_layout));
38785+ layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
38786+ layout.pass_frame_status = 1;
38787+ ret = dpni_set_tx_conf_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, &layout);
38788+ if (ret) {
38789+ printf("Error (%d) in setting tx-conf buffer layout\n", ret);
38790+ return -1;
38791+ }
38792+
38793+ /* TODO - Set the MTU if required */
38794+
38795+ eth_dev->dev_ops = &ops;
38796+ eth_dev->rx_pkt_burst = eth_dpaa2_prefetch_rx;/*eth_dpaa2_rx;*/
38797+ eth_dev->tx_pkt_burst = eth_dpaa2_tx;
38798+
38799+ rte_free(ext_cfg);
38800+
38801+ return 0;
38802+}
38803+
38804+static struct eth_driver rte_dpaa2_dpni = {
38805+ {
38806+ .name = "rte_dpaa2_dpni",
38807+ .id_table = pci_id_dpaa2_map,
38808+ },
38809+ .eth_dev_init = dpaa2_dev_init,
38810+ .dev_private_size = sizeof(struct dpaa2_dev_priv),
38811+};
38812+
38813+static int
38814+rte_pmd_dpaa2_devinit(
38815+ const char *name __rte_unused,
38816+ const char *params __rte_unused)
38817+{
38818+ printf("Initializing dpaa2_pmd for %s\n", name);
38819+ rte_eth_driver_register(&rte_dpaa2_dpni);
38820+
38821+ return 0;
38822+}
38823+
38824+static struct rte_driver pmd_dpaa2_drv = {
38825+ .name = "dpaa2_pmd",
38826+ .type = PMD_PDEV,
38827+ .init = rte_pmd_dpaa2_devinit,
38828+};
38829+
38830+PMD_REGISTER_DRIVER(pmd_dpaa2_drv);
38831diff --git a/drivers/net/dpaa2/rte_eth_dpni_annot.h b/drivers/net/dpaa2/rte_eth_dpni_annot.h
38832new file mode 100644
38833index 0000000..00fac9b
38834--- /dev/null
38835+++ b/drivers/net/dpaa2/rte_eth_dpni_annot.h
38836@@ -0,0 +1,311 @@
38837+/*-
38838+ * BSD LICENSE
38839+ *
38840+ * Copyright (c) 2014 Freescale Semiconductor, Inc. All rights reserved.
38841+ *
38842+ * Redistribution and use in source and binary forms, with or without
38843+ * modification, are permitted provided that the following conditions
38844+ * are met:
38845+ *
38846+ * * Redistributions of source code must retain the above copyright
38847+ * notice, this list of conditions and the following disclaimer.
38848+ * * Redistributions in binary form must reproduce the above copyright
38849+ * notice, this list of conditions and the following disclaimer in
38850+ * the documentation and/or other materials provided with the
38851+ * distribution.
38852+ * * Neither the name of Freescale Semiconductor, Inc nor the names of its
38853+ * contributors may be used to endorse or promote products derived
38854+ * from this software without specific prior written permission.
38855+ *
38856+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38857+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38858+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38859+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38860+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38861+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
38862+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38863+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38864+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38865+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38866+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38867+ */
38868+
38869+/**
38870+ * @file
38871+ *
38872+ * DPNI packet parse results - implementation internal
38873+ */
38874+
38875+#ifndef RTE_ETH_DPNI_ANNOT_H_
38876+#define RTE_ETH_DPNI_ANNOT_H_
38877+
38878+#ifdef __cplusplus
38879+extern "C" {
38880+#endif
38881+
38882+/* Annotation valid bits in FD FRC */
38883+#define DPAA2_FD_FRC_FASV 0x8000
38884+#define DPAA2_FD_FRC_FAEADV 0x4000
38885+#define DPAA2_FD_FRC_FAPRV 0x2000
38886+#define DPAA2_FD_FRC_FAIADV 0x1000
38887+#define DPAA2_FD_FRC_FASWOV 0x0800
38888+#define DPAA2_FD_FRC_FAICFDV 0x0400
38889+
38890+/* Annotation bits in FD CTRL */
38891+#define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */
38892+#define DPAA2_FD_CTRL_PTA 0x00800000
38893+#define DPAA2_FD_CTRL_PTV1 0x00400000
38894+
38895+/* Frame annotation status */
38896+struct dpaa2_fas {
38897+ uint8_t reserved;
38898+ uint8_t ppid;
38899+ __le16 ifpid;
38900+ __le32 status;
38901+} __packed;
38902+
38903+/**
38904+ * Internal Packet annotation header
38905+ */
38906+struct pkt_annotation {
38907+ /**< word1: Frame Annotation Status (8 bytes)*/
38908+ uint64_t word1;
38909+ /**< word2: Time Stamp (8 bytes)*/
38910+ uint64_t word2;
38911+ /**< word3: Next Hdr + FAF Extension + FAF (2 + 2 + 4 bytes)*/
38912+ uint64_t word3;
38913+ /**< word4: Frame Annotation Flags-FAF (8 bytes) */
38914+ uint64_t word4;
38915+ /**< word5:
38916+ ShimOffset_1 + ShimOffset_2 + IPPIDOffset + EthOffset +
38917+ LLC+SNAPOffset + VLANTCIOffset_1 + VLANTCIOffset_n +
38918+ LastETypeOffset (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 bytes)
38919+ */
38920+ uint64_t word5;
38921+ /**< word6:
38922+ PPPoEOffset + MPLSOffset_1 + MPLSOffset_n + ARPorIPOffset_1
38923+ + IPOffset_norMInEncapO + GREOffset + L4Offset +
38924+ GTPorESPorIPSecOffset(1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 bytes)
38925+ */
38926+ uint64_t word6;
38927+ /**< word7:
38928+ RoutingHdrOfset1 + RoutingHdrOfset2 + NxtHdrOffset + IPv6FragOffset +
38929+ GrossRunningSum + RunningSum(1 + 1 + 1 + 1 + 2 + 2 bytes)
38930+ */
38931+ uint64_t word7;
38932+ /**< word8:
38933+ ParseErrorcode + Soft Parsing Context (1 + 7 bytes)
38934+ */
38935+ uint64_t word8; /**< Layer 4 length */
38936+};
38937+
38938+/**
38939+ * Internal Macros to get/set Packet annotation header
38940+ */
38941+
38942+/** General Macro to define a particular bit position*/
38943+#define BIT_POS(x) ((uint64_t)1 << ((x)))
38944+/** Set a bit in the variable */
38945+#define BIT_SET_AT_POS(var, pos) (var |= pos)
38946+/** Reset the bit in the variable */
38947+#define BIT_RESET_AT_POS(var, pos) (var &= ~(pos))
38948+/** Check the bit is set in the variable */
38949+#define BIT_ISSET_AT_POS(var, pos) ((var & pos) ? 1 : 0)
38950+/**
38951+ * Macrso to define bit position in word3
38952+ */
38953+#define NEXT_HDR(var) ((uint64_t)var & 0xFFFF000000000000)
38954+#define FAF_EXTN_IPV6_ROUTE_HDR_PRESENT(var) BIT_POS(16)
38955+#define FAF_EXTN_RESERVED(var) ((uint64_t)var & 0x00007FFF00000000)
38956+#define FAF_USER_DEFINED_RESERVED(var) ((uint64_t)var & 0x00000000FF000000)
38957+#define SHIM_SHELL_SOFT_PARSING_ERRROR BIT_POS(23)
38958+#define PARSING_ERROR BIT_POS(22)
38959+#define L2_ETH_MAC_PRESENT BIT_POS(21)
38960+#define L2_ETH_MAC_UNICAST BIT_POS(20)
38961+#define L2_ETH_MAC_MULTICAST BIT_POS(19)
38962+#define L2_ETH_MAC_BROADCAST BIT_POS(18)
38963+#define L2_ETH_FRAME_IS_BPDU BIT_POS(17)
38964+#define L2_ETH_FCOE_PRESENT BIT_POS(16)
38965+#define L2_ETH_FIP_PRESENT BIT_POS(15)
38966+#define L2_ETH_PARSING_ERROR BIT_POS(14)
38967+#define L2_LLC_SNAP_PRESENT BIT_POS(13)
38968+#define L2_UNKNOWN_LLC_OUI BIT_POS(12)
38969+#define L2_LLC_SNAP_ERROR BIT_POS(11)
38970+#define L2_VLAN_1_PRESENT BIT_POS(10)
38971+#define L2_VLAN_N_PRESENT BIT_POS(9)
38972+#define L2_VLAN_CFI_BIT_PRESENT BIT_POS(8)
38973+#define L2_VLAN_PARSING_ERROR BIT_POS(7)
38974+#define L2_PPPOE_PPP_PRESENT BIT_POS(6)
38975+#define L2_PPPOE_PPP_PARSING_ERROR BIT_POS(5)
38976+#define L2_MPLS_1_PRESENT BIT_POS(4)
38977+#define L2_MPLS_N_PRESENT BIT_POS(3)
38978+#define L2_MPLS_PARSING_ERROR BIT_POS(2)
38979+#define L2_ARP_PRESENT BIT_POS(1)
38980+#define L2_ARP_PARSING_ERROR BIT_POS(0)
38981+/**
38982+ * Macrso to define bit position in word4
38983+ */
38984+#define L2_UNKNOWN_PROTOCOL BIT_POS(63)
38985+#define L2_SOFT_PARSING_ERROR BIT_POS(62)
38986+#define L3_IPV4_1_PRESENT BIT_POS(61)
38987+#define L3_IPV4_1_UNICAST BIT_POS(60)
38988+#define L3_IPV4_1_MULTICAST BIT_POS(59)
38989+#define L3_IPV4_1_BROADCAST BIT_POS(58)
38990+#define L3_IPV4_N_PRESENT BIT_POS(57)
38991+#define L3_IPV4_N_UNICAST BIT_POS(56)
38992+#define L3_IPV4_N_MULTICAST BIT_POS(55)
38993+#define L3_IPV4_N_BROADCAST BIT_POS(54)
38994+#define L3_IPV6_1_PRESENT BIT_POS(53)
38995+#define L3_IPV6_1_UNICAST BIT_POS(52)
38996+#define L3_IPV6_1_MULTICAST BIT_POS(51)
38997+#define L3_IPV6_N_PRESENT BIT_POS(50)
38998+#define L3_IPV6_N_UNICAST BIT_POS(49)
38999+#define L3_IPV6_N_MULTICAST BIT_POS(48)
39000+#define L3_IP_1_OPT_PRESENT BIT_POS(47)
39001+#define L3_IP_1_UNKNOWN_PROTOCOL BIT_POS(46)
39002+#define L3_IP_1_MORE_FRAGMENT BIT_POS(45)
39003+#define L3_IP_1_FIRST_FRAGMENT BIT_POS(44)
39004+#define L3_IP_1_PARSING_ERROR BIT_POS(43)
39005+#define L3_IP_N_OPT_PRESENT BIT_POS(42)
39006+#define L3_IP_N_UNKNOWN_PROTOCOL BIT_POS(41)
39007+#define L3_IP_N_MORE_FRAGMENT BIT_POS(40)
39008+#define L3_IP_N_FIRST_FRAGMENT BIT_POS(39)
39009+#define L3_PROTO_ICMP_PRESENT BIT_POS(38)
39010+#define L3_PROTO_IGMP_PRESENT BIT_POS(37)
39011+#define L3_PROTO_ICMPV6_PRESENT BIT_POS(36)
39012+#define L3_PROTO_UDP_LIGHT_PRESENT BIT_POS(35)
39013+#define L3_IP_N_PARSING_ERROR BIT_POS(34)
39014+#define L3_MIN_ENCAP_PRESENT BIT_POS(33)
39015+#define L3_MIN_ENCAP_SBIT_PRESENT BIT_POS(32)
39016+#define L3_MIN_ENCAP_PARSING_ERROR BIT_POS(31)
39017+#define L3_PROTO_GRE_PRESENT BIT_POS(30)
39018+#define L3_PROTO_GRE_RBIT_PRESENT BIT_POS(29)
39019+#define L3_PROTO_GRE_PARSING_ERROR BIT_POS(28)
39020+#define L3_IP_UNKNOWN_PROTOCOL BIT_POS(27)
39021+#define L3_SOFT_PARSING_ERROR BIT_POS(26)
39022+#define L3_PROTO_UDP_PRESENT BIT_POS(25)
39023+#define L3_PROTO_UDP_PARSING_ERROR BIT_POS(24)
39024+#define L3_PROTO_TCP_PRESENT BIT_POS(23)
39025+#define L3_PROTO_TCP_OPT_PRESENT BIT_POS(22)
39026+#define L3_PROTO_TCP_CTRL_BIT_6_TO_11_PRESENT BIT_POS(21)
39027+#define L3_PROTO_TCP_CTRL_BIT_3_TO_5_PRESENT BIT_POS(20)
39028+#define L3_PROTO_TCP_PARSING_ERROR BIT_POS(19)
39029+#define L3_PROTO_IPSEC_PRESENT BIT_POS(18)
39030+#define L3_PROTO_IPSEC_ESP_PRESENT BIT_POS(17)
39031+#define L3_PROTO_IPSEC_AH_PRESENT BIT_POS(16)
39032+#define L3_PROTO_IPSEC_PARSING_ERROR BIT_POS(15)
39033+#define L3_PROTO_SCTP_PRESENT BIT_POS(14)
39034+#define L3_PROTO_SCTP_PARSING_ERROR BIT_POS(13)
39035+#define L3_PROTO_DCCP_PRESENT BIT_POS(12)
39036+#define L3_PROTO_DCCP_PARSING_ERROR BIT_POS(11)
39037+#define L4_UNKNOWN_PROTOCOL BIT_POS(10)
39038+#define L4_SOFT_PARSING_ERROR BIT_POS(9)
39039+#define L3_PROTO_GTP_PRESENT BIT_POS(8)
39040+#define L3_PROTO_GTP_PARSING_ERROR BIT_POS(7)
39041+#define L3_PROTO_ESP_PRESENT BIT_POS(6)
39042+#define L3_PROTO_ESP_PARSING_ERROR BIT_POS(5)
39043+#define L3_PROTO_ISCSI_PRESENT BIT_POS(4)
39044+#define L3_PROTO_CAPWAN__CTRL_PRESENT BIT_POS(3)
39045+#define L3_PROTO_CAPWAN__DATA_PRESENT BIT_POS(2)
39046+#define L5_SOFT_PARSING_ERROR BIT_POS(1)
39047+#define L3_IPV6_ROUTE_HDR_PRESENT BIT_POS(0)
39048+
39049+/**
39050+ * Macros to get values in word5
39051+ */
39052+#define SHIM_OFFSET_1(var) ((uint64_t)var & 0xFF00000000000000)
39053+#define SHIM_OFFSET_2(var) ((uint64_t)var & 0x00FF000000000000)
39054+#define IP_PID_OFFSET(var) ((uint64_t)var & 0x0000FF0000000000)
39055+#define ETH_OFFSET(var) ((uint64_t)var & 0x000000FF00000000)
39056+#define LLC_SNAP_OFFSET(var) ((uint64_t)var & 0x00000000FF000000)
39057+#define VLAN_TCI_OFFSET_1(var) ((uint64_t)var & 0x0000000000FF0000)
39058+#define VLAN_TCI_OFFSET_N(var) ((uint64_t)var & 0x000000000000FF00)
39059+#define LAST_ETYPE_OFFSET(var) ((uint64_t)var & 0x00000000000000FF)
39060+
39061+/**
39062+ * Macros to get values in word6
39063+ */
39064+#define PPPOE_OFFSET(var) ((uint64_t)var & 0xFF00000000000000)
39065+#define MPLS_OFFSET_1(var) ((uint64_t)var & 0x00FF000000000000)
39066+#define MPLS_OFFSET_N(var) ((uint64_t)var & 0x0000FF0000000000)
39067+#define ARP_OR_IP_OFFSET_1(var) ((uint64_t)var & 0x000000FF00000000)
39068+#define IP_N_OR_MIN_ENCAP_OFFSET(var) ((uint64_t)var & 0x00000000FF000000)
39069+#define GRE_OFFSET(var) ((uint64_t)var & 0x0000000000FF0000)
39070+#define L4_OFFSET(var) ((uint64_t)var & 0x000000000000FF00)
39071+#define GTP_OR_ESP_OR_IPSEC_OFFSET(var) ((uint64_t)var & 0x00000000000000FF)
39072+
39073+/**
39074+ * Macros to get values in word7
39075+ */
39076+#define IPV6_ROUTING_HDR_OFFSET_1(var) ((uint64_t)var & 0xFF00000000000000)
39077+#define IPV6_ROUTING_HDR_OFFSET_2(var) ((uint64_t)var & 0x00FF000000000000)
39078+#define NEXT_HDR_OFFSET(var) ((uint64_t)var & 0x0000FF0000000000)
39079+#define IPV6_FRAG_OFFSET(var) ((uint64_t)var & 0x000000FF00000000)
39080+#define GROSS_RUNNING_SUM(var) ((uint64_t)var & 0x00000000FFFF0000)
39081+#define RUNNING_SUM(var) ((uint64_t)var & 0x000000000000FFFF)
39082+
39083+/**
39084+ * Macros to get values in word8
39085+ */
39086+#define PARSE_ERROR_CODE(var) ((uint64_t)var & 0xFF00000000000000)
39087+#define SOFT_PARSING_CONTEXT(var) ((uint64_t)var & 0x00FFFFFFFFFFFFFF)
39088+
39089+/* Debug frame, otherwise supposed to be discarded */
39090+#define DPAA2_ETH_FAS_DISC 0x80000000
39091+/* MACSEC frame */
39092+#define DPAA2_ETH_FAS_MS 0x40000000
39093+#define DPAA2_ETH_FAS_PTP 0x08000000
39094+/* Ethernet multicast frame */
39095+#define DPAA2_ETH_FAS_MC 0x04000000
39096+/* Ethernet broadcast frame */
39097+#define DPAA2_ETH_FAS_BC 0x02000000
39098+#define DPAA2_ETH_FAS_KSE 0x00040000
39099+#define DPAA2_ETH_FAS_EOFHE 0x00020000
39100+#define DPAA2_ETH_FAS_MNLE 0x00010000
39101+#define DPAA2_ETH_FAS_TIDE 0x00008000
39102+#define DPAA2_ETH_FAS_PIEE 0x00004000
39103+/* Frame length error */
39104+#define DPAA2_ETH_FAS_FLE 0x00002000
39105+/* Frame physical error; our favourite pastime */
39106+#define DPAA2_ETH_FAS_FPE 0x00001000
39107+#define DPAA2_ETH_FAS_PTE 0x00000080
39108+#define DPAA2_ETH_FAS_ISP 0x00000040
39109+#define DPAA2_ETH_FAS_PHE 0x00000020
39110+#define DPAA2_ETH_FAS_BLE 0x00000010
39111+/* L3 csum validation performed */
39112+#define DPAA2_ETH_FAS_L3CV 0x00000008
39113+/* L3 csum error */
39114+#define DPAA2_ETH_FAS_L3CE 0x00000004
39115+/* L4 csum validation performed */
39116+#define DPAA2_ETH_FAS_L4CV 0x00000002
39117+/* L4 csum error */
39118+#define DPAA2_ETH_FAS_L4CE 0x00000001
39119+
39120+/* These bits always signal errors */
39121+#define DPAA2_ETH_RX_ERR_MASK (DPAA2_ETH_FAS_KSE | \
39122+ DPAA2_ETH_FAS_EOFHE | \
39123+ DPAA2_ETH_FAS_MNLE | \
39124+ DPAA2_ETH_FAS_TIDE | \
39125+ DPAA2_ETH_FAS_PIEE | \
39126+ DPAA2_ETH_FAS_FLE | \
39127+ DPAA2_ETH_FAS_FPE | \
39128+ DPAA2_ETH_FAS_PTE | \
39129+ DPAA2_ETH_FAS_ISP | \
39130+ DPAA2_ETH_FAS_PHE | \
39131+ DPAA2_ETH_FAS_BLE | \
39132+ DPAA2_ETH_FAS_L3CE | \
39133+ DPAA2_ETH_FAS_L4CE)
39134+/* Unsupported features in the ingress */
39135+#define DPAA2_ETH_RX_UNSUPP_MASK DPAA2_ETH_FAS_MS
39136+/* Tx errors */
39137+#define DPAA2_ETH_TXCONF_ERR_MASK (DPAA2_ETH_FAS_KSE | \
39138+ DPAA2_ETH_FAS_EOFHE | \
39139+ DPAA2_ETH_FAS_MNLE | \
39140+ DPAA2_ETH_FAS_TIDE)
39141+
39142+
39143+#ifdef __cplusplus
39144+}
39145+#endif
39146+
39147+#endif
39148diff --git a/drivers/net/dpaa2/rte_pmd_dpaa2_version.map b/drivers/net/dpaa2/rte_pmd_dpaa2_version.map
39149new file mode 100644
39150index 0000000..349c6e1
39151--- /dev/null
39152+++ b/drivers/net/dpaa2/rte_pmd_dpaa2_version.map
39153@@ -0,0 +1,4 @@
39154+DPDK_16.04 {
39155+
39156+ local: *;
39157+};
39158diff --git a/lib/librte_eal/common/eal_private.h b/lib/librte_eal/common/eal_private.h
39159index 2342fa1..8f27836 100644
39160--- a/lib/librte_eal/common/eal_private.h
39161+++ b/lib/librte_eal/common/eal_private.h
39162@@ -328,4 +328,16 @@ int rte_eal_hugepage_init(void);
39163 */
39164 int rte_eal_hugepage_attach(void);
39165
39166+#ifdef RTE_LIBRTE_DPAA2_PMD
39167+/**
39168+ * Initialize any soc init related functions if any before thread creation
39169+ */
39170+int rte_eal_soc_pre_init(void);
39171+
39172+/**
39173+ * Initialize any soc init related functions if any after thread creation
39174+ */
39175+int rte_eal_soc_post_init(void);
39176+#endif
39177+
39178 #endif /* _EAL_PRIVATE_H_ */
39179diff --git a/lib/librte_eal/linuxapp/eal/Makefile b/lib/librte_eal/linuxapp/eal/Makefile
39180index e109361..abcd02c 100644
39181--- a/lib/librte_eal/linuxapp/eal/Makefile
39182+++ b/lib/librte_eal/linuxapp/eal/Makefile
39183@@ -47,6 +47,13 @@ CFLAGS += -I$(RTE_SDK)/lib/librte_eal/common/include
39184 CFLAGS += -I$(RTE_SDK)/lib/librte_ring
39185 CFLAGS += -I$(RTE_SDK)/lib/librte_mempool
39186 CFLAGS += -I$(RTE_SDK)/lib/librte_ivshmem
39187+ifeq ($(CONFIG_RTE_LIBRTE_DPAA2_PMD),y)
39188+CFLAGS += -I$(RTE_SDK)/lib/librte_mbuf
39189+CFLAGS += -I$(RTE_SDK)/drivers/net/dpaa2/qbman/include
39190+CFLAGS += -I$(RTE_SDK)/drivers/net/dpaa2/qbman/include/drivers
39191+CFLAGS += -I$(RTE_SDK)/drivers/net/dpaa2/mc
39192+CFLAGS += -I$(RTE_SDK)/drivers/net/dpaa2/driver
39193+endif
39194 CFLAGS += $(WERROR_FLAGS) -O3
39195
39196 LDLIBS += -ldl
39197@@ -72,6 +79,10 @@ SRCS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += eal_lcore.c
39198 SRCS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += eal_timer.c
39199 SRCS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += eal_interrupts.c
39200 SRCS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += eal_alarm.c
39201+ifeq ($(CONFIG_RTE_LIBRTE_DPAA2_PMD),y)
39202+SRCS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += eal_soc.c
39203+SRCS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += eal_vfio_fsl_mc.c
39204+endif
39205 ifeq ($(CONFIG_RTE_LIBRTE_IVSHMEM),y)
39206 SRCS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += eal_ivshmem.c
39207 endif
39208diff --git a/lib/librte_eal/linuxapp/eal/eal.c b/lib/librte_eal/linuxapp/eal/eal.c
39209index 8aafd51..b2327c7 100644
39210--- a/lib/librte_eal/linuxapp/eal/eal.c
39211+++ b/lib/librte_eal/linuxapp/eal/eal.c
39212@@ -805,6 +805,11 @@ rte_eal_init(int argc, char **argv)
39213 if (rte_eal_tailqs_init() < 0)
39214 rte_panic("Cannot init tail queues for objects\n");
39215
39216+#ifdef RTE_LIBRTE_DPAA2_PMD
39217+ if (rte_eal_soc_pre_init() < 0)
39218+ rte_panic("Cannot pre init soc\n");
39219+#endif
39220+
39221 #ifdef RTE_LIBRTE_IVSHMEM
39222 if (rte_eal_ivshmem_obj_init() < 0)
39223 rte_panic("Cannot init IVSHMEM objects\n");
39224@@ -874,6 +879,11 @@ rte_eal_init(int argc, char **argv)
39225 rte_eal_mp_remote_launch(sync_func, NULL, SKIP_MASTER);
39226 rte_eal_mp_wait_lcore();
39227
39228+#ifdef RTE_LIBRTE_DPAA2_PMD
39229+ if (rte_eal_soc_post_init() < 0)
39230+ rte_panic("Cannot post init soc\n");
39231+#endif
39232+
39233 /* Probe & Initialize PCI devices */
39234 if (rte_eal_pci_probe())
39235 rte_panic("Cannot probe PCI\n");
39236diff --git a/lib/librte_eal/linuxapp/eal/eal_soc.c b/lib/librte_eal/linuxapp/eal/eal_soc.c
39237new file mode 100644
39238index 0000000..32ae172
39239--- /dev/null
39240+++ b/lib/librte_eal/linuxapp/eal/eal_soc.c
39241@@ -0,0 +1,84 @@
39242+/*-
39243+ * BSD LICENSE
39244+ *
39245+ * Copyright(c) 2016 Freescale Semiconductor, Inc. All rights reserved.
39246+ * All rights reserved.
39247+ *
39248+ * Redistribution and use in source and binary forms, with or without
39249+ * modification, are permitted provided that the following conditions
39250+ * are met:
39251+ *
39252+ * * Redistributions of source code must retain the above copyright
39253+ * notice, this list of conditions and the following disclaimer.
39254+ * * Redistributions in binary form must reproduce the above copyright
39255+ * notice, this list of conditions and the following disclaimer in
39256+ * the documentation and/or other materials provided with the
39257+ * distribution.
39258+ * * Neither the name of Freescale Semiconductor, Inc or the names of its
39259+ * contributors may be used to endorse or promote products derived
39260+ * from this software without specific prior written permission.
39261+ *
39262+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39263+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39264+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39265+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39266+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39267+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39268+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39269+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39270+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39271+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39272+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39273+ */
39274+
39275+#include <unistd.h>
39276+#include <limits.h>
39277+#include <string.h>
39278+#include <dirent.h>
39279+
39280+#include <rte_log.h>
39281+#include <rte_eal.h>
39282+#include <rte_lcore.h>
39283+#include <rte_common.h>
39284+#include <rte_string_fns.h>
39285+#include <rte_debug.h>
39286+#include "eal_private.h"
39287+
39288+#ifdef RTE_LIBRTE_DPAA2_PMD
39289+#include "eal_vfio_fsl_mc.h"
39290+#endif
39291+
39292+
39293+#if (defined RTE_LIBRTE_DPAA_PMD)
39294+extern int usdpaa_pre_rte_eal_init(void);
39295+extern int usdpaa_post_rte_eal_init(void);
39296+#endif
39297+
39298+
39299+/* Initialize any soc init related functions if any before thread creation*/
39300+int
39301+rte_eal_soc_pre_init(void)
39302+{
39303+#ifdef RTE_LIBRTE_DPAA2_PMD
39304+ if (rte_eal_dpaa2_init() < 0)
39305+ RTE_LOG(WARNING, EAL, "Cannot init FSL_MC SCAN \n");
39306+#endif
39307+#if (defined RTE_LIBRTE_DPAA_PMD)
39308+ if (usdpaa_pre_rte_eal_init())
39309+ RTE_LOG(WARNING, EAL, "Cannot init FSL_DPAA \n");
39310+#endif
39311+ return 0;
39312+}
39313+
39314+/* Initialize any soc init related functions if any after thread creation*/
39315+int
39316+rte_eal_soc_post_init(void)
39317+{
39318+#if (defined RTE_LIBRTE_DPAA_PMD)
39319+ if (usdpaa_post_rte_eal_init()) {
39320+ RTE_LOG(WARNING, EAL, "dpaa1: usdpaa portal init failed\n");
39321+ }
39322+#endif
39323+ return 0;
39324+}
39325+
39326diff --git a/lib/librte_eal/linuxapp/eal/eal_vfio_fsl_mc.c b/lib/librte_eal/linuxapp/eal/eal_vfio_fsl_mc.c
39327new file mode 100644
39328index 0000000..c71d8d6
39329--- /dev/null
39330+++ b/lib/librte_eal/linuxapp/eal/eal_vfio_fsl_mc.c
39331@@ -0,0 +1,653 @@
39332+/*-
39333+ * BSD LICENSE
39334+ *
39335+ * Copyright(c) 2014 Freescale Semiconductor. All rights reserved.
39336+ * All rights reserved.
39337+ *
39338+ * Redistribution and use in source and binary forms, with or without
39339+ * modification, are permitted provided that the following conditions
39340+ * are met:
39341+ *
39342+ * * Redistributions of source code must retain the above copyright
39343+ * notice, this list of conditions and the following disclaimer.
39344+ * * Redistributions in binary form must reproduce the above copyright
39345+ * notice, this list of conditions and the following disclaimer in
39346+ * the documentation and/or other materials provided with the
39347+ * distribution.
39348+ * * Neither the name of Freescale Semiconductor nor the names of its
39349+ * contributors may be used to endorse or promote products derived
39350+ * from this software without specific prior written permission.
39351+ *
39352+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39353+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39354+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39355+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39356+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39357+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39358+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39359+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39360+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39361+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39362+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39363+ */
39364+
39365+#include <unistd.h>
39366+#include <stdio.h>
39367+#include <sys/types.h>
39368+#include <string.h>
39369+#include <stdlib.h>
39370+#include <fcntl.h>
39371+#include <errno.h>
39372+#include <sys/ioctl.h>
39373+#include <sys/stat.h>
39374+#include <sys/types.h>
39375+#include <sys/mman.h>
39376+#include <sys/vfs.h>
39377+#include <libgen.h>
39378+#include <dirent.h>
39379+
39380+#include "rte_pci.h"
39381+#include "eal_vfio.h"
39382+
39383+#include <rte_log.h>
39384+
39385+#include "eal_vfio_fsl_mc.h"
39386+
39387+#include "rte_pci_dev_ids.h"
39388+#include "eal_filesystem.h"
39389+#include "eal_private.h"
39390+
39391+#ifndef VFIO_MAX_GROUPS
39392+#define VFIO_MAX_GROUPS 64
39393+#endif
39394+
39395+//#define DPAA2_STAGE2_STASHING
39396+
39397+/** Pathname of FSL-MC devices directory. */
39398+#define SYSFS_FSL_MC_DEVICES "/sys/bus/fsl-mc/devices"
39399+
39400+/* Number of VFIO containers & groups with in */
39401+static struct vfio_group vfio_groups[VFIO_MAX_GRP];
39402+static struct vfio_container vfio_containers[VFIO_MAX_CONTAINERS];
39403+static char *ls2bus_container;
39404+static int container_device_fd;
39405+static uint32_t *msi_intr_vaddr;
39406+void *(*mcp_ptr_list);
39407+static uint32_t mcp_id;
39408+
39409+static int vfio_connect_container(struct vfio_group *vfio_group)
39410+{
39411+ struct vfio_container *container;
39412+ int i, fd, ret;
39413+
39414+ /* Try connecting to vfio container already created */
39415+ for (i = 0; i < VFIO_MAX_CONTAINERS; i++) {
39416+ container = &vfio_containers[i];
39417+ if (!ioctl(vfio_group->fd, VFIO_GROUP_SET_CONTAINER, &container->fd)) {
39418+ RTE_LOG(ERR, EAL, "Container pre-exists with FD[0x%x]"
39419+ " for this group\n", container->fd);
39420+ vfio_group->container = container;
39421+ return 0;
39422+ }
39423+ }
39424+
39425+ /* Opens main vfio file descriptor which represents the "container" */
39426+ fd = open("/dev/vfio/vfio", O_RDWR);
39427+ if (fd < 0) {
39428+ RTE_LOG(ERR, EAL, "vfio: failed to open /dev/vfio/vfio\n");
39429+ return -errno;
39430+ }
39431+
39432+ ret = ioctl(fd, VFIO_GET_API_VERSION);
39433+ if (ret != VFIO_API_VERSION) {
39434+ RTE_LOG(ERR, EAL, "vfio: supported vfio version: %d, "
39435+ "reported version: %d", VFIO_API_VERSION, ret);
39436+ close(fd);
39437+ return -EINVAL;
39438+ }
39439+#ifndef DPAA2_STAGE2_STASHING
39440+ /* Check whether support for SMMU type IOMMU prresent or not */
39441+ if (ioctl(fd, VFIO_CHECK_EXTENSION, VFIO_TYPE1_IOMMU)) {
39442+ /* Connect group to container */
39443+ ret = ioctl(vfio_group->fd, VFIO_GROUP_SET_CONTAINER, &fd);
39444+ if (ret) {
39445+ RTE_LOG(ERR, EAL, "vfio: failed to set group container:\n");
39446+ close(fd);
39447+ return -errno;
39448+ }
39449+
39450+ ret = ioctl(fd, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU);
39451+ if (ret) {
39452+ RTE_LOG(ERR, EAL, "vfio: failed to set iommu for container:\n");
39453+ close(fd);
39454+ return -errno;
39455+ }
39456+ } else {
39457+ RTE_LOG(ERR, EAL, "vfio error: No supported IOMMU\n");
39458+ close(fd);
39459+ return -EINVAL;
39460+ }
39461+#else
39462+ /* Check whether support for SMMU type IOMMU stage 2 present or not */
39463+ if (ioctl(fd, VFIO_CHECK_EXTENSION, VFIO_TYPE1_NESTING_IOMMU)) {
39464+ /* Connect group to container */
39465+ ret = ioctl(vfio_group->fd, VFIO_GROUP_SET_CONTAINER, &fd);
39466+ if (ret) {
39467+ RTE_LOG(ERR, EAL, "vfio: failed to set group container:\n");
39468+ close(fd);
39469+ return -errno;
39470+ }
39471+
39472+ ret = ioctl(fd, VFIO_SET_IOMMU, VFIO_TYPE1_NESTING_IOMMU);
39473+ if (ret) {
39474+ RTE_LOG(ERR, EAL, "vfio: failed to set iommu-2 for container:\n");
39475+ close(fd);
39476+ return -errno;
39477+ }
39478+ } else {
39479+ RTE_LOG(ERR, EAL, "vfio error: No supported IOMMU-2\n");
39480+ close(fd);
39481+ return -EINVAL;
39482+ }
39483+#endif
39484+ container = NULL;
39485+ for (i = 0; i < VFIO_MAX_CONTAINERS; i++) {
39486+ if (vfio_containers[i].used)
39487+ continue;
39488+ RTE_LOG(ERR, EAL, "DPAA2-Unused container at index %d\n", i);
39489+ container = &vfio_containers[i];
39490+ }
39491+ if (!container) {
39492+ RTE_LOG(ERR, EAL, "vfio error: No Free Container Found\n");
39493+ close(fd);
39494+ return -ENOMEM;
39495+ }
39496+
39497+ container->used = 1;
39498+ container->fd = fd;
39499+ container->group_list[container->index] = vfio_group;
39500+ vfio_group->container = container;
39501+ container->index++;
39502+ return 0;
39503+}
39504+
39505+static int vfio_map_irq_region(struct vfio_group *group)
39506+{
39507+ int ret;
39508+ unsigned long *vaddr = NULL;
39509+ struct vfio_iommu_type1_dma_map map = {
39510+ .argsz = sizeof(map),
39511+ .flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE,
39512+ .vaddr = 0x6030000,
39513+ .iova = 0x6030000,
39514+ .size = 0x1000,
39515+ };
39516+
39517+ vaddr = (unsigned long *)mmap(NULL, 0x1000, PROT_WRITE |
39518+ PROT_READ, MAP_SHARED, container_device_fd, 0x6030000);
39519+ if (vaddr == MAP_FAILED) {
39520+ RTE_LOG(ERR, EAL, " mapping GITS region (errno = %d)", errno);
39521+ return -errno;
39522+ }
39523+
39524+ msi_intr_vaddr = (uint32_t *)((char *)(vaddr) + 64);
39525+ map.vaddr = (unsigned long)vaddr;
39526+ ret = ioctl(group->container->fd, VFIO_IOMMU_MAP_DMA, &map);
39527+ if (ret == 0)
39528+ return 0;
39529+
39530+ RTE_LOG(ERR, EAL, "vfio_map_irq_region fails (errno = %d)", errno);
39531+ return -errno;
39532+}
39533+
39534+int vfio_dmamap_mem_region(uint64_t vaddr,
39535+ uint64_t iova,
39536+ uint64_t size)
39537+{
39538+ struct vfio_group *group;
39539+ struct vfio_iommu_type1_dma_map dma_map = {
39540+ .argsz = sizeof(dma_map),
39541+ .flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE,
39542+ };
39543+
39544+ dma_map.vaddr = vaddr;
39545+ dma_map.size = size;
39546+ dma_map.iova = iova;
39547+
39548+ /* SET DMA MAP for IOMMU */
39549+ group = &vfio_groups[0];
39550+ if (ioctl(group->container->fd, VFIO_IOMMU_MAP_DMA, &dma_map)) {
39551+ /* todo changes these to RTE_LOG */
39552+ RTE_LOG(ERR, EAL, "SWP: VFIO_IOMMU_MAP_DMA API Error %d.\n", errno);
39553+ return -1;
39554+ }
39555+ return 0;
39556+}
39557+
39558+static int32_t setup_dmamap(void)
39559+{
39560+ int ret;
39561+ struct vfio_group *group;
39562+ struct vfio_iommu_type1_dma_map dma_map = {
39563+ .argsz = sizeof(struct vfio_iommu_type1_dma_map),
39564+ .flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE,
39565+ };
39566+
39567+ int i;
39568+ const struct rte_memseg *memseg;
39569+
39570+ for (i = 0; i < RTE_MAX_MEMSEG; i++) {
39571+ memseg = rte_eal_get_physmem_layout();
39572+ if (memseg == NULL) {
39573+ RTE_LOG(ERR, EAL,
39574+ "\nError Cannot get physical layout\n");
39575+ return -ENODEV;
39576+ }
39577+
39578+ if (memseg[i].addr == NULL && memseg[i].len == 0) {
39579+ break;
39580+ }
39581+
39582+ dma_map.size = memseg[i].len;
39583+ dma_map.vaddr = memseg[i].addr_64;
39584+#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
39585+ dma_map.iova = memseg[i].phys_addr;
39586+#else
39587+ dma_map.iova = dma_map.vaddr;
39588+#endif
39589+
39590+ /* SET DMA MAP for IOMMU */
39591+ group = &vfio_groups[0];
39592+
39593+ printf("-->Initial SHM Virtual ADDR %llX\n", dma_map.vaddr);
39594+ printf("-----> DMA size 0x%llX\n", dma_map.size);
39595+ ret = ioctl(group->container->fd, VFIO_IOMMU_MAP_DMA, &dma_map);
39596+ if (ret) {
39597+ RTE_LOG(ERR, EAL,
39598+ "\nErr: VFIO_IOMMU_MAP_DMA API Error %d.\n",
39599+ errno);
39600+ return ret;
39601+ }
39602+ printf("-----> dma_map.vaddr = 0x%llX\n", dma_map.vaddr);
39603+ }
39604+
39605+ /* TODO - This is a W.A. as VFIO currently does not add the mapping of
39606+ the interrupt region to SMMU. This should be removed once the
39607+ support is added in the Kernel.
39608+ */
39609+ vfio_map_irq_region(group);
39610+
39611+ return 0;
39612+}
39613+
39614+static int vfio_set_group(struct vfio_group *group, int groupid)
39615+{
39616+ char path[PATH_MAX];
39617+ struct vfio_group_status status = { .argsz = sizeof(status) };
39618+
39619+ /* Open the VFIO file corresponding to the IOMMU group */
39620+ snprintf(path, sizeof(path), "/dev/vfio/%d", groupid);
39621+
39622+ group->fd = open(path, O_RDWR);
39623+ if (group->fd < 0) {
39624+ RTE_LOG(ERR, EAL, "vfio: error opening %s\n", path);
39625+ return -1;
39626+ }
39627+
39628+ /* Test & Verify that group is VIABLE & AVAILABLE */
39629+ if (ioctl(group->fd, VFIO_GROUP_GET_STATUS, &status)) {
39630+ RTE_LOG(ERR, EAL, "vfio: error getting group status\n");
39631+ close(group->fd);
39632+ return -1;
39633+ }
39634+ if (!(status.flags & VFIO_GROUP_FLAGS_VIABLE)) {
39635+ RTE_LOG(ERR, EAL, "vfio: group not viable\n");
39636+ close(group->fd);
39637+ return -1;
39638+ }
39639+ /* Since Group is VIABLE, Store the groupid */
39640+ group->groupid = groupid;
39641+
39642+ /* Now connect this IOMMU group to given container */
39643+ if (vfio_connect_container(group)) {
39644+ RTE_LOG(ERR, EAL,
39645+ "vfio: error sonnecting container with group %d\n",
39646+ groupid);
39647+ close(group->fd);
39648+ return -1;
39649+ }
39650+
39651+ return 0;
39652+}
39653+
39654+static int32_t setup_vfio_grp(char *vfio_container)
39655+{
39656+ char path[PATH_MAX];
39657+ char iommu_group_path[PATH_MAX], *group_name;
39658+ struct vfio_group *group = NULL;
39659+ struct stat st;
39660+ int groupid;
39661+ int ret, len, i;
39662+
39663+ printf("\tProcessing Container = %s\n", vfio_container);
39664+ sprintf(path, "/sys/bus/fsl-mc/devices/%s", vfio_container);
39665+ /* Check whether ls-container exists or not */
39666+ printf("\tcontainer device path = %s\n", path);
39667+ if (stat(path, &st) < 0) {
39668+ RTE_LOG(ERR, EAL, "vfio: Error (%d) getting FSL-MC device (%s)\n",
39669+ errno, path);
39670+ return -errno;
39671+ }
39672+
39673+ /* DPRC container exists. NOw checkout the IOMMU Group */
39674+ strncat(path, "/iommu_group", sizeof(path) - strlen(path) - 1);
39675+
39676+ len = readlink(path, iommu_group_path, PATH_MAX);
39677+ if (len == -1) {
39678+ RTE_LOG(ERR, EAL, "\tvfio: error no iommu_group for device\n");
39679+ RTE_LOG(ERR, EAL, "\t%s: len = %d, errno = %d\n",
39680+ path, len, errno);
39681+ return -errno;
39682+ }
39683+
39684+ iommu_group_path[len] = 0;
39685+ group_name = basename(iommu_group_path);
39686+ if (sscanf(group_name, "%d", &groupid) != 1) {
39687+ RTE_LOG(ERR, EAL, "\tvfio: error reading %s: %m\n", path);
39688+ return -errno;
39689+ }
39690+
39691+ RTE_LOG(INFO, EAL, "\tvfio: iommu group id = %d\n", groupid);
39692+
39693+ /* Check if group already exists */
39694+ for (i = 0; i < VFIO_MAX_GRP; i++) {
39695+ group = &vfio_groups[i];
39696+ if (group->groupid == groupid) {
39697+ RTE_LOG(ERR, EAL, "groupid already exists %d\n", groupid);
39698+ return 0;
39699+ }
39700+ }
39701+
39702+ if (vfio_set_group(group, groupid)) {
39703+ RTE_LOG(ERR, EAL, "group setup failure - %d\n", groupid);
39704+ return -ENODEV;
39705+ }
39706+
39707+ /* Get Device information */
39708+ ret = ioctl(group->fd, VFIO_GROUP_GET_DEVICE_FD, vfio_container);
39709+ if (ret < 0) {
39710+ RTE_LOG(ERR, EAL, "\tvfio: error getting device %s fd from group %d\n",
39711+ vfio_container, group->groupid);
39712+ return ret;
39713+ }
39714+ container_device_fd = ret;
39715+ RTE_LOG(INFO, EAL, "vfio: Container FD is [0x%X]\n", container_device_fd);
39716+ /* Set up SMMU */
39717+ ret = setup_dmamap();
39718+ if (ret) {
39719+ RTE_LOG(ERR, EAL, ": Setting dma map\n");
39720+ return ret;
39721+ }
39722+
39723+ return 0;
39724+}
39725+
39726+
39727+static int64_t vfio_map_mcp_obj(struct vfio_group *group, char *mcp_obj)
39728+{
39729+ int64_t v_addr = (int64_t)MAP_FAILED;
39730+ int32_t ret, mc_fd;
39731+
39732+ struct vfio_device_info d_info = { .argsz = sizeof(d_info) };
39733+ struct vfio_region_info reg_info = { .argsz = sizeof(reg_info) };
39734+
39735+ /* getting the mcp object's fd*/
39736+ mc_fd = ioctl(group->fd, VFIO_GROUP_GET_DEVICE_FD, mcp_obj);
39737+ if (mc_fd < 0) {
39738+ RTE_LOG(ERR, EAL, "vfio: error getting device %s fd from group %d\n",
39739+ mcp_obj, group->fd);
39740+ return v_addr;
39741+ }
39742+
39743+ /* getting device info*/
39744+ ret = ioctl(mc_fd, VFIO_DEVICE_GET_INFO, &d_info);
39745+ if (ret < 0) {
39746+ RTE_LOG(ERR, EAL, "vfio: error getting DEVICE_INFO\n");
39747+ goto MC_FAILURE;
39748+ }
39749+
39750+ /* getting device region info*/
39751+ ret = ioctl(mc_fd, VFIO_DEVICE_GET_REGION_INFO, &reg_info);
39752+ if (ret < 0) {
39753+ RTE_LOG(ERR, EAL, "vfio: error getting REGION_INFO\n");
39754+ goto MC_FAILURE;
39755+ }
39756+
39757+ RTE_LOG(INFO, EAL, "region offset = %llx , region size = %llx\n",
39758+ reg_info.offset, reg_info.size);
39759+
39760+ v_addr = (uint64_t)mmap(NULL, reg_info.size,
39761+ PROT_WRITE | PROT_READ, MAP_SHARED,
39762+ mc_fd, reg_info.offset);
39763+
39764+MC_FAILURE:
39765+ close(mc_fd);
39766+
39767+ return v_addr;
39768+}
39769+
39770+/* Following function shall fetch total available list of MC devices
39771+ * from VFIO container & populate private list of devices and other
39772+ * data structures
39773+ */
39774+static int vfio_process_group_devices(void)
39775+{
39776+ struct vfio_device *vdev;
39777+ struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
39778+ char *temp_obj, *object_type, *mcp_obj, *dev_name;
39779+ int32_t object_id, i, dev_fd, ret;
39780+ DIR *d;
39781+ struct dirent *dir;
39782+ char path[PATH_MAX];
39783+ int64_t v_addr;
39784+ int ndev_count;
39785+ struct vfio_group *group = &vfio_groups[0];
39786+
39787+ sprintf(path, "/sys/kernel/iommu_groups/%d/devices", group->groupid);
39788+
39789+ d = opendir(path);
39790+ if (!d) {
39791+ RTE_LOG(ERR, EAL,"Unable to open directory %s\n", path);
39792+ return -1;
39793+ }
39794+
39795+ /*Counting the number of devices in a group and getting the mcp ID*/
39796+ ndev_count = 0;
39797+ mcp_obj = NULL;
39798+ while ((dir = readdir(d)) != NULL) {
39799+ if (dir->d_type == DT_LNK) {
39800+ ndev_count++;
39801+ if (!strncmp("dpmcp", dir->d_name, 5)) {
39802+ if (mcp_obj)
39803+ free(mcp_obj);
39804+ mcp_obj = malloc(sizeof(dir->d_name));
39805+ if (!mcp_obj) {
39806+ RTE_LOG(ERR, EAL,
39807+ "Unable to allocate memory\n");
39808+ return -ENOMEM;
39809+ }
39810+ strcpy(mcp_obj, dir->d_name);
39811+ temp_obj = strtok(dir->d_name, ".");
39812+ temp_obj = strtok(NULL, ".");
39813+ sscanf(temp_obj, "%d", &mcp_id);
39814+ }
39815+ }
39816+ }
39817+ closedir(d);
39818+
39819+ if (!mcp_obj) {
39820+ RTE_LOG(ERR, EAL,"MCP Object not Found\n");
39821+ return -ENODEV;
39822+ }
39823+ RTE_LOG(INFO, EAL,"Total devices in conatiner = %d, MCP ID = %d\n",
39824+ ndev_count, mcp_id);
39825+
39826+ /* Allocate the memory depends upon number of objects in a group*/
39827+ group->vfio_device = (struct vfio_device *)malloc(ndev_count * sizeof(struct vfio_device));
39828+ if (!(group->vfio_device)) {
39829+ RTE_LOG(ERR, EAL,"Unable to allocate memory\n");
39830+ free(mcp_obj);
39831+ return -ENOMEM;
39832+ }
39833+
39834+ /* Allocate memory for MC Portal list */
39835+ mcp_ptr_list = malloc(sizeof(void *) * 1);
39836+ if (!mcp_ptr_list) {
39837+ RTE_LOG(ERR, EAL, "NO Memory!\n");
39838+ free(mcp_obj);
39839+ goto FAILURE;
39840+ }
39841+
39842+ v_addr = vfio_map_mcp_obj(group, mcp_obj);
39843+ free(mcp_obj);
39844+ if (v_addr == (int64_t)MAP_FAILED) {
39845+ RTE_LOG(ERR, EAL, "mapping region (errno = %d)\n", errno);
39846+ goto FAILURE;
39847+ }
39848+
39849+ RTE_LOG(INFO, EAL, "MC has VIR_ADD = 0x%ld\n", v_addr);
39850+
39851+ mcp_ptr_list[0] = (void *)v_addr;
39852+
39853+ d = opendir(path);
39854+ if (!d) {
39855+ RTE_LOG(ERR, EAL, "Directory %s not able to open\n", path);
39856+ goto FAILURE;
39857+ }
39858+
39859+ i = 0;
39860+ printf("\nDPAA2 - Parsing MC Device Objects:\n");
39861+ /* Parsing each object and initiating them*/
39862+ while ((dir = readdir(d)) != NULL) {
39863+ if (dir->d_type != DT_LNK)
39864+ continue;
39865+ if (!strncmp("dprc", dir->d_name, 4) || !strncmp("dpmcp", dir->d_name, 5))
39866+ continue;
39867+ dev_name = malloc(sizeof(dir->d_name));
39868+ if (!dev_name) {
39869+ RTE_LOG(ERR, EAL, "Unable to allocate memory\n");
39870+ goto FAILURE;
39871+ }
39872+ strcpy(dev_name, dir->d_name);
39873+ object_type = strtok(dir->d_name, ".");
39874+ temp_obj = strtok(NULL, ".");
39875+ sscanf(temp_obj, "%d", &object_id);
39876+ RTE_LOG(INFO, EAL, "%s ", dev_name);
39877+
39878+ /* getting the device fd*/
39879+ dev_fd = ioctl(group->fd, VFIO_GROUP_GET_DEVICE_FD, dev_name);
39880+ if (dev_fd < 0) {
39881+ RTE_LOG(ERR, EAL, "vfio getting device %s fd from group %d\n",
39882+ dev_name, group->fd);
39883+ free(dev_name);
39884+ goto FAILURE;
39885+ }
39886+
39887+ free(dev_name);
39888+ vdev = &group->vfio_device[group->object_index++];
39889+ vdev->fd = dev_fd;
39890+ vdev->index = i;
39891+ i++;
39892+ /* Get Device inofrmation */
39893+ if (ioctl(vdev->fd, VFIO_DEVICE_GET_INFO, &device_info)) {
39894+ RTE_LOG(ERR, EAL, "VFIO_DEVICE_FSL_MC_GET_INFO failed\n");
39895+ goto FAILURE;
39896+ }
39897+
39898+ if (!strcmp(object_type, "dpni") ||
39899+ !strcmp(object_type, "dpseci")) {
39900+ struct rte_pci_device *dev;
39901+
39902+ dev = malloc(sizeof(struct rte_pci_device));
39903+ if (dev == NULL) {
39904+ return -1;
39905+ }
39906+ memset(dev, 0, sizeof(*dev));
39907+ /* store hw_id of dpni/dpseci device */
39908+ dev->addr.devid = object_id;
39909+ dev->id.vendor_id = FSL_VENDOR_ID;
39910+ dev->id.device_id = (strcmp(object_type, "dpseci"))?
39911+ FSL_MC_DPNI_DEVID: FSL_MC_DPSECI_DEVID;
39912+
39913+ TAILQ_INSERT_TAIL(&pci_device_list, dev, next);
39914+ }
39915+
39916+ if (!strcmp(object_type, "dpio")) {
39917+ dpaa2_create_dpio_device(vdev, &device_info, object_id);
39918+ }
39919+
39920+ if (!strcmp(object_type, "dpbp")) {
39921+ dpaa2_create_dpbp_device(object_id);
39922+ }
39923+ }
39924+ closedir(d);
39925+
39926+ ret = dpaa2_affine_qbman_swp();
39927+ if (ret)
39928+ RTE_LOG(ERR, EAL, "%s(): Err in affining qbman swp\n", __func__);
39929+
39930+ return 0;
39931+
39932+FAILURE:
39933+ free(group->vfio_device);
39934+ group->vfio_device = NULL;
39935+ return -1;
39936+}
39937+
39938+/*
39939+ * Scan the content of the PCI bus, and the devices in the devices
39940+ * list
39941+ */
39942+static int
39943+fsl_mc_scan(void)
39944+{
39945+ char path[PATH_MAX];
39946+ struct stat st;
39947+
39948+ ls2bus_container = getenv("DPRC");
39949+
39950+ if (ls2bus_container == NULL) {
39951+ RTE_LOG(WARNING, EAL, "vfio container not set in env DPRC\n");
39952+ return -1;
39953+ }
39954+
39955+ snprintf(path, sizeof(path), "%s/%s", SYSFS_FSL_MC_DEVICES,
39956+ ls2bus_container);
39957+ /* Check whether LS-Container exists or not */
39958+ RTE_LOG(INFO, EAL, "\tcontainer device path = %s\n", path);
39959+ if (stat(path, &st) < 0) {
39960+ RTE_LOG(ERR, EAL, "vfio:fsl-mc device does not exists\n");
39961+ return -1;
39962+ }
39963+ return 0;
39964+}
39965+
39966+/* Init the FSL-MC- LS2 EAL subsystem */
39967+int
39968+rte_eal_dpaa2_init(void)
39969+{
39970+ if (fsl_mc_scan() < 0)
39971+ return -1;
39972+
39973+#ifdef VFIO_PRESENT
39974+ if (setup_vfio_grp(ls2bus_container)) {
39975+ RTE_LOG(ERR, EAL, "setup_vfio_grp\n");
39976+ return -1;
39977+ }
39978+ if (vfio_process_group_devices()) {
39979+ RTE_LOG(ERR, EAL, "vfio_process_group_devices\n");
39980+ return -1;
39981+ }
39982+#endif
39983+ return 0;
39984+}
39985diff --git a/lib/librte_eal/linuxapp/eal/eal_vfio_fsl_mc.h b/lib/librte_eal/linuxapp/eal/eal_vfio_fsl_mc.h
39986new file mode 100644
39987index 0000000..7fc5ec6
39988--- /dev/null
39989+++ b/lib/librte_eal/linuxapp/eal/eal_vfio_fsl_mc.h
39990@@ -0,0 +1,102 @@
39991+/*-
39992+ * BSD LICENSE
39993+ *
39994+ * Copyright(c) 2014 Freescale Semiconductor. All rights reserved.
39995+ * All rights reserved.
39996+ *
39997+ * Redistribution and use in source and binary forms, with or without
39998+ * modification, are permitted provided that the following conditions
39999+ * are met:
40000+ *
40001+ * * Redistributions of source code must retain the above copyright
40002+ * notice, this list of conditions and the following disclaimer.
40003+ * * Redistributions in binary form must reproduce the above copyright
40004+ * notice, this list of conditions and the following disclaimer in
40005+ * the documentation and/or other materials provided with the
40006+ * distribution.
40007+ * * Neither the name of Freescale Semiconductor nor the names of its
40008+ * contributors may be used to endorse or promote products derived
40009+ * from this software without specific prior written permission.
40010+ *
40011+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
40012+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40013+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40014+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40015+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40016+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40017+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40018+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
40019+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40020+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40021+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40022+ */
40023+
40024+#ifndef _EAL_VFIO_FSL_MC_H_
40025+#define _EAL_VFIO_FSL_MC_H_
40026+
40027+#include <rte_memory.h>
40028+#include <rte_mbuf.h>
40029+#include <rte_atomic.h>
40030+#include "eal_vfio.h"
40031+
40032+#define FSL_VENDOR_ID 0x1957
40033+#define FSL_MC_DPNI_DEVID 7
40034+#define FSL_MC_DPSECI_DEVID 3
40035+
40036+#define VFIO_MAX_GRP 1
40037+#define VFIO_MAX_CONTAINERS 1
40038+
40039+#define DPAA2_MBUF_HW_ANNOTATION 64
40040+#define DPAA2_FD_PTA_SIZE 64
40041+#define DPAA2_PACKET_LAYOUT_ALIGN 256
40042+#if (RTE_CACHE_LINE_SIZE == 128)
40043+#define DPAA2_RES 128
40044+#else
40045+#define DPAA2_RES 0
40046+#endif
40047+
40048+#define DPAA2_ALIGN_ROUNDUP(x, align) ((align) * (((x) + align - 1) / (align)))
40049+#define DPAA2_ALIGN_ROUNDUP_PTR(x, align)\
40050+ ((void *)DPAA2_ALIGN_ROUNDUP((uintptr_t)(x), (uintptr_t)(align)))
40051+
40052+typedef struct vfio_device {
40053+ int fd; /* fsl_mc root container device ?? */
40054+ int index; /*index of child object */
40055+ struct vfio_device *child; /* Child object */
40056+} vfio_device;
40057+
40058+typedef struct vfio_group {
40059+ int fd; /* /dev/vfio/"groupid" */
40060+ int groupid;
40061+ struct vfio_container *container;
40062+ int object_index;
40063+ struct vfio_device *vfio_device;
40064+} vfio_group;
40065+
40066+typedef struct vfio_container {
40067+ int fd; /* /dev/vfio/vfio */
40068+ int used;
40069+ int index; /* index in group list */
40070+ struct vfio_group *group_list[VFIO_MAX_GRP];
40071+} vfio_container;
40072+
40073+int vfio_dmamap_mem_region(
40074+ uint64_t vaddr,
40075+ uint64_t iova,
40076+ uint64_t size);
40077+
40078+/* initialize the NXP/FSL dpaa2 accelerators */
40079+int rte_eal_dpaa2_init(void);
40080+
40081+int dpaa2_create_dpio_device(struct vfio_device *vdev,
40082+ struct vfio_device_info *obj_info,
40083+ int object_id);
40084+
40085+int dpaa2_create_dpbp_device(int dpbp_id);
40086+
40087+int dpaa2_affine_qbman_swp(void);
40088+
40089+int dpaa2_affine_qbman_swp_sec(void);
40090+
40091+#endif
40092+
40093diff --git a/lib/librte_mbuf/Makefile b/lib/librte_mbuf/Makefile
40094index 8d62b0d..92446d1 100644
40095--- a/lib/librte_mbuf/Makefile
40096+++ b/lib/librte_mbuf/Makefile
40097@@ -36,6 +36,10 @@ LIB = librte_mbuf.a
40098
40099 CFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3
40100
40101+ifeq ($(CONFIG_RTE_LIBRTE_DPAA2_PMD),y)
40102+CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal
40103+endif
40104+
40105 EXPORT_MAP := rte_mbuf_version.map
40106
40107 LIBABIVER := 2
40108diff --git a/lib/librte_mbuf/rte_mbuf.c b/lib/librte_mbuf/rte_mbuf.c
40109index dc0467c..c4009ee 100644
40110--- a/lib/librte_mbuf/rte_mbuf.c
40111+++ b/lib/librte_mbuf/rte_mbuf.c
40112@@ -60,6 +60,59 @@
40113 #include <rte_hexdump.h>
40114 #include <rte_errno.h>
40115
40116+#ifdef RTE_LIBRTE_DPAA2_PMD
40117+
40118+int __attribute__((weak))
40119+hw_mbuf_create_pool(
40120+struct rte_mempool __rte_unused *mp)
40121+{
40122+ RTE_LOG(WARNING, MBUF, "%s/n", __func__);
40123+ return -1;
40124+}
40125+
40126+int __attribute__((weak))
40127+hw_mbuf_init(
40128+ struct rte_mempool __rte_unused*mp,
40129+ void __rte_unused *_m)
40130+{
40131+ RTE_LOG(WARNING, MBUF, "%s/n", __func__);
40132+ return -1;
40133+}
40134+
40135+int __attribute__((weak))
40136+hw_mbuf_alloc(
40137+ struct rte_mempool __rte_unused *mp,
40138+ void __rte_unused **obj_p)
40139+{
40140+ RTE_LOG(WARNING, MBUF, "%s/n", __func__);
40141+ return -1;
40142+}
40143+
40144+int __attribute__((weak))
40145+hw_mbuf_free(void __rte_unused *m)
40146+{
40147+ RTE_LOG(WARNING, MBUF, "%s/n", __func__);
40148+ return -1;
40149+}
40150+
40151+int __attribute__((weak))
40152+hw_mbuf_alloc_bulk(struct rte_mempool __rte_unused *pool,
40153+ void __rte_unused **obj_table,
40154+ unsigned __rte_unused count)
40155+{
40156+ RTE_LOG(WARNING, MBUF, "%s/n", __func__);
40157+ return -1;
40158+}
40159+
40160+int __attribute__((weak))
40161+hw_mbuf_free_bulk(struct rte_mempool __rte_unused *mp,
40162+ void __rte_unused * const *obj_table,
40163+ unsigned __rte_unused n)
40164+{
40165+ RTE_LOG(WARNING, MBUF, "%s/n", __func__);
40166+ return -1;
40167+}
40168+#endif
40169 /*
40170 * ctrlmbuf constructor, given as a callback function to
40171 * rte_mempool_create()
40172@@ -106,6 +159,10 @@ rte_pktmbuf_pool_init(struct rte_mempool *mp, void *opaque_arg)
40173
40174 mbp_priv = rte_mempool_get_priv(mp);
40175 memcpy(mbp_priv, user_mbp_priv, sizeof(*mbp_priv));
40176+#ifdef RTE_LIBRTE_DPAA2_PMD
40177+ if (mp->flags & MEMPOOL_F_HW_PKT_POOL)
40178+ hw_mbuf_create_pool(mp);
40179+#endif
40180 }
40181
40182 /*
40183@@ -122,6 +179,12 @@ rte_pktmbuf_init(struct rte_mempool *mp,
40184 struct rte_mbuf *m = _m;
40185 uint32_t mbuf_size, buf_len, priv_size;
40186
40187+#ifdef RTE_LIBRTE_DPAA2_PMD
40188+ if (mp->flags & MEMPOOL_F_HW_PKT_POOL) {
40189+ if (hw_mbuf_init(mp, m) == 0)
40190+ return;
40191+ }
40192+#endif
40193 priv_size = rte_pktmbuf_priv_size(mp);
40194 mbuf_size = sizeof(struct rte_mbuf) + priv_size;
40195 buf_len = rte_pktmbuf_data_room_size(mp);
40196@@ -170,7 +233,11 @@ rte_pktmbuf_pool_create(const char *name, unsigned n,
40197 return rte_mempool_create(name, n, elt_size,
40198 cache_size, sizeof(struct rte_pktmbuf_pool_private),
40199 rte_pktmbuf_pool_init, &mbp_priv, rte_pktmbuf_init, NULL,
40200+#if defined(RTE_LIBRTE_DPAA2_PMD)
40201+ socket_id, MEMPOOL_F_HW_PKT_POOL);
40202+#else
40203 socket_id, 0);
40204+#endif
40205 }
40206
40207 /* do some sanity checks on a mbuf: panic if it fails */
40208diff --git a/lib/librte_mempool/Makefile b/lib/librte_mempool/Makefile
40209index a6898ef..6116d52 100644
40210--- a/lib/librte_mempool/Makefile
40211+++ b/lib/librte_mempool/Makefile
40212@@ -36,6 +36,10 @@ LIB = librte_mempool.a
40213
40214 CFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3
40215
40216+ifeq ($(CONFIG_RTE_LIBRTE_DPAA2_PMD),y)
40217+CFLAGS += -I$(RTE_SDK)/lib/librte_mbuf
40218+CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal
40219+endif
40220 EXPORT_MAP := rte_mempool_version.map
40221
40222 LIBABIVER := 1
40223diff --git a/lib/librte_mempool/rte_mempool.c b/lib/librte_mempool/rte_mempool.c
40224index f8781e1..ac9595d 100644
40225--- a/lib/librte_mempool/rte_mempool.c
40226+++ b/lib/librte_mempool/rte_mempool.c
40227@@ -60,6 +60,10 @@
40228
40229 #include "rte_mempool.h"
40230
40231+#ifdef RTE_LIBRTE_DPAA2_PMD
40232+#include "eal_vfio_fsl_mc.h"
40233+#endif
40234+
40235 TAILQ_HEAD(rte_mempool_list, rte_tailq_entry);
40236
40237 static struct rte_tailq_elem rte_mempool_tailq = {
40238@@ -316,6 +320,12 @@ rte_mempool_calc_obj_size(uint32_t elt_size, uint32_t flags,
40239
40240 /* this is the size of an object, including header and trailer */
40241 sz->total_size = sz->header_size + sz->elt_size + sz->trailer_size;
40242+#ifdef RTE_LIBRTE_DPAA2_PMD
40243+ if (flags & MEMPOOL_F_HW_PKT_POOL)
40244+ sz->total_size += DPAA2_ALIGN_ROUNDUP(
40245+ DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE,
40246+ DPAA2_PACKET_LAYOUT_ALIGN);
40247+#endif
40248
40249 return sz->total_size;
40250 }
40251@@ -590,6 +600,9 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size,
40252 mp->cache_size = cache_size;
40253 mp->cache_flushthresh = CALC_CACHE_FLUSHTHRESH(cache_size);
40254 mp->private_data_size = private_data_size;
40255+#ifdef RTE_LIBRTE_DPAA2_PMD
40256+ mp->offload_ptr = UINTPTR_MAX;
40257+#endif
40258
40259 /* calculate address of the first element for continuous mempool. */
40260 obj = (char *)mp + MEMPOOL_HEADER_SIZE(mp, pg_num) +
40261diff --git a/lib/librte_mempool/rte_mempool.h b/lib/librte_mempool/rte_mempool.h
40262index 9745bf0..304a434 100644
40263--- a/lib/librte_mempool/rte_mempool.h
40264+++ b/lib/librte_mempool/rte_mempool.h
40265@@ -215,7 +215,10 @@ struct rte_mempool {
40266 uintptr_t elt_va_end;
40267 /**< Virtual address of the <size + 1> mempool object. */
40268 phys_addr_t elt_pa[MEMPOOL_PG_NUM_DEFAULT];
40269+#ifdef RTE_LIBRTE_DPAA2_PMD
40270 /**< Array of physical page addresses for the mempool objects buffer. */
40271+ uintptr_t offload_ptr;
40272+#endif
40273
40274 } __rte_cache_aligned;
40275
40276@@ -223,7 +226,18 @@ struct rte_mempool {
40277 #define MEMPOOL_F_NO_CACHE_ALIGN 0x0002 /**< Do not align objs on cache lines.*/
40278 #define MEMPOOL_F_SP_PUT 0x0004 /**< Default put is "single-producer".*/
40279 #define MEMPOOL_F_SC_GET 0x0008 /**< Default get is "single-consumer".*/
40280-
40281+#ifdef RTE_LIBRTE_DPAA2_PMD
40282+#define MEMPOOL_F_HW_PKT_POOL 0x0010 /**< HW offload for packet buffer mgmt*/
40283+
40284+int hw_mbuf_create_pool(struct rte_mempool *mp);
40285+int hw_mbuf_init(struct rte_mempool *mp, void *_m);
40286+int hw_mbuf_alloc(struct rte_mempool *mp, void **obj_p);
40287+int hw_mbuf_free(void *_m);
40288+int hw_mbuf_alloc_bulk(struct rte_mempool *pool,
40289+ void **obj_table, unsigned count);
40290+int hw_mbuf_free_bulk(struct rte_mempool *mp, void * const *obj_table,
40291+ unsigned n);
40292+#endif
40293 /**
40294 * @internal When debug is enabled, store some statistics.
40295 *
40296@@ -877,6 +891,12 @@ static inline void __attribute__((always_inline))
40297 rte_mempool_put_bulk(struct rte_mempool *mp, void * const *obj_table,
40298 unsigned n)
40299 {
40300+#ifdef RTE_LIBRTE_DPAA2_PMD
40301+ if (mp->flags & MEMPOOL_F_HW_PKT_POOL) {
40302+ if (hw_mbuf_free_bulk(mp, obj_table, n) == 0)
40303+ return;
40304+ }
40305+#endif
40306 __mempool_check_cookies(mp, obj_table, n, 0);
40307 __mempool_put_bulk(mp, obj_table, n, !(mp->flags & MEMPOOL_F_SP_PUT));
40308 }
40309@@ -1091,6 +1111,14 @@ static inline int __attribute__((always_inline))
40310 rte_mempool_get_bulk(struct rte_mempool *mp, void **obj_table, unsigned n)
40311 {
40312 int ret;
40313+
40314+#ifdef RTE_LIBRTE_DPAA2_PMD
40315+ if (mp->flags & MEMPOOL_F_HW_PKT_POOL) {
40316+ ret = hw_mbuf_alloc_bulk(mp, obj_table, n);
40317+ if (ret > -2)
40318+ return ret;
40319+ }
40320+#endif
40321 ret = __mempool_get_bulk(mp, obj_table, n,
40322 !(mp->flags & MEMPOOL_F_SC_GET));
40323 if (ret == 0)
40324diff --git a/mk/machine/dpaa2/rte.vars.mk b/mk/machine/dpaa2/rte.vars.mk
40325new file mode 100644
40326index 0000000..8541633
40327--- /dev/null
40328+++ b/mk/machine/dpaa2/rte.vars.mk
40329@@ -0,0 +1,60 @@
40330+# BSD LICENSE
40331+#
40332+# Copyright(c) 2016 Freescale Semiconductor, Inc. All rights reserved.
40333+#
40334+# Redistribution and use in source and binary forms, with or without
40335+# modification, are permitted provided that the following conditions
40336+# are met:
40337+#
40338+# * Redistributions of source code must retain the above copyright
40339+# notice, this list of conditions and the following disclaimer.
40340+# * Redistributions in binary form must reproduce the above copyright
40341+# notice, this list of conditions and the following disclaimer in
40342+# the documentation and/or other materials provided with the
40343+# distribution.
40344+# * Neither the name of Freescale Semiconductor nor the names of its
40345+# contributors may be used to endorse or promote products derived
40346+# from this software without specific prior written permission.
40347+#
40348+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
40349+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40350+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40351+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40352+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40353+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40354+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40355+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
40356+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40357+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40358+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40359+
40360+#
40361+# machine:
40362+#
40363+# - can define ARCH variable (overridden by cmdline value)
40364+# - can define CROSS variable (overridden by cmdline value)
40365+# - define MACHINE_CFLAGS variable (overridden by cmdline value)
40366+# - define MACHINE_LDFLAGS variable (overridden by cmdline value)
40367+# - define MACHINE_ASFLAGS variable (overridden by cmdline value)
40368+# - can define CPU_CFLAGS variable (overridden by cmdline value) that
40369+# overrides the one defined in arch.
40370+# - can define CPU_LDFLAGS variable (overridden by cmdline value) that
40371+# overrides the one defined in arch.
40372+# - can define CPU_ASFLAGS variable (overridden by cmdline value) that
40373+# overrides the one defined in arch.
40374+# - may override any previously defined variable
40375+#
40376+
40377+# ARCH =
40378+# CROSS =
40379+# MACHINE_CFLAGS =
40380+# MACHINE_LDFLAGS =
40381+# MACHINE_ASFLAGS =
40382+# CPU_CFLAGS =
40383+# CPU_LDFLAGS =
40384+# CPU_ASFLAGS =
40385+MACHINE_CFLAGS += -march=armv8-a
40386+
40387+ifdef CONFIG_RTE_ARCH_ARM_TUNE
40388+MACHINE_CFLAGS += -mcpu=$(CONFIG_RTE_ARCH_ARM_TUNE)
40389+endif
40390diff --git a/mk/rte.app.mk b/mk/rte.app.mk
40391index c66e491..ee25ba3 100644
40392--- a/mk/rte.app.mk
40393+++ b/mk/rte.app.mk
40394@@ -125,6 +125,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_CFGFILE) += -lrte_cfgfile
40395 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += -lrte_pmd_bond
40396
40397 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_XENVIRT) += -lrte_pmd_xenvirt
40398+_LDLIBS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += -lrte_pmd_dpaa2
40399
40400 ifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),n)
40401 # plugins (link only if static libraries)
40402--
404032.5.0
40404