| Damjan Marion | 47d165e | 2019-01-28 13:27:31 +0100 | [diff] [blame] | 1 | |
| 2 | #include <perfmon/perfmon_intel.h> |
| 3 | |
| 4 | static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = { |
| 5 | {0x37, 0x00, 0}, |
| 6 | {0x4C, 0x00, 0}, |
| 7 | {0x4D, 0x00, 0}, |
| 8 | |
| 9 | }; |
| 10 | |
| 11 | static perfmon_intel_pmc_event_t event_table[] = { |
| 12 | { |
| 13 | .event_code = {0xC4}, |
| 14 | .umask = 0x00, |
| 15 | .event_name = "br_inst_retired.all_branches", |
| 16 | }, |
| 17 | { |
| 18 | .event_code = {0xC4}, |
| 19 | .umask = 0x7E, |
| 20 | .event_name = "br_inst_retired.jcc", |
| 21 | }, |
| 22 | { |
| 23 | .event_code = {0xC4}, |
| 24 | .umask = 0xFE, |
| 25 | .event_name = "br_inst_retired.taken_jcc", |
| 26 | }, |
| 27 | { |
| 28 | .event_code = {0xC4}, |
| 29 | .umask = 0xF9, |
| 30 | .event_name = "br_inst_retired.call", |
| 31 | }, |
| 32 | { |
| 33 | .event_code = {0xC4}, |
| 34 | .umask = 0xFD, |
| 35 | .event_name = "br_inst_retired.rel_call", |
| 36 | }, |
| 37 | { |
| 38 | .event_code = {0xC4}, |
| 39 | .umask = 0xFB, |
| 40 | .event_name = "br_inst_retired.ind_call", |
| 41 | }, |
| 42 | { |
| 43 | .event_code = {0xC4}, |
| 44 | .umask = 0xF7, |
| 45 | .event_name = "br_inst_retired.return", |
| 46 | }, |
| 47 | { |
| 48 | .event_code = {0xC4}, |
| 49 | .umask = 0xEB, |
| 50 | .event_name = "br_inst_retired.non_return_ind", |
| 51 | }, |
| 52 | { |
| 53 | .event_code = {0xC4}, |
| 54 | .umask = 0xBF, |
| 55 | .event_name = "br_inst_retired.far_branch", |
| 56 | }, |
| 57 | { |
| 58 | .event_code = {0xC5}, |
| 59 | .umask = 0x00, |
| 60 | .event_name = "br_misp_retired.all_branches", |
| 61 | }, |
| 62 | { |
| 63 | .event_code = {0xC5}, |
| 64 | .umask = 0x7E, |
| 65 | .event_name = "br_misp_retired.jcc", |
| 66 | }, |
| 67 | { |
| 68 | .event_code = {0xC5}, |
| 69 | .umask = 0xFE, |
| 70 | .event_name = "br_misp_retired.taken_jcc", |
| 71 | }, |
| 72 | { |
| 73 | .event_code = {0xC5}, |
| 74 | .umask = 0xFB, |
| 75 | .event_name = "br_misp_retired.ind_call", |
| 76 | }, |
| 77 | { |
| 78 | .event_code = {0xC5}, |
| 79 | .umask = 0xF7, |
| 80 | .event_name = "br_misp_retired.return", |
| 81 | }, |
| 82 | { |
| 83 | .event_code = {0xC5}, |
| 84 | .umask = 0xEB, |
| 85 | .event_name = "br_misp_retired.non_return_ind", |
| 86 | }, |
| 87 | { |
| 88 | .event_code = {0xC2}, |
| 89 | .umask = 0x01, |
| 90 | .event_name = "uops_retired.ms", |
| 91 | }, |
| 92 | { |
| 93 | .event_code = {0xC2}, |
| 94 | .umask = 0x10, |
| 95 | .event_name = "uops_retired.all", |
| 96 | }, |
| 97 | { |
| 98 | .event_code = {0xC3}, |
| 99 | .umask = 0x01, |
| 100 | .event_name = "machine_clears.smc", |
| 101 | }, |
| 102 | { |
| 103 | .event_code = {0xC3}, |
| 104 | .umask = 0x02, |
| 105 | .event_name = "machine_clears.memory_ordering", |
| 106 | }, |
| 107 | { |
| 108 | .event_code = {0xC3}, |
| 109 | .umask = 0x04, |
| 110 | .event_name = "machine_clears.fp_assist", |
| 111 | }, |
| 112 | { |
| 113 | .event_code = {0xC3}, |
| 114 | .umask = 0x08, |
| 115 | .event_name = "machine_clears.all", |
| 116 | }, |
| 117 | { |
| 118 | .event_code = {0xCA}, |
| 119 | .umask = 0x01, |
| 120 | .event_name = "no_alloc_cycles.rob_full", |
| 121 | }, |
| 122 | { |
| 123 | .event_code = {0xCA}, |
| 124 | .umask = 0x04, |
| 125 | .event_name = "no_alloc_cycles.mispredicts", |
| 126 | }, |
| 127 | { |
| 128 | .event_code = {0xCA}, |
| 129 | .umask = 0x20, |
| 130 | .event_name = "no_alloc_cycles.rat_stall", |
| 131 | }, |
| 132 | { |
| 133 | .event_code = {0xCA}, |
| 134 | .umask = 0x50, |
| 135 | .event_name = "no_alloc_cycles.not_delivered", |
| 136 | }, |
| 137 | { |
| 138 | .event_code = {0xCA}, |
| 139 | .umask = 0x3F, |
| 140 | .event_name = "no_alloc_cycles.all", |
| 141 | }, |
| 142 | { |
| 143 | .event_code = {0xCB}, |
| 144 | .umask = 0x01, |
| 145 | .event_name = "rs_full_stall.mec", |
| 146 | }, |
| 147 | { |
| 148 | .event_code = {0xCB}, |
| 149 | .umask = 0x1F, |
| 150 | .event_name = "rs_full_stall.all", |
| 151 | }, |
| 152 | { |
| 153 | .event_code = {0xC0}, |
| 154 | .umask = 0x00, |
| 155 | .event_name = "inst_retired.any_p", |
| 156 | }, |
| 157 | { |
| 158 | .event_code = {0xCD}, |
| 159 | .umask = 0x01, |
| 160 | .event_name = "cycles_div_busy.all", |
| 161 | }, |
| 162 | { |
| 163 | .event_code = {0x00}, |
| 164 | .umask = 0x01, |
| 165 | .event_name = "inst_retired.any", |
| 166 | }, |
| 167 | { |
| 168 | .event_code = {0x00}, |
| 169 | .umask = 0x02, |
| 170 | .event_name = "cpu_clk_unhalted.core", |
| 171 | }, |
| 172 | { |
| 173 | .event_code = {0x00}, |
| 174 | .umask = 0x03, |
| 175 | .event_name = "cpu_clk_unhalted.ref_tsc", |
| 176 | }, |
| 177 | { |
| 178 | .event_code = {0x3C}, |
| 179 | .umask = 0x00, |
| 180 | .event_name = "cpu_clk_unhalted.core_p", |
| 181 | }, |
| 182 | { |
| 183 | .event_code = {0x3C}, |
| 184 | .umask = 0x01, |
| 185 | .event_name = "cpu_clk_unhalted.ref", |
| 186 | }, |
| 187 | { |
| 188 | .event_code = {0x30}, |
| 189 | .umask = 0x00, |
| 190 | .event_name = "l2_reject_xq.all", |
| 191 | }, |
| 192 | { |
| 193 | .event_code = {0x31}, |
| 194 | .umask = 0x00, |
| 195 | .event_name = "core_reject_l2q.all", |
| 196 | }, |
| 197 | { |
| 198 | .event_code = {0x2E}, |
| 199 | .umask = 0x4F, |
| 200 | .event_name = "longest_lat_cache.reference", |
| 201 | }, |
| 202 | { |
| 203 | .event_code = {0x2E}, |
| 204 | .umask = 0x41, |
| 205 | .event_name = "longest_lat_cache.miss", |
| 206 | }, |
| 207 | { |
| 208 | .event_code = {0x80}, |
| 209 | .umask = 0x03, |
| 210 | .event_name = "icache.accesses", |
| 211 | }, |
| 212 | { |
| 213 | .event_code = {0x80}, |
| 214 | .umask = 0x01, |
| 215 | .event_name = "icache.hit", |
| 216 | }, |
| 217 | { |
| 218 | .event_code = {0x80}, |
| 219 | .umask = 0x02, |
| 220 | .event_name = "icache.misses", |
| 221 | }, |
| 222 | { |
| 223 | .event_code = {0x86}, |
| 224 | .umask = 0x02, |
| 225 | .event_name = "fetch_stall.itlb_fill_pending_cycles", |
| 226 | }, |
| 227 | { |
| 228 | .event_code = {0x86}, |
| 229 | .umask = 0x04, |
| 230 | .event_name = "fetch_stall.icache_fill_pending_cycles", |
| 231 | }, |
| 232 | { |
| 233 | .event_code = {0x86}, |
| 234 | .umask = 0x3F, |
| 235 | .event_name = "fetch_stall.all", |
| 236 | }, |
| 237 | { |
| 238 | .event_code = {0xE6}, |
| 239 | .umask = 0x01, |
| 240 | .event_name = "baclears.all", |
| 241 | }, |
| 242 | { |
| 243 | .event_code = {0xE6}, |
| 244 | .umask = 0x08, |
| 245 | .event_name = "baclears.return", |
| 246 | }, |
| 247 | { |
| 248 | .event_code = {0xE6}, |
| 249 | .umask = 0x10, |
| 250 | .event_name = "baclears.cond", |
| 251 | }, |
| 252 | { |
| 253 | .event_code = {0xE7}, |
| 254 | .umask = 0x01, |
| 255 | .event_name = "ms_decoded.ms_entry", |
| 256 | }, |
| 257 | { |
| 258 | .event_code = {0xE9}, |
| 259 | .umask = 0x01, |
| 260 | .event_name = "decode_restriction.predecode_wrong", |
| 261 | }, |
| 262 | { |
| 263 | .event_code = {0x03}, |
| 264 | .umask = 0x01, |
| 265 | .event_name = "rehabq.ld_block_st_forward", |
| 266 | }, |
| 267 | { |
| 268 | .event_code = {0x03}, |
| 269 | .umask = 0x02, |
| 270 | .event_name = "rehabq.ld_block_std_notready", |
| 271 | }, |
| 272 | { |
| 273 | .event_code = {0x03}, |
| 274 | .umask = 0x04, |
| 275 | .event_name = "rehabq.st_splits", |
| 276 | }, |
| 277 | { |
| 278 | .event_code = {0x03}, |
| 279 | .umask = 0x08, |
| 280 | .event_name = "rehabq.ld_splits", |
| 281 | }, |
| 282 | { |
| 283 | .event_code = {0x03}, |
| 284 | .umask = 0x10, |
| 285 | .event_name = "rehabq.lock", |
| 286 | }, |
| 287 | { |
| 288 | .event_code = {0x03}, |
| 289 | .umask = 0x20, |
| 290 | .event_name = "rehabq.sta_full", |
| 291 | }, |
| 292 | { |
| 293 | .event_code = {0x03}, |
| 294 | .umask = 0x40, |
| 295 | .event_name = "rehabq.any_ld", |
| 296 | }, |
| 297 | { |
| 298 | .event_code = {0x03}, |
| 299 | .umask = 0x80, |
| 300 | .event_name = "rehabq.any_st", |
| 301 | }, |
| 302 | { |
| 303 | .event_code = {0x04}, |
| 304 | .umask = 0x01, |
| 305 | .event_name = "mem_uops_retired.l1_miss_loads", |
| 306 | }, |
| 307 | { |
| 308 | .event_code = {0x04}, |
| 309 | .umask = 0x02, |
| 310 | .event_name = "mem_uops_retired.l2_hit_loads", |
| 311 | }, |
| 312 | { |
| 313 | .event_code = {0x04}, |
| 314 | .umask = 0x04, |
| 315 | .event_name = "mem_uops_retired.l2_miss_loads", |
| 316 | }, |
| 317 | { |
| 318 | .event_code = {0x04}, |
| 319 | .umask = 0x08, |
| 320 | .event_name = "mem_uops_retired.dtlb_miss_loads", |
| 321 | }, |
| 322 | { |
| 323 | .event_code = {0x04}, |
| 324 | .umask = 0x10, |
| 325 | .event_name = "mem_uops_retired.utlb_miss", |
| 326 | }, |
| 327 | { |
| 328 | .event_code = {0x04}, |
| 329 | .umask = 0x20, |
| 330 | .event_name = "mem_uops_retired.hitm", |
| 331 | }, |
| 332 | { |
| 333 | .event_code = {0x04}, |
| 334 | .umask = 0x40, |
| 335 | .event_name = "mem_uops_retired.all_loads", |
| 336 | }, |
| 337 | { |
| 338 | .event_code = {0x04}, |
| 339 | .umask = 0x80, |
| 340 | .event_name = "mem_uops_retired.all_stores", |
| 341 | }, |
| 342 | { |
| 343 | .event_code = {0x05}, |
| 344 | .umask = 0x01, |
| 345 | .event_name = "page_walks.d_side_walks", |
| 346 | }, |
| 347 | { |
| 348 | .event_code = {0x05}, |
| 349 | .umask = 0x01, |
| 350 | .event_name = "page_walks.d_side_cycles", |
| 351 | }, |
| 352 | { |
| 353 | .event_code = {0x05}, |
| 354 | .umask = 0x02, |
| 355 | .event_name = "page_walks.i_side_walks", |
| 356 | }, |
| 357 | { |
| 358 | .event_code = {0x05}, |
| 359 | .umask = 0x02, |
| 360 | .event_name = "page_walks.i_side_cycles", |
| 361 | }, |
| 362 | { |
| 363 | .event_code = {0x05}, |
| 364 | .umask = 0x03, |
| 365 | .event_name = "page_walks.walks", |
| 366 | }, |
| 367 | { |
| 368 | .event_code = {0x05}, |
| 369 | .umask = 0x03, |
| 370 | .event_name = "page_walks.cycles", |
| 371 | }, |
| 372 | { |
| 373 | .event_code = {0xC4}, |
| 374 | .umask = 0x80, |
| 375 | .event_name = "br_inst_retired.all_taken_branches", |
| 376 | }, |
| 377 | { |
| 378 | .event_name = 0, |
| 379 | }, |
| 380 | }; |
| 381 | |
| 382 | PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table); |
| 383 | |