blob: 0db04c1966a88468c2799085f6a18e660b60db90 [file] [log] [blame]
Mohsin Kazmia0a68332020-07-16 12:55:42 +00001/*
2 * Copyright (c) 2018 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16#ifndef __included_virtio_pci_legacy_h__
17#define __included_virtio_pci_legacy_h__
18
19/*
20 * VirtIO Header, located in BAR 0.
21 */
22#define VIRTIO_PCI_HOST_FEATURES 0 /* host's supported features (32bit, RO) */
23#define VIRTIO_PCI_GUEST_FEATURES 4 /* guest's supported features (32, RW) */
24#define VIRTIO_PCI_QUEUE_PFN 8 /* physical address of VQ (32, RW) */
25#define VIRTIO_PCI_QUEUE_NUM 12 /* number of ring entries (16, RO) */
26#define VIRTIO_PCI_QUEUE_SEL 14 /* current VQ selection (16, RW) */
27#define VIRTIO_PCI_QUEUE_NOTIFY 16 /* notify host regarding VQ (16, RW) */
28#define VIRTIO_PCI_STATUS 18 /* device status register (8, RW) */
29#define VIRTIO_PCI_ISR 19 /* interrupt status register, reading
30 * also clears the register (8, RO) */
31/* Only if MSIX is enabled: */
32#define VIRTIO_MSI_CONFIG_VECTOR 20 /* configuration change vector (16, RW) */
33#define VIRTIO_MSI_QUEUE_VECTOR 22 /* vector for selected VQ notifications
34 (16, RW) */
35#define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12
36
37#endif /* __included_virtio_pci_legacy_h__ */
38/*
39 * fd.io coding-style-patch-verification: ON
40 *
41 * Local Variables:
42 * eval: (c-set-style "gnu")
43 * End:
44 */