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gerrit.nordix.org / fdio / vpp / ce8805c6a62893ec52a09c6acec48cce32c76706 / . / dpdk / dpdk-17.02_patches / 0007-add-hardware-checksum-offload-for-tunnel-pa.patch
blob: bbcce4864107c5cb2e6d7e80a94c1383a9da26b2 [file] [log] [blame]
Damjan Marion0f60ff82017-03-30 17:58:42 +0200[diff] [blame]1From f0dda2ab16635894b1e3836d0b960b9270a3b491 Mon Sep 17 00:00:00 2001
2From: Shahaf Shuler <shahafs@mellanox.com>
3Date: Thu, 2 Mar 2017 11:05:44 +0200
4Subject: [PATCH] net/mlx5: add hardware checksum offload for tunnel packets
5
6Prior to this commit Tx checksum offload was supported only for the
7inner headers.
8This commit adds support for the hardware to compute the checksum for the
9outer headers as well.
10
11The support is for tunneling protocols GRE and VXLAN.
12
13Signed-off-by: Shahaf Shuler <shahafs@mellanox.com>
14Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
15---
16 doc/guides/nics/features/mlx5.ini | 2 ++
17 doc/guides/nics/mlx5.rst | 3 ++-
18 drivers/net/mlx5/mlx5.c | 7 +++++++
19 drivers/net/mlx5/mlx5.h | 2 ++
20 drivers/net/mlx5/mlx5_ethdev.c | 2 ++
21 drivers/net/mlx5/mlx5_prm.h | 6 ++++++
22 drivers/net/mlx5/mlx5_rxtx.c | 14 +++++++++++++-
23 drivers/net/mlx5/mlx5_rxtx.h | 2 ++
24 drivers/net/mlx5/mlx5_txq.c | 2 ++
25 9 files changed, 38 insertions(+), 2 deletions(-)
26
27diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini
28index 8df25ce..1814f82 100644
29--- a/doc/guides/nics/features/mlx5.ini
30+++ b/doc/guides/nics/features/mlx5.ini
31@@ -27,6 +27,8 @@ CRC offload = Y
32 VLAN offload = Y
33 L3 checksum offload = Y
34 L4 checksum offload = Y
35+Inner L3 checksum = Y
36+Inner L4 checksum = Y
37 Packet type parsing = Y
38 Basic stats = Y
39 Stats per queue = Y
40diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
41index 9b0ba29..41f3a47 100644
42--- a/doc/guides/nics/mlx5.rst
43+++ b/doc/guides/nics/mlx5.rst
44@@ -91,13 +91,14 @@ Features
45 - KVM and VMware ESX SR-IOV modes are supported.
46 - RSS hash result is supported.
47 - Hardware TSO.
48+- Hardware checksum TX offload for VXLAN and GRE.
49
50 Limitations
51 -----------
52
53 - Inner RSS for VXLAN frames is not supported yet.
54 - Port statistics through software counters only.
55-- Hardware checksum offloads for VXLAN inner header are not supported yet.
56+- Hardware checksum RX offloads for VXLAN inner header are not supported yet.
57 - Secondary process RX is not supported.
58
59 Configuration
60diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
61index 03ed3b3..6f42948 100644
62--- a/drivers/net/mlx5/mlx5.c
63+++ b/drivers/net/mlx5/mlx5.c
64@@ -375,6 +375,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
65 struct ibv_device_attr device_attr;
66 unsigned int sriov;
67 unsigned int mps;
68+ unsigned int tunnel_en;
69 int idx;
70 int i;
71
72@@ -429,12 +430,17 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
73 * as all ConnectX-5 devices.
74 */
75 switch (pci_dev->id.device_id) {
76+ case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
77+ tunnel_en = 1;
78+ mps = 0;
79+ break;
80 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
81 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
82 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
83 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
84 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
85 mps = 1;
86+ tunnel_en = 1;
87 break;
88 default:
89 mps = 0;
90@@ -539,6 +545,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
91 priv->mtu = ETHER_MTU;
92 priv->mps = mps; /* Enable MPW by default if supported. */
93 priv->cqe_comp = 1; /* Enable compression by default. */
94+ priv->tunnel_en = tunnel_en;
95 err = mlx5_args(priv, pci_dev->device.devargs);
96 if (err) {
97 ERROR("failed to process device arguments: %s",
98diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
99index 93f129b..870e01f 100644
100--- a/drivers/net/mlx5/mlx5.h
101+++ b/drivers/net/mlx5/mlx5.h
102@@ -127,6 +127,8 @@ struct priv {
103 unsigned int cqe_comp:1; /* Whether CQE compression is enabled. */
104 unsigned int pending_alarm:1; /* An alarm is pending. */
105 unsigned int tso:1; /* Whether TSO is supported. */
106+ unsigned int tunnel_en:1;
107+ /* Whether Tx offloads for tunneled packets are supported. */
108 unsigned int max_tso_payload_sz; /* Maximum TCP payload for TSO. */
109 unsigned int txq_inline; /* Maximum packet size for inlining. */
110 unsigned int txqs_inline; /* Queue number threshold for inlining. */
111diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
112index 5542193..8be9e77 100644
113--- a/drivers/net/mlx5/mlx5_ethdev.c
114+++ b/drivers/net/mlx5/mlx5_ethdev.c
115@@ -695,6 +695,8 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
116 DEV_TX_OFFLOAD_TCP_CKSUM);
117 if (priv->tso)
118 info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
119+ if (priv->tunnel_en)
120+ info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
121 if (priv_get_ifname(priv, &ifname) == 0)
122 info->if_index = if_nametoindex(ifname);
123 /* FIXME: RETA update/query API expects the callee to know the size of
124diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
125index 3318668..0a77f5b 100644
126--- a/drivers/net/mlx5/mlx5_prm.h
127+++ b/drivers/net/mlx5/mlx5_prm.h
128@@ -120,6 +120,12 @@
129 /* Tunnel packet bit in the CQE. */
130 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
131
132+/* Inner L3 checksum offload (Tunneled packets only). */
133+#define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
134+
135+/* Inner L4 checksum offload (Tunneled packets only). */
136+#define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
137+
138 /* INVALID is used by packets matching no flow rules. */
139 #define MLX5_FLOW_MARK_INVALID 0
140
141diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
142index 98889f6..c2eb891 100644
143--- a/drivers/net/mlx5/mlx5_rxtx.c
144+++ b/drivers/net/mlx5/mlx5_rxtx.c
145@@ -443,7 +443,19 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
146 /* Should we enable HW CKSUM offload */
147 if (buf->ol_flags &
148 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
149- cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
150+ const uint64_t is_tunneled = buf->ol_flags &
151+ (PKT_TX_TUNNEL_GRE |
152+ PKT_TX_TUNNEL_VXLAN);
153+
154+ if (is_tunneled && txq->tunnel_en) {
155+ cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
156+ MLX5_ETH_WQE_L4_INNER_CSUM;
157+ if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
158+ cs_flags |= MLX5_ETH_WQE_L3_CSUM;
159+ } else {
160+ cs_flags = MLX5_ETH_WQE_L3_CSUM |
161+ MLX5_ETH_WQE_L4_CSUM;
162+ }
163 }
164 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
165 /* Replace the Ethernet type by the VLAN if necessary. */
166diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
167index 6b328cf..9669564 100644
168--- a/drivers/net/mlx5/mlx5_rxtx.h
169+++ b/drivers/net/mlx5/mlx5_rxtx.h
170@@ -256,6 +256,8 @@ struct txq {
171 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
172 uint16_t inline_en:1; /* When set inline is enabled. */
173 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
174+ uint16_t tunnel_en:1;
175+ /* When set TX offload for tunneled packets are supported. */
176 uint32_t qp_num_8s; /* QP number shifted by 8. */
177 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
178 volatile void *wqes; /* Work queue (use volatile to write into). */
179diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
180index 995b763..9d0c00f 100644
181--- a/drivers/net/mlx5/mlx5_txq.c
182+++ b/drivers/net/mlx5/mlx5_txq.c
183@@ -356,6 +356,8 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,
184 max_tso_inline);
185 tmpl.txq.tso_en = 1;
186 }
187+ if (priv->tunnel_en)
188+ tmpl.txq.tunnel_en = 1;
189 tmpl.qp = ibv_exp_create_qp(priv->ctx, &attr.init);
190 if (tmpl.qp == NULL) {
191 ret = (errno ? errno : EINVAL);
192--
1932.7.4
194