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wdenk71f95112003-06-15 22:40:42 +00001/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00002 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05003 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00006 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenk71f95112003-06-15 22:40:42 +00008 */
9
10#ifndef _MMC_H_
11#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000012
Andy Fleming272cc702008-10-30 16:41:01 -050013#include <linux/list.h>
Lad, Prabhakar0d986e62012-06-24 21:35:20 +000014#include <linux/compiler.h>
Andy Fleming272cc702008-10-30 16:41:01 -050015
16#define SD_VERSION_SD 0x20000
Jaehoon Chung1741c642013-01-29 22:58:16 +000017#define SD_VERSION_3 (SD_VERSION_SD | 0x300)
Jaehoon Chung64f4a612013-01-29 19:31:16 +000018#define SD_VERSION_2 (SD_VERSION_SD | 0x200)
19#define SD_VERSION_1_0 (SD_VERSION_SD | 0x100)
20#define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a)
Andy Fleming272cc702008-10-30 16:41:01 -050021#define MMC_VERSION_MMC 0x10000
22#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
Jaehoon Chung64f4a612013-01-29 19:31:16 +000023#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x102)
24#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x104)
25#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x202)
26#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x300)
27#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x400)
28#define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x401)
29#define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x402)
30#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403)
31#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429)
32#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405)
Andy Fleming272cc702008-10-30 16:41:01 -050033
34#define MMC_MODE_HS 0x001
35#define MMC_MODE_HS_52MHz 0x010
36#define MMC_MODE_4BIT 0x100
37#define MMC_MODE_8BIT 0x200
Thomas Choud52ebf12010-12-24 13:12:21 +000038#define MMC_MODE_SPI 0x400
Łukasz Majewskib1f1e822011-07-05 02:19:44 +000039#define MMC_MODE_HC 0x800
Andy Fleming272cc702008-10-30 16:41:01 -050040
Łukasz Majewski62722032012-03-12 22:07:18 +000041#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT)
42#define MMC_MODE_WIDTH_BITS_SHIFT 8
43
Andy Fleming272cc702008-10-30 16:41:01 -050044#define SD_DATA_4BIT 0x00040000
45
Albin Tonnerre79b91de2009-08-22 14:21:53 +020046#define IS_SD(x) (x->version & SD_VERSION_SD)
Andy Fleming272cc702008-10-30 16:41:01 -050047
48#define MMC_DATA_READ 1
49#define MMC_DATA_WRITE 2
50
51#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
52#define UNUSABLE_ERR -17 /* Unusable Card */
53#define COMM_ERR -18 /* Communications Error */
54#define TIMEOUT -19
Che-Liang Chioue9550442012-11-28 15:21:13 +000055#define IN_PROGRESS -20 /* operation is in progress */
Andy Fleming272cc702008-10-30 16:41:01 -050056
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020057#define MMC_CMD_GO_IDLE_STATE 0
58#define MMC_CMD_SEND_OP_COND 1
59#define MMC_CMD_ALL_SEND_CID 2
60#define MMC_CMD_SET_RELATIVE_ADDR 3
61#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050062#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020063#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050064#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020065#define MMC_CMD_SEND_CSD 9
66#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -050067#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020068#define MMC_CMD_SEND_STATUS 13
69#define MMC_CMD_SET_BLOCKLEN 16
70#define MMC_CMD_READ_SINGLE_BLOCK 17
71#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Andy Fleming272cc702008-10-30 16:41:01 -050072#define MMC_CMD_WRITE_SINGLE_BLOCK 24
73#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Lei Wene6f99a52011-06-22 17:03:31 +000074#define MMC_CMD_ERASE_GROUP_START 35
75#define MMC_CMD_ERASE_GROUP_END 36
76#define MMC_CMD_ERASE 38
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020077#define MMC_CMD_APP_CMD 55
Thomas Choud52ebf12010-12-24 13:12:21 +000078#define MMC_CMD_SPI_READ_OCR 58
79#define MMC_CMD_SPI_CRC_ON_OFF 59
Amar3690d6d2013-04-27 11:42:58 +053080#define MMC_CMD_RES_MAN 62
81
82#define MMC_CMD62_ARG1 0xefac62ec
83#define MMC_CMD62_ARG2 0xcbaea7
84
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020085
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020086#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -050087#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020088#define SD_CMD_SEND_IF_COND 8
89
90#define SD_CMD_APP_SET_BUS_WIDTH 6
Lei Wene6f99a52011-06-22 17:03:31 +000091#define SD_CMD_ERASE_WR_BLK_START 32
92#define SD_CMD_ERASE_WR_BLK_END 33
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020093#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -050094#define SD_CMD_APP_SEND_SCR 51
95
96/* SCR definitions in different words */
97#define SD_HIGHSPEED_BUSY 0x00020000
98#define SD_HIGHSPEED_SUPPORTED 0x00020000
99
100#define MMC_HS_TIMING 0x00000100
101#define MMC_HS_52MHZ 0x2
102
Thomas Chouabe2c932011-04-19 03:48:31 +0000103#define OCR_BUSY 0x80000000
104#define OCR_HCS 0x40000000
Raffaele Recalcati31cacba2011-03-11 02:01:13 +0000105#define OCR_VOLTAGE_MASK 0x007FFF80
106#define OCR_ACCESS_MODE 0x60000000
Andy Fleming272cc702008-10-30 16:41:01 -0500107
Lei Wene6f99a52011-06-22 17:03:31 +0000108#define SECURE_ERASE 0x80000000
109
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000110#define MMC_STATUS_MASK (~0x0206BF7F)
Thomas Chouabe2c932011-04-19 03:48:31 +0000111#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
112#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Choued018b22011-04-19 03:48:32 +0000113#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000114
Jan Kloetzked617c422012-02-05 22:29:12 +0000115#define MMC_STATE_PRG (7 << 9)
116
Andy Fleming272cc702008-10-30 16:41:01 -0500117#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
118#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
119#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
120#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
121#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
122#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
123#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
124#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
125#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
126#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
127#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
128#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
129#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
130#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
131#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
132#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
133#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
134
135#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
136#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
137 addressed by index which are
138 1 in value field */
139#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
140 addressed by index, which are
141 1 in value field */
142#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
143
144#define SD_SWITCH_CHECK 0
145#define SD_SWITCH_SWITCH 1
146
147/*
148 * EXT_CSD fields
149 */
Stephen Warrenf866a462013-06-11 15:14:01 -0600150#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
Oliver Metz1937e5a2013-10-01 20:32:07 +0200151#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
Lei Wen0560db12011-10-03 20:35:10 +0000152#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
Stephen Warrenf866a462013-06-11 15:14:01 -0600153#define EXT_CSD_RPMB_MULT 168 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000154#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
Amar3690d6d2013-04-27 11:42:58 +0530155#define EXT_CSD_BOOT_BUS_WIDTH 177
Lei Wen0560db12011-10-03 20:35:10 +0000156#define EXT_CSD_PART_CONF 179 /* R/W */
157#define EXT_CSD_BUS_WIDTH 183 /* R/W */
158#define EXT_CSD_HS_TIMING 185 /* R/W */
159#define EXT_CSD_REV 192 /* RO */
160#define EXT_CSD_CARD_TYPE 196 /* RO */
161#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
Stephen Warrenf866a462013-06-11 15:14:01 -0600162#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000163#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Stephen Warren8948ea82012-07-30 10:55:43 +0000164#define EXT_CSD_BOOT_MULT 226 /* RO */
Andy Fleming272cc702008-10-30 16:41:01 -0500165
166/*
167 * EXT_CSD field definitions
168 */
169
Thomas Chouabe2c932011-04-19 03:48:31 +0000170#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
171#define EXT_CSD_CMD_SET_SECURE (1 << 1)
172#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Fleming272cc702008-10-30 16:41:01 -0500173
Thomas Chouabe2c932011-04-19 03:48:31 +0000174#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
175#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Andy Fleming272cc702008-10-30 16:41:01 -0500176
177#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
178#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
179#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200180
Amar3690d6d2013-04-27 11:42:58 +0530181#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
182#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
183#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
184#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
185
186#define EXT_CSD_BOOT_ACK(x) (x << 6)
187#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
188#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
189
Tom Rini5a99b9d2014-02-05 10:24:22 -0500190#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
191#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
192#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
Amar3690d6d2013-04-27 11:42:58 +0530193
Andy Fleming1de97f92008-10-30 16:31:39 -0500194#define R1_ILLEGAL_COMMAND (1 << 22)
195#define R1_APP_CMD (1 << 5)
196
Andy Fleming272cc702008-10-30 16:41:01 -0500197#define MMC_RSP_PRESENT (1 << 0)
Thomas Chouabe2c932011-04-19 03:48:31 +0000198#define MMC_RSP_136 (1 << 1) /* 136 bit response */
199#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
200#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
201#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Fleming272cc702008-10-30 16:41:01 -0500202
Thomas Chouabe2c932011-04-19 03:48:31 +0000203#define MMC_RSP_NONE (0)
204#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500205#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
206 MMC_RSP_BUSY)
Thomas Chouabe2c932011-04-19 03:48:31 +0000207#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
208#define MMC_RSP_R3 (MMC_RSP_PRESENT)
209#define MMC_RSP_R4 (MMC_RSP_PRESENT)
210#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
211#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
212#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500213
Lei Wenbc897b12011-05-02 16:26:26 +0000214#define MMCPART_NOAVAILABLE (0xff)
215#define PART_ACCESS_MASK (0x7)
216#define PART_SUPPORT (0x1)
Oliver Metz1937e5a2013-10-01 20:32:07 +0200217#define PART_ENH_ATTRIB (0x1f)
wdenk71f95112003-06-15 22:40:42 +0000218
Simon Glass8bfa1952013-04-03 08:54:30 +0000219/* Maximum block size for MMC */
220#define MMC_MAX_BLOCK_LEN 512
221
Amar3690d6d2013-04-27 11:42:58 +0530222/* The number of MMC physical partitions. These consist of:
223 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
224 */
225#define MMC_NUM_BOOT_PARTITION 2
226
Andy Fleming1de97f92008-10-30 16:31:39 -0500227struct mmc_cid {
228 unsigned long psn;
229 unsigned short oid;
230 unsigned char mid;
231 unsigned char prv;
232 unsigned char mdt;
233 char pnm[7];
234};
235
Andy Fleming272cc702008-10-30 16:41:01 -0500236struct mmc_cmd {
237 ushort cmdidx;
238 uint resp_type;
239 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530240 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500241};
242
243struct mmc_data {
244 union {
245 char *dest;
246 const char *src; /* src buffers don't get written to */
247 };
248 uint flags;
249 uint blocks;
250 uint blocksize;
251};
252
253struct mmc {
254 struct list_head link;
255 char name[32];
256 void *priv;
257 uint voltages;
258 uint version;
Lei Wenbc897b12011-05-02 16:26:26 +0000259 uint has_init;
Andy Fleming272cc702008-10-30 16:41:01 -0500260 uint f_min;
261 uint f_max;
262 int high_capacity;
263 uint bus_width;
264 uint clock;
265 uint card_caps;
266 uint host_caps;
267 uint ocr;
Markus Niebelab711882013-12-16 13:40:46 +0100268 uint dsr;
269 uint dsr_imp;
Andy Fleming272cc702008-10-30 16:41:01 -0500270 uint scr[2];
271 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530272 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500273 ushort rca;
Lei Wenbc897b12011-05-02 16:26:26 +0000274 char part_config;
275 char part_num;
Andy Fleming272cc702008-10-30 16:41:01 -0500276 uint tran_speed;
277 uint read_bl_len;
278 uint write_bl_len;
Lei Wene6f99a52011-06-22 17:03:31 +0000279 uint erase_grp_size;
Andy Fleming272cc702008-10-30 16:41:01 -0500280 u64 capacity;
Stephen Warrenf866a462013-06-11 15:14:01 -0600281 u64 capacity_user;
282 u64 capacity_boot;
283 u64 capacity_rpmb;
284 u64 capacity_gp[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500285 block_dev_desc_t block_dev;
286 int (*send_cmd)(struct mmc *mmc,
287 struct mmc_cmd *cmd, struct mmc_data *data);
288 void (*set_ios)(struct mmc *mmc);
289 int (*init)(struct mmc *mmc);
Thierry Reding48972d92012-01-02 01:15:37 +0000290 int (*getcd)(struct mmc *mmc);
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +0000291 int (*getwp)(struct mmc *mmc);
Sandeep Paulraj57418d22010-12-20 20:01:21 -0500292 uint b_max;
Che-Liang Chioue9550442012-11-28 15:21:13 +0000293 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
294 char init_in_progress; /* 1 if we have done mmc_start_init() */
295 char preinit; /* start init as early as possible */
296 uint op_cond_response; /* the response byte from the last op_cond */
Andy Fleming272cc702008-10-30 16:41:01 -0500297};
298
299int mmc_register(struct mmc *mmc);
300int mmc_initialize(bd_t *bis);
301int mmc_init(struct mmc *mmc);
302int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Jerry Huang4a6ee172010-11-25 17:06:07 +0000303void mmc_set_clock(struct mmc *mmc, uint clock);
Andy Fleming272cc702008-10-30 16:41:01 -0500304struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700305int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500306void print_mmc_devices(char separator);
Lei Wenea6ebe22011-05-02 16:26:25 +0000307int get_mmc_num(void);
Thierry Reding314284b2012-01-02 01:15:36 +0000308int board_mmc_getcd(struct mmc *mmc);
Lei Wenbc897b12011-05-02 16:26:26 +0000309int mmc_switch_part(int dev_num, unsigned int part_num);
Thierry Reding48972d92012-01-02 01:15:37 +0000310int mmc_getcd(struct mmc *mmc);
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +0000311int mmc_getwp(struct mmc *mmc);
Markus Niebelab711882013-12-16 13:40:46 +0100312int mmc_set_dsr(struct mmc *mmc, u16 val);
Amar3690d6d2013-04-27 11:42:58 +0530313/* Function to change the size of boot partition and rpmb partitions */
314int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
315 unsigned long rpmbsize);
Tom Rini792970b2014-02-05 10:24:21 -0500316/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
317int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
Tom Rini5a99b9d2014-02-05 10:24:22 -0500318/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
319int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
Andy Fleming272cc702008-10-30 16:41:01 -0500320
Che-Liang Chioue9550442012-11-28 15:21:13 +0000321/**
322 * Start device initialization and return immediately; it does not block on
323 * polling OCR (operation condition register) status. Then you should call
324 * mmc_init, which would block on polling OCR status and complete the device
325 * initializatin.
326 *
327 * @param mmc Pointer to a MMC device struct
328 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
329 */
330int mmc_start_init(struct mmc *mmc);
331
332/**
333 * Set preinit flag of mmc device.
334 *
335 * This will cause the device to be pre-inited during mmc_initialize(),
336 * which may save boot time if the device is not accessed until later.
337 * Some eMMC devices take 200-300ms to init, but unfortunately they
338 * must be sent a series of commands to even get them to start preparing
339 * for operation.
340 *
341 * @param mmc Pointer to a MMC device struct
342 * @param preinit preinit flag value
343 */
344void mmc_set_preinit(struct mmc *mmc, int preinit);
345
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200346#ifdef CONFIG_GENERIC_MMC
Paul Burton8687d5c2013-09-04 16:12:26 +0100347#ifdef CONFIG_MMC_SPI
Thomas Choud52ebf12010-12-24 13:12:21 +0000348#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
Paul Burton8687d5c2013-09-04 16:12:26 +0100349#else
350#define mmc_host_is_spi(mmc) 0
351#endif
Thomas Choud52ebf12010-12-24 13:12:21 +0000352struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200353#else
Andy Fleming272cc702008-10-30 16:41:01 -0500354int mmc_legacy_init(int verbose);
355#endif
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200356
wdenk71f95112003-06-15 22:40:42 +0000357#endif /* _MMC_H_ */