wdenk | 71f9511 | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 1 | /* |
Jerry Huang | 4a6ee17 | 2010-11-25 17:06:07 +0000 | [diff] [blame] | 2 | * Copyright 2008,2010 Freescale Semiconductor, Inc |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 3 | * Andy Fleming |
| 4 | * |
| 5 | * Based (loosely) on the Linux code |
wdenk | 71f9511 | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 6 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 71f9511 | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef _MMC_H_ |
| 11 | #define _MMC_H_ |
wdenk | 71f9511 | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 12 | |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 13 | #include <linux/list.h> |
Lad, Prabhakar | 0d986e6 | 2012-06-24 21:35:20 +0000 | [diff] [blame] | 14 | #include <linux/compiler.h> |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 15 | |
| 16 | #define SD_VERSION_SD 0x20000 |
Jaehoon Chung | 1741c64 | 2013-01-29 22:58:16 +0000 | [diff] [blame] | 17 | #define SD_VERSION_3 (SD_VERSION_SD | 0x300) |
Jaehoon Chung | 64f4a61 | 2013-01-29 19:31:16 +0000 | [diff] [blame] | 18 | #define SD_VERSION_2 (SD_VERSION_SD | 0x200) |
| 19 | #define SD_VERSION_1_0 (SD_VERSION_SD | 0x100) |
| 20 | #define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a) |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 21 | #define MMC_VERSION_MMC 0x10000 |
| 22 | #define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) |
Jaehoon Chung | 64f4a61 | 2013-01-29 19:31:16 +0000 | [diff] [blame] | 23 | #define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x102) |
| 24 | #define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x104) |
| 25 | #define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x202) |
| 26 | #define MMC_VERSION_3 (MMC_VERSION_MMC | 0x300) |
| 27 | #define MMC_VERSION_4 (MMC_VERSION_MMC | 0x400) |
| 28 | #define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x401) |
| 29 | #define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x402) |
| 30 | #define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403) |
| 31 | #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) |
| 32 | #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405) |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 33 | |
| 34 | #define MMC_MODE_HS 0x001 |
| 35 | #define MMC_MODE_HS_52MHz 0x010 |
| 36 | #define MMC_MODE_4BIT 0x100 |
| 37 | #define MMC_MODE_8BIT 0x200 |
Thomas Chou | d52ebf1 | 2010-12-24 13:12:21 +0000 | [diff] [blame] | 38 | #define MMC_MODE_SPI 0x400 |
Łukasz Majewski | b1f1e82 | 2011-07-05 02:19:44 +0000 | [diff] [blame] | 39 | #define MMC_MODE_HC 0x800 |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 40 | |
Łukasz Majewski | 6272203 | 2012-03-12 22:07:18 +0000 | [diff] [blame] | 41 | #define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT) |
| 42 | #define MMC_MODE_WIDTH_BITS_SHIFT 8 |
| 43 | |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 44 | #define SD_DATA_4BIT 0x00040000 |
| 45 | |
Albin Tonnerre | 79b91de | 2009-08-22 14:21:53 +0200 | [diff] [blame] | 46 | #define IS_SD(x) (x->version & SD_VERSION_SD) |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 47 | |
| 48 | #define MMC_DATA_READ 1 |
| 49 | #define MMC_DATA_WRITE 2 |
| 50 | |
| 51 | #define NO_CARD_ERR -16 /* No SD/MMC card inserted */ |
| 52 | #define UNUSABLE_ERR -17 /* Unusable Card */ |
| 53 | #define COMM_ERR -18 /* Communications Error */ |
| 54 | #define TIMEOUT -19 |
Che-Liang Chiou | e955044 | 2012-11-28 15:21:13 +0000 | [diff] [blame] | 55 | #define IN_PROGRESS -20 /* operation is in progress */ |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 56 | |
Haavard Skinnemoen | 341188b | 2008-05-22 11:09:59 +0200 | [diff] [blame] | 57 | #define MMC_CMD_GO_IDLE_STATE 0 |
| 58 | #define MMC_CMD_SEND_OP_COND 1 |
| 59 | #define MMC_CMD_ALL_SEND_CID 2 |
| 60 | #define MMC_CMD_SET_RELATIVE_ADDR 3 |
| 61 | #define MMC_CMD_SET_DSR 4 |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 62 | #define MMC_CMD_SWITCH 6 |
Haavard Skinnemoen | 341188b | 2008-05-22 11:09:59 +0200 | [diff] [blame] | 63 | #define MMC_CMD_SELECT_CARD 7 |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 64 | #define MMC_CMD_SEND_EXT_CSD 8 |
Haavard Skinnemoen | 341188b | 2008-05-22 11:09:59 +0200 | [diff] [blame] | 65 | #define MMC_CMD_SEND_CSD 9 |
| 66 | #define MMC_CMD_SEND_CID 10 |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 67 | #define MMC_CMD_STOP_TRANSMISSION 12 |
Haavard Skinnemoen | 341188b | 2008-05-22 11:09:59 +0200 | [diff] [blame] | 68 | #define MMC_CMD_SEND_STATUS 13 |
| 69 | #define MMC_CMD_SET_BLOCKLEN 16 |
| 70 | #define MMC_CMD_READ_SINGLE_BLOCK 17 |
| 71 | #define MMC_CMD_READ_MULTIPLE_BLOCK 18 |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 72 | #define MMC_CMD_WRITE_SINGLE_BLOCK 24 |
| 73 | #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 |
Lei Wen | e6f99a5 | 2011-06-22 17:03:31 +0000 | [diff] [blame] | 74 | #define MMC_CMD_ERASE_GROUP_START 35 |
| 75 | #define MMC_CMD_ERASE_GROUP_END 36 |
| 76 | #define MMC_CMD_ERASE 38 |
Haavard Skinnemoen | 341188b | 2008-05-22 11:09:59 +0200 | [diff] [blame] | 77 | #define MMC_CMD_APP_CMD 55 |
Thomas Chou | d52ebf1 | 2010-12-24 13:12:21 +0000 | [diff] [blame] | 78 | #define MMC_CMD_SPI_READ_OCR 58 |
| 79 | #define MMC_CMD_SPI_CRC_ON_OFF 59 |
Amar | 3690d6d | 2013-04-27 11:42:58 +0530 | [diff] [blame] | 80 | #define MMC_CMD_RES_MAN 62 |
| 81 | |
| 82 | #define MMC_CMD62_ARG1 0xefac62ec |
| 83 | #define MMC_CMD62_ARG2 0xcbaea7 |
| 84 | |
Haavard Skinnemoen | 341188b | 2008-05-22 11:09:59 +0200 | [diff] [blame] | 85 | |
Haavard Skinnemoen | 341188b | 2008-05-22 11:09:59 +0200 | [diff] [blame] | 86 | #define SD_CMD_SEND_RELATIVE_ADDR 3 |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 87 | #define SD_CMD_SWITCH_FUNC 6 |
Haavard Skinnemoen | 341188b | 2008-05-22 11:09:59 +0200 | [diff] [blame] | 88 | #define SD_CMD_SEND_IF_COND 8 |
| 89 | |
| 90 | #define SD_CMD_APP_SET_BUS_WIDTH 6 |
Lei Wen | e6f99a5 | 2011-06-22 17:03:31 +0000 | [diff] [blame] | 91 | #define SD_CMD_ERASE_WR_BLK_START 32 |
| 92 | #define SD_CMD_ERASE_WR_BLK_END 33 |
Haavard Skinnemoen | 341188b | 2008-05-22 11:09:59 +0200 | [diff] [blame] | 93 | #define SD_CMD_APP_SEND_OP_COND 41 |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 94 | #define SD_CMD_APP_SEND_SCR 51 |
| 95 | |
| 96 | /* SCR definitions in different words */ |
| 97 | #define SD_HIGHSPEED_BUSY 0x00020000 |
| 98 | #define SD_HIGHSPEED_SUPPORTED 0x00020000 |
| 99 | |
| 100 | #define MMC_HS_TIMING 0x00000100 |
| 101 | #define MMC_HS_52MHZ 0x2 |
| 102 | |
Thomas Chou | abe2c93 | 2011-04-19 03:48:31 +0000 | [diff] [blame] | 103 | #define OCR_BUSY 0x80000000 |
| 104 | #define OCR_HCS 0x40000000 |
Raffaele Recalcati | 31cacba | 2011-03-11 02:01:13 +0000 | [diff] [blame] | 105 | #define OCR_VOLTAGE_MASK 0x007FFF80 |
| 106 | #define OCR_ACCESS_MODE 0x60000000 |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 107 | |
Lei Wen | e6f99a5 | 2011-06-22 17:03:31 +0000 | [diff] [blame] | 108 | #define SECURE_ERASE 0x80000000 |
| 109 | |
Raffaele Recalcati | 5d4fc8d | 2011-03-11 02:01:12 +0000 | [diff] [blame] | 110 | #define MMC_STATUS_MASK (~0x0206BF7F) |
Thomas Chou | abe2c93 | 2011-04-19 03:48:31 +0000 | [diff] [blame] | 111 | #define MMC_STATUS_RDY_FOR_DATA (1 << 8) |
| 112 | #define MMC_STATUS_CURR_STATE (0xf << 9) |
Thomas Chou | ed018b2 | 2011-04-19 03:48:32 +0000 | [diff] [blame] | 113 | #define MMC_STATUS_ERROR (1 << 19) |
Raffaele Recalcati | 5d4fc8d | 2011-03-11 02:01:12 +0000 | [diff] [blame] | 114 | |
Jan Kloetzke | d617c42 | 2012-02-05 22:29:12 +0000 | [diff] [blame] | 115 | #define MMC_STATE_PRG (7 << 9) |
| 116 | |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 117 | #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ |
| 118 | #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ |
| 119 | #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ |
| 120 | #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ |
| 121 | #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ |
| 122 | #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ |
| 123 | #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ |
| 124 | #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ |
| 125 | #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ |
| 126 | #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ |
| 127 | #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ |
| 128 | #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ |
| 129 | #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ |
| 130 | #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ |
| 131 | #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ |
| 132 | #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ |
| 133 | #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ |
| 134 | |
| 135 | #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ |
| 136 | #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte |
| 137 | addressed by index which are |
| 138 | 1 in value field */ |
| 139 | #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte |
| 140 | addressed by index, which are |
| 141 | 1 in value field */ |
| 142 | #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ |
| 143 | |
| 144 | #define SD_SWITCH_CHECK 0 |
| 145 | #define SD_SWITCH_SWITCH 1 |
| 146 | |
| 147 | /* |
| 148 | * EXT_CSD fields |
| 149 | */ |
Stephen Warren | f866a46 | 2013-06-11 15:14:01 -0600 | [diff] [blame] | 150 | #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ |
Oliver Metz | 1937e5a | 2013-10-01 20:32:07 +0200 | [diff] [blame] | 151 | #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ |
Lei Wen | 0560db1 | 2011-10-03 20:35:10 +0000 | [diff] [blame] | 152 | #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ |
Stephen Warren | f866a46 | 2013-06-11 15:14:01 -0600 | [diff] [blame] | 153 | #define EXT_CSD_RPMB_MULT 168 /* RO */ |
Lei Wen | 0560db1 | 2011-10-03 20:35:10 +0000 | [diff] [blame] | 154 | #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ |
Amar | 3690d6d | 2013-04-27 11:42:58 +0530 | [diff] [blame] | 155 | #define EXT_CSD_BOOT_BUS_WIDTH 177 |
Lei Wen | 0560db1 | 2011-10-03 20:35:10 +0000 | [diff] [blame] | 156 | #define EXT_CSD_PART_CONF 179 /* R/W */ |
| 157 | #define EXT_CSD_BUS_WIDTH 183 /* R/W */ |
| 158 | #define EXT_CSD_HS_TIMING 185 /* R/W */ |
| 159 | #define EXT_CSD_REV 192 /* RO */ |
| 160 | #define EXT_CSD_CARD_TYPE 196 /* RO */ |
| 161 | #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ |
Stephen Warren | f866a46 | 2013-06-11 15:14:01 -0600 | [diff] [blame] | 162 | #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ |
Lei Wen | 0560db1 | 2011-10-03 20:35:10 +0000 | [diff] [blame] | 163 | #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ |
Stephen Warren | 8948ea8 | 2012-07-30 10:55:43 +0000 | [diff] [blame] | 164 | #define EXT_CSD_BOOT_MULT 226 /* RO */ |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 165 | |
| 166 | /* |
| 167 | * EXT_CSD field definitions |
| 168 | */ |
| 169 | |
Thomas Chou | abe2c93 | 2011-04-19 03:48:31 +0000 | [diff] [blame] | 170 | #define EXT_CSD_CMD_SET_NORMAL (1 << 0) |
| 171 | #define EXT_CSD_CMD_SET_SECURE (1 << 1) |
| 172 | #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 173 | |
Thomas Chou | abe2c93 | 2011-04-19 03:48:31 +0000 | [diff] [blame] | 174 | #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ |
| 175 | #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 176 | |
| 177 | #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ |
| 178 | #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ |
| 179 | #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ |
Haavard Skinnemoen | 341188b | 2008-05-22 11:09:59 +0200 | [diff] [blame] | 180 | |
Amar | 3690d6d | 2013-04-27 11:42:58 +0530 | [diff] [blame] | 181 | #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) |
| 182 | #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) |
| 183 | #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) |
| 184 | #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) |
| 185 | |
| 186 | #define EXT_CSD_BOOT_ACK(x) (x << 6) |
| 187 | #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) |
| 188 | #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) |
| 189 | |
| 190 | |
Andy Fleming | 1de97f9 | 2008-10-30 16:31:39 -0500 | [diff] [blame] | 191 | #define R1_ILLEGAL_COMMAND (1 << 22) |
| 192 | #define R1_APP_CMD (1 << 5) |
| 193 | |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 194 | #define MMC_RSP_PRESENT (1 << 0) |
Thomas Chou | abe2c93 | 2011-04-19 03:48:31 +0000 | [diff] [blame] | 195 | #define MMC_RSP_136 (1 << 1) /* 136 bit response */ |
| 196 | #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ |
| 197 | #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ |
| 198 | #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 199 | |
Thomas Chou | abe2c93 | 2011-04-19 03:48:31 +0000 | [diff] [blame] | 200 | #define MMC_RSP_NONE (0) |
| 201 | #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 202 | #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ |
| 203 | MMC_RSP_BUSY) |
Thomas Chou | abe2c93 | 2011-04-19 03:48:31 +0000 | [diff] [blame] | 204 | #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) |
| 205 | #define MMC_RSP_R3 (MMC_RSP_PRESENT) |
| 206 | #define MMC_RSP_R4 (MMC_RSP_PRESENT) |
| 207 | #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) |
| 208 | #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) |
| 209 | #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 210 | |
Lei Wen | bc897b1 | 2011-05-02 16:26:26 +0000 | [diff] [blame] | 211 | #define MMCPART_NOAVAILABLE (0xff) |
| 212 | #define PART_ACCESS_MASK (0x7) |
| 213 | #define PART_SUPPORT (0x1) |
Oliver Metz | 1937e5a | 2013-10-01 20:32:07 +0200 | [diff] [blame] | 214 | #define PART_ENH_ATTRIB (0x1f) |
wdenk | 71f9511 | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 215 | |
Simon Glass | 8bfa195 | 2013-04-03 08:54:30 +0000 | [diff] [blame] | 216 | /* Maximum block size for MMC */ |
| 217 | #define MMC_MAX_BLOCK_LEN 512 |
| 218 | |
Amar | 3690d6d | 2013-04-27 11:42:58 +0530 | [diff] [blame] | 219 | /* The number of MMC physical partitions. These consist of: |
| 220 | * boot partitions (2), general purpose partitions (4) in MMC v4.4. |
| 221 | */ |
| 222 | #define MMC_NUM_BOOT_PARTITION 2 |
| 223 | |
Andy Fleming | 1de97f9 | 2008-10-30 16:31:39 -0500 | [diff] [blame] | 224 | struct mmc_cid { |
| 225 | unsigned long psn; |
| 226 | unsigned short oid; |
| 227 | unsigned char mid; |
| 228 | unsigned char prv; |
| 229 | unsigned char mdt; |
| 230 | char pnm[7]; |
| 231 | }; |
| 232 | |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 233 | struct mmc_cmd { |
| 234 | ushort cmdidx; |
| 235 | uint resp_type; |
| 236 | uint cmdarg; |
Rabin Vincent | 0b453ff | 2009-04-05 13:30:55 +0530 | [diff] [blame] | 237 | uint response[4]; |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 238 | }; |
| 239 | |
| 240 | struct mmc_data { |
| 241 | union { |
| 242 | char *dest; |
| 243 | const char *src; /* src buffers don't get written to */ |
| 244 | }; |
| 245 | uint flags; |
| 246 | uint blocks; |
| 247 | uint blocksize; |
| 248 | }; |
| 249 | |
| 250 | struct mmc { |
| 251 | struct list_head link; |
| 252 | char name[32]; |
| 253 | void *priv; |
| 254 | uint voltages; |
| 255 | uint version; |
Lei Wen | bc897b1 | 2011-05-02 16:26:26 +0000 | [diff] [blame] | 256 | uint has_init; |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 257 | uint f_min; |
| 258 | uint f_max; |
| 259 | int high_capacity; |
| 260 | uint bus_width; |
| 261 | uint clock; |
| 262 | uint card_caps; |
| 263 | uint host_caps; |
| 264 | uint ocr; |
Markus Niebel | ab71188 | 2013-12-16 13:40:46 +0100 | [diff] [blame] | 265 | uint dsr; |
| 266 | uint dsr_imp; |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 267 | uint scr[2]; |
| 268 | uint csd[4]; |
Rabin Vincent | 0b453ff | 2009-04-05 13:30:55 +0530 | [diff] [blame] | 269 | uint cid[4]; |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 270 | ushort rca; |
Lei Wen | bc897b1 | 2011-05-02 16:26:26 +0000 | [diff] [blame] | 271 | char part_config; |
| 272 | char part_num; |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 273 | uint tran_speed; |
| 274 | uint read_bl_len; |
| 275 | uint write_bl_len; |
Lei Wen | e6f99a5 | 2011-06-22 17:03:31 +0000 | [diff] [blame] | 276 | uint erase_grp_size; |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 277 | u64 capacity; |
Stephen Warren | f866a46 | 2013-06-11 15:14:01 -0600 | [diff] [blame] | 278 | u64 capacity_user; |
| 279 | u64 capacity_boot; |
| 280 | u64 capacity_rpmb; |
| 281 | u64 capacity_gp[4]; |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 282 | block_dev_desc_t block_dev; |
| 283 | int (*send_cmd)(struct mmc *mmc, |
| 284 | struct mmc_cmd *cmd, struct mmc_data *data); |
| 285 | void (*set_ios)(struct mmc *mmc); |
| 286 | int (*init)(struct mmc *mmc); |
Thierry Reding | 48972d9 | 2012-01-02 01:15:37 +0000 | [diff] [blame] | 287 | int (*getcd)(struct mmc *mmc); |
Nikita Kiryanov | d23d8d7 | 2012-12-03 02:19:46 +0000 | [diff] [blame] | 288 | int (*getwp)(struct mmc *mmc); |
Sandeep Paulraj | 57418d2 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 289 | uint b_max; |
Che-Liang Chiou | e955044 | 2012-11-28 15:21:13 +0000 | [diff] [blame] | 290 | char op_cond_pending; /* 1 if we are waiting on an op_cond command */ |
| 291 | char init_in_progress; /* 1 if we have done mmc_start_init() */ |
| 292 | char preinit; /* start init as early as possible */ |
| 293 | uint op_cond_response; /* the response byte from the last op_cond */ |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 294 | }; |
| 295 | |
| 296 | int mmc_register(struct mmc *mmc); |
| 297 | int mmc_initialize(bd_t *bis); |
| 298 | int mmc_init(struct mmc *mmc); |
| 299 | int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); |
Jerry Huang | 4a6ee17 | 2010-11-25 17:06:07 +0000 | [diff] [blame] | 300 | void mmc_set_clock(struct mmc *mmc, uint clock); |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 301 | struct mmc *find_mmc_device(int dev_num); |
Steve Sakoman | 8971696 | 2010-07-01 12:12:42 -0700 | [diff] [blame] | 302 | int mmc_set_dev(int dev_num); |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 303 | void print_mmc_devices(char separator); |
Lei Wen | ea6ebe2 | 2011-05-02 16:26:25 +0000 | [diff] [blame] | 304 | int get_mmc_num(void); |
Thierry Reding | 314284b | 2012-01-02 01:15:36 +0000 | [diff] [blame] | 305 | int board_mmc_getcd(struct mmc *mmc); |
Lei Wen | bc897b1 | 2011-05-02 16:26:26 +0000 | [diff] [blame] | 306 | int mmc_switch_part(int dev_num, unsigned int part_num); |
Thierry Reding | 48972d9 | 2012-01-02 01:15:37 +0000 | [diff] [blame] | 307 | int mmc_getcd(struct mmc *mmc); |
Nikita Kiryanov | d23d8d7 | 2012-12-03 02:19:46 +0000 | [diff] [blame] | 308 | int mmc_getwp(struct mmc *mmc); |
Markus Niebel | ab71188 | 2013-12-16 13:40:46 +0100 | [diff] [blame] | 309 | int mmc_set_dsr(struct mmc *mmc, u16 val); |
Amar | 3690d6d | 2013-04-27 11:42:58 +0530 | [diff] [blame] | 310 | /* Function to change the size of boot partition and rpmb partitions */ |
| 311 | int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, |
| 312 | unsigned long rpmbsize); |
| 313 | /* Function to send commands to open/close the specified boot partition */ |
| 314 | int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access); |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 315 | |
Che-Liang Chiou | e955044 | 2012-11-28 15:21:13 +0000 | [diff] [blame] | 316 | /** |
| 317 | * Start device initialization and return immediately; it does not block on |
| 318 | * polling OCR (operation condition register) status. Then you should call |
| 319 | * mmc_init, which would block on polling OCR status and complete the device |
| 320 | * initializatin. |
| 321 | * |
| 322 | * @param mmc Pointer to a MMC device struct |
| 323 | * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. |
| 324 | */ |
| 325 | int mmc_start_init(struct mmc *mmc); |
| 326 | |
| 327 | /** |
| 328 | * Set preinit flag of mmc device. |
| 329 | * |
| 330 | * This will cause the device to be pre-inited during mmc_initialize(), |
| 331 | * which may save boot time if the device is not accessed until later. |
| 332 | * Some eMMC devices take 200-300ms to init, but unfortunately they |
| 333 | * must be sent a series of commands to even get them to start preparing |
| 334 | * for operation. |
| 335 | * |
| 336 | * @param mmc Pointer to a MMC device struct |
| 337 | * @param preinit preinit flag value |
| 338 | */ |
| 339 | void mmc_set_preinit(struct mmc *mmc, int preinit); |
| 340 | |
Reinhard Meyer | 1592ef8 | 2010-08-13 10:31:06 +0200 | [diff] [blame] | 341 | #ifdef CONFIG_GENERIC_MMC |
Paul Burton | 8687d5c | 2013-09-04 16:12:26 +0100 | [diff] [blame] | 342 | #ifdef CONFIG_MMC_SPI |
Thomas Chou | d52ebf1 | 2010-12-24 13:12:21 +0000 | [diff] [blame] | 343 | #define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI) |
Paul Burton | 8687d5c | 2013-09-04 16:12:26 +0100 | [diff] [blame] | 344 | #else |
| 345 | #define mmc_host_is_spi(mmc) 0 |
| 346 | #endif |
Thomas Chou | d52ebf1 | 2010-12-24 13:12:21 +0000 | [diff] [blame] | 347 | struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); |
Reinhard Meyer | 1592ef8 | 2010-08-13 10:31:06 +0200 | [diff] [blame] | 348 | #else |
Andy Fleming | 272cc70 | 2008-10-30 16:41:01 -0500 | [diff] [blame] | 349 | int mmc_legacy_init(int verbose); |
| 350 | #endif |
Reinhard Meyer | 1592ef8 | 2010-08-13 10:31:06 +0200 | [diff] [blame] | 351 | |
wdenk | 71f9511 | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 352 | #endif /* _MMC_H_ */ |