blob: 3bf22b64705b93bc79988dc060f9078d82537f58 [file] [log] [blame]
Zhimin2fbf7002020-05-29 06:01:04 +08001/******************************************************************************
2*
3* Copyright (c) 2019 Intel.
4*
5* Licensed under the Apache License, Version 2.0 (the "License");
6* you may not use this file except in compliance with the License.
7* You may obtain a copy of the License at
8*
9* http://www.apache.org/licenses/LICENSE-2.0
10*
11* Unless required by applicable law or agreed to in writing, software
12* distributed under the License is distributed on an "AS IS" BASIS,
13* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14* See the License for the specific language governing permissions and
15* limitations under the License.
16*
17*******************************************************************************/
18
19#include <assert.h>
20#include <err.h>
21#include <arpa/inet.h>
22#include <sys/time.h>
23#include <time.h>
24
25#include "common.h"
26#include "xran_fh_o_du.h"
27#include "xran_pkt.h"
28#include "xran_pkt_up.h"
29#include "xran_cp_api.h"
30#include "xran_up_api.h"
31
32#include "xran_mlog_lnx.h"
33
34extern enum app_state state;
35
36int iq_playback_buffer_size_dl = IQ_PLAYBACK_BUFFER_BYTES;
37int iq_playback_buffer_size_ul = IQ_PLAYBACK_BUFFER_BYTES;
38
39int iq_bfw_buffer_size_dl = IQ_PLAYBACK_BUFFER_BYTES;
40int iq_bfw_buffer_size_ul = IQ_PLAYBACK_BUFFER_BYTES;
41
42int iq_srs_buffer_size_ul = IQ_PLAYBACK_BUFFER_BYTES;
43
44uint8_t numCCPorts = 1;
45/* Number of antennas supported by front-end */
46
47uint8_t num_eAxc = 4;
48/* Number of CPRI ports supported by front-end */
49
50int16_t *p_tx_play_buffer[MAX_ANT_CARRIER_SUPPORTED];
51int32_t tx_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
52int32_t tx_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
53
54int16_t *p_tx_prach_play_buffer[MAX_ANT_CARRIER_SUPPORTED];
55int32_t tx_prach_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
56int32_t tx_prach_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
57
58int16_t *p_tx_srs_play_buffer[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
59int32_t tx_srs_play_buffer_size[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
60int32_t tx_srs_play_buffer_position[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
61
62int16_t *p_rx_log_buffer[MAX_ANT_CARRIER_SUPPORTED];
63int32_t rx_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
64int32_t rx_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
65
66int16_t *p_prach_log_buffer[MAX_ANT_CARRIER_SUPPORTED];
67int32_t prach_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
68int32_t prach_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
69
70int16_t *p_srs_log_buffer[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
71int32_t srs_log_buffer_size[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
72int32_t srs_log_buffer_position[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR];
73
74int16_t *p_tx_buffer[MAX_ANT_CARRIER_SUPPORTED];
75int32_t tx_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
76
77int16_t *p_rx_buffer[MAX_ANT_CARRIER_SUPPORTED];
78int32_t rx_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
79
80/* beamforming weights for UL (O-DU) */
81int16_t *p_tx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
82int32_t tx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
83int32_t tx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
84
85/* beamforming weights for UL (O-DU) */
86int16_t *p_tx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
87int32_t tx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
88int32_t tx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
89
90/* beamforming weights for UL (O-RU) */
91int16_t *p_rx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
92int32_t rx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
93int32_t rx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
94
95/* beamforming weights for UL (O-RU) */
96int16_t *p_rx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED];
97int32_t rx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED];
98int32_t rx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED];
99
100// F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
101uint16_t nNumRbsPerSymF1[3][13] =
102{
103 // 5MHz 10MHz 15MHz 20 MHz 25 MHz 30 MHz 40 MHz 50MHz 60 MHz 70 MHz 80 MHz 90 MHz 100 MHz
104 {25, 52, 79, 106, 133, 160, 216, 270, 0, 0, 0, 0, 0}, // Numerology 0 (15KHz)
105 {11, 24, 38, 51, 65, 78, 106, 133, 162, 0, 217, 245, 273}, // Numerology 1 (30KHz)
106 {0, 11, 18, 24, 31, 38, 51, 65, 79, 0, 107, 121, 135} // Numerology 2 (60KHz)
107};
108
109// F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
110uint16_t nNumRbsPerSymF2[2][4] =
111{
112 // 50Mhz 100MHz 200MHz 400MHz
113 {66, 132, 264, 0}, // Numerology 2 (60KHz)
114 {32, 66, 132, 264} // Numerology 3 (120KHz)
115};
116
117// 38.211 - Table 4.2.1
118uint16_t nSubCarrierSpacing[5] =
119{
120 15, // mu = 0
121 30, // mu = 1
122 60, // mu = 2
123 120, // mu = 3
124 240 // mu = 4
125};
126
127// TTI interval in us (slot duration)
128uint16_t nTtiInterval[4] =
129{
130 1000, // mu = 0
131 500, // mu = 1
132 250, // mu = 2
133 125, // mu = 3
134};
135
136
137// F1 Tables 38.101-1 Table F.5.3. Window length for normal CP
138uint16_t nCpSizeF1[3][13][2] =
139{
140 // 5MHz 10MHz 15MHz 20 MHz 25 MHz 30 MHz 40 MHz 50MHz 60 MHz 70 MHz 80 MHz 90 MHz 100 MHz
141 {{40, 36}, {80, 72}, {120, 108}, {160, 144}, {160, 144}, {240, 216}, {320, 288}, {320, 288}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}}, // Numerology 0 (15KHz)
142 {{22, 18}, {44, 36}, {66, 54}, {88, 72}, {88, 72}, {132, 108}, {176, 144}, {176, 144}, {264, 216}, {264, 216}, {352, 288}, {352, 288}, {352, 288}}, // Numerology 1 (30KHz)
143 { {0, 0}, {26, 18}, {39, 27}, {52, 36}, {52, 36}, {78, 54}, {104, 72}, {104, 72}, {156, 108}, {156, 108}, {208, 144}, {208, 144}, {208, 144}}, // Numerology 2 (60KHz)
144};
145
146// F2 Tables 38.101-2 Table F.5.3. Window length for normal CP
147int16_t nCpSizeF2[2][4][2] =
148{
149 // 50Mhz 100MHz 200MHz 400MHz
150 { {0, 0}, {104, 72}, {208, 144}, {416, 288}}, // Numerology 2 (60KHz)
151 {{68, 36}, {136, 72}, {272, 144}, {544, 288}}, // Numerology 3 (120KHz)
152};
153
154uint32_t gMaxSlotNum;
155uint32_t gNumDLCtx;
156uint32_t gNumULCtx;
157uint32_t gDLResetAdvance;
158uint32_t gDLProcAdvance;
159uint32_t gULProcAdvance;
160
161static uint16_t g_NumSlotTDDLoop[XRAN_MAX_SECTOR_NR] = { XRAN_NUM_OF_SLOT_IN_TDD_LOOP };
162static uint16_t g_NumDLSymSp[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0};
163static uint16_t g_NumULSymSp[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0};
164static uint8_t g_SlotType[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{XRAN_SLOT_TYPE_INVALID}};
165float g_UlRate[XRAN_MAX_SECTOR_NR] = {0.0};
166float g_DlRate[XRAN_MAX_SECTOR_NR] = {0.0};
167
168uint32_t app_xran_get_tti_interval(uint8_t nMu)
169{
170 if (nMu < 4)
171 {
172 return nTtiInterval[nMu];
173 }
174 else
175 {
176 printf("ERROR: %s Mu[%d] is not valid\n",__FUNCTION__, nMu);
177 }
178
179 return 0;
180}
181
182uint32_t app_xran_get_scs(uint8_t nMu)
183{
184 if (nMu <= 3)
185 {
186 return nSubCarrierSpacing[nMu];
187 }
188 else
189 {
190 printf("ERROR: %s Mu[%d] is not valid\n",__FUNCTION__, nMu);
191 }
192
193 return 0;
194}
195
196
197
198
199//-------------------------------------------------------------------------------------------
200/** @ingroup group_nr5g_source_phy_common
201 *
202 * @param[in] nNumerology - Numerology determine sub carrier spacing, Value: 0->4 0: 15khz, 1: 30khz, 2: 60khz 3: 120khz, 4: 240khz
203 * @param[in] nBandwidth - Carrier bandwidth for in MHz. Value: 5->400
204 * @param[in] nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000
205 *
206 * @return Number of RBs in cell
207 *
208 * @description
209 * Returns number of RBs based on 38.101-1 and 38.101-2 for the cell
210 *
211**/
212//-------------------------------------------------------------------------------------------
213uint16_t app_xran_get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA)
214{
215 uint32_t error = 1;
216 uint16_t numRBs = 0;
217
218 if (nAbsFrePointA <= 6000000)
219 {
220 // F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
221 if (nNumerology < 3)
222 {
223 switch(nBandwidth)
224 {
225 case PHY_BW_5_0_MHZ:
226 numRBs = nNumRbsPerSymF1[nNumerology][0];
227 error = 0;
228 break;
229 case PHY_BW_10_0_MHZ:
230 numRBs = nNumRbsPerSymF1[nNumerology][1];
231 error = 0;
232 break;
233 case PHY_BW_15_0_MHZ:
234 numRBs = nNumRbsPerSymF1[nNumerology][2];
235 error = 0;
236 break;
237 case PHY_BW_20_0_MHZ:
238 numRBs = nNumRbsPerSymF1[nNumerology][3];
239 error = 0;
240 break;
241 case PHY_BW_25_0_MHZ:
242 numRBs = nNumRbsPerSymF1[nNumerology][4];
243 error = 0;
244 break;
245 case PHY_BW_30_0_MHZ:
246 numRBs = nNumRbsPerSymF1[nNumerology][5];
247 error = 0;
248 break;
249 case PHY_BW_40_0_MHZ:
250 numRBs = nNumRbsPerSymF1[nNumerology][6];
251 error = 0;
252 break;
253 case PHY_BW_50_0_MHZ:
254 numRBs = nNumRbsPerSymF1[nNumerology][7];
255 error = 0;
256 break;
257 case PHY_BW_60_0_MHZ:
258 numRBs = nNumRbsPerSymF1[nNumerology][8];
259 error = 0;
260 break;
261 case PHY_BW_70_0_MHZ:
262 numRBs = nNumRbsPerSymF1[nNumerology][9];
263 error = 0;
264 break;
265 case PHY_BW_80_0_MHZ:
266 numRBs = nNumRbsPerSymF1[nNumerology][10];
267 error = 0;
268 break;
269 case PHY_BW_90_0_MHZ:
270 numRBs = nNumRbsPerSymF1[nNumerology][11];
271 error = 0;
272 break;
273 case PHY_BW_100_0_MHZ:
274 numRBs = nNumRbsPerSymF1[nNumerology][12];
275 error = 0;
276 break;
277 default:
278 error = 1;
279 break;
280 }
281 }
282 }
283 else
284 {
285 if ((nNumerology >= 2) && (nNumerology <= 3))
286 {
287 // F2 Tables 38.101-2 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB
288 switch(nBandwidth)
289 {
290 case PHY_BW_50_0_MHZ:
291 numRBs = nNumRbsPerSymF2[nNumerology-2][0];
292 error = 0;
293 break;
294 case PHY_BW_100_0_MHZ:
295 numRBs = nNumRbsPerSymF2[nNumerology-2][1];
296 error = 0;
297 break;
298 case PHY_BW_200_0_MHZ:
299 numRBs = nNumRbsPerSymF2[nNumerology-2][2];
300 error = 0;
301 break;
302 case PHY_BW_400_0_MHZ:
303 numRBs = nNumRbsPerSymF2[nNumerology-2][3];
304 error = 0;
305 break;
306 default:
307 error = 1;
308 break;
309 }
310 }
311 }
312
313
314 if (error)
315 {
316 printf("ERROR: %s: nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d]\n",__FUNCTION__, nNumerology, nBandwidth, nAbsFrePointA);
317 }
318 else
319 {
320 printf("%s: nNumerology[%d] nBandwidth[%d] nAbsFrePointA[%d] numRBs[%d]\n",__FUNCTION__, nNumerology, nBandwidth, nAbsFrePointA, numRBs);
321 }
322
323 return numRBs;
324}
325
326//-------------------------------------------------------------------------------------------
327/** @ingroup phy_cal_nrarfcn
328 *
329 * @param[in] center frequency
330 *
331 * @return NR-ARFCN
332 *
333 * @description
334 * This calculates NR-ARFCN value according to center frequency
335 *
336**/
337//-------------------------------------------------------------------------------------------
338uint32_t app_xran_cal_nrarfcn(uint32_t nCenterFreq)
339{
340 uint32_t nDeltaFglobal,nFoffs,nNoffs;
341 uint32_t nNRARFCN = 0;
342
343 if(nCenterFreq > 0 && nCenterFreq < 3000*1000)
344 {
345 nDeltaFglobal = 5;
346 nFoffs = 0;
347 nNoffs = 0;
348 }
349 else if(nCenterFreq >= 3000*1000 && nCenterFreq < 24250*1000)
350 {
351 nDeltaFglobal = 15;
352 nFoffs = 3000*1000;
353 nNoffs = 600000;
354 }
355 else if(nCenterFreq >= 24250*1000 && nCenterFreq <= 100000*1000)
356 {
357 nDeltaFglobal = 60;
358 nFoffs = 24250080;
359 nNoffs = 2016667;
360 }
361 else
362 {
363 printf("@@@@ incorrect center frerquency %d\n",nCenterFreq);
364 return (0);
365 }
366
367 nNRARFCN = ((nCenterFreq - nFoffs)/nDeltaFglobal) + nNoffs;
368
369 printf("%s: nCenterFreq[%d] nDeltaFglobal[%d] nFoffs[%d] nNoffs[%d] nNRARFCN[%d]\n", __FUNCTION__, nCenterFreq, nDeltaFglobal, nFoffs, nNoffs, nNRARFCN);
370 return (nNRARFCN);
371}
372
373int32_t app_xran_slot_limit(int32_t nSfIdx)
374{
375 while (nSfIdx < 0) {
376 nSfIdx += gMaxSlotNum;
377 }
378
379 while (nSfIdx >= gMaxSlotNum) {
380 nSfIdx -= gMaxSlotNum;
381 }
382
383 return nSfIdx;
384}
385
386void app_xran_clear_slot_type(uint32_t nPhyInstanceId)
387{
388 g_UlRate[nPhyInstanceId] = 0.0;
389 g_DlRate[nPhyInstanceId] = 0.0;
390 g_NumSlotTDDLoop[nPhyInstanceId] = 1;
391}
392
393int32_t app_xran_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType, uint32_t nTddPeriod, struct xran_slot_config *psSlotConfig)
394{
395 uint32_t nSlotNum, nSymNum, nVal, i;
396 uint32_t numDlSym, numUlSym, numGuardSym;
397 uint32_t numDlSlots = 0, numUlSlots = 0, numSpDlSlots = 0, numSpUlSlots = 0, numSpSlots = 0;
398 char sSlotPattern[XRAN_SLOT_TYPE_LAST][10] = {"IN\0", "DL\0", "UL\0", "SP\0", "FD\0"};
399
400 // nPhyInstanceId Carrier ID
401 // nFrameDuplexType 0 = FDD 1 = TDD
402 // nTddPeriod Tdd Periodicity
403 // psSlotConfig[80] Slot Config Structure for nTddPeriod Slots
404
405 g_UlRate[nPhyInstanceId] = 0.0;
406 g_DlRate[nPhyInstanceId] = 0.0;
407 g_NumSlotTDDLoop[nPhyInstanceId] = nTddPeriod;
408
409 for (i = 0; i < XRAN_NUM_OF_SLOT_IN_TDD_LOOP; i++)
410 {
411 g_SlotType[nPhyInstanceId][i] = XRAN_SLOT_TYPE_INVALID;
412 g_NumDLSymSp[nPhyInstanceId][i] = 0;
413 g_NumULSymSp[nPhyInstanceId][i] = 0;
414 }
415
416 if (nFrameDuplexType == XRAN_FDD)
417 {
418 for (i = 0; i < XRAN_NUM_OF_SLOT_IN_TDD_LOOP; i++)
419 {
420 g_SlotType[nPhyInstanceId][i] = XRAN_SLOT_TYPE_FDD;
421 }
422 g_NumSlotTDDLoop[nPhyInstanceId] = 1;
423 g_DlRate[nPhyInstanceId] = 1.0;
424 g_UlRate[nPhyInstanceId] = 1.0;
425 }
426 else
427 {
428 for (nSlotNum = 0; nSlotNum < nTddPeriod; nSlotNum++)
429 {
430 numDlSym = 0;
431 numUlSym = 0;
432 numGuardSym = 0;
433 for (nSymNum = 0; nSymNum < XRAN_NUM_OF_SYMBOL_PER_SLOT; nSymNum++)
434 {
435 switch(psSlotConfig[nSlotNum].nSymbolType[nSymNum])
436 {
437 case XRAN_SYMBOL_TYPE_DL:
438 numDlSym++;
439 break;
440 case XRAN_SYMBOL_TYPE_GUARD:
441 numGuardSym++;
442 break;
443 default:
444 numUlSym++;
445 break;
446 }
447 }
448
449 // printf("nSlotNum[%d] : numDlSym[%d] numGuardSym[%d] numUlSym[%d]\n", nSlotNum, numDlSym, numGuardSym, numUlSym);
450
451 if ((numUlSym == 0) && (numGuardSym == 0))
452 {
453 g_SlotType[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_DL;
454 numDlSlots++;
455 }
456 else if ((numDlSym == 0) && (numGuardSym == 0))
457 {
458 g_SlotType[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_UL;
459 numUlSlots++;
460 }
461 else
462 {
463 g_SlotType[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_SP;
464 numSpSlots++;
465
466 if (numDlSym)
467 {
468 numSpDlSlots++;
469 g_NumDLSymSp[nPhyInstanceId][nSlotNum] = numDlSym;
470 }
471 if (numUlSym)
472 {
473 numSpUlSlots++;
474 g_NumULSymSp[nPhyInstanceId][nSlotNum] = numUlSym;
475 }
476 }
477
478 // printf(" numDlSlots[%d] numUlSlots[%d] numSpSlots[%d] numSpDlSlots[%d] numSpUlSlots[%d]\n", numDlSlots, numUlSlots, numSpSlots, numSpDlSlots, numSpUlSlots);
479 }
480
481 g_DlRate[nPhyInstanceId] = (float)(numDlSlots + numSpDlSlots) / (float)nTddPeriod;
482 g_UlRate[nPhyInstanceId] = (float)(numUlSlots + numSpUlSlots) / (float)nTddPeriod;
483 }
484
485 printf("set_slot_type: nPhyInstanceId[%d] nFrameDuplexType[%d], nTddPeriod[%d]\n",
486 nPhyInstanceId, nFrameDuplexType, nTddPeriod);
487
488 printf("DLRate[%f] ULRate[%f]\n", g_DlRate[nPhyInstanceId], g_UlRate[nPhyInstanceId]);
489
490 nVal = (g_NumSlotTDDLoop[nPhyInstanceId] < 10) ? g_NumSlotTDDLoop[nPhyInstanceId] : 10;
491
492 printf("SlotPattern:\n");
493 printf("Slot: ");
494 for (nSlotNum = 0; nSlotNum < nVal; nSlotNum++)
495 {
496 printf("%d ", nSlotNum);
497 }
498 printf("\n");
499
500 printf(" %3d ", 0);
501 for (nSlotNum = 0, i = 0; nSlotNum < g_NumSlotTDDLoop[nPhyInstanceId]; nSlotNum++)
502 {
503 printf("%s ", sSlotPattern[g_SlotType[nPhyInstanceId][nSlotNum]]);
504 i++;
505 if ((i == 10) && ((nSlotNum+1) < g_NumSlotTDDLoop[nPhyInstanceId]))
506 {
507 printf("\n");
508 printf(" %3d ", nSlotNum);
509 i = 0;
510 }
511 }
512 printf("\n\n");
513
514 return 0;
515}
516
517int32_t app_xran_get_slot_type(int32_t nCellIdx, int32_t nSlotdx, int32_t nType)
518{
519 int32_t nSfIdxMod, nSfType, ret = 0;
520
521 nSfIdxMod = app_xran_slot_limit(nSlotdx) % ((g_NumSlotTDDLoop[nCellIdx] > 0) ? g_NumSlotTDDLoop[nCellIdx]: 1);
522 nSfType = g_SlotType[nCellIdx][nSfIdxMod];
523
524 if (nSfType == nType)
525 {
526 ret = 1;
527 }
528 else if (nSfType == XRAN_SLOT_TYPE_SP)
529 {
530 if ((nType == XRAN_SLOT_TYPE_DL) && g_NumDLSymSp[nCellIdx][nSfIdxMod])
531 {
532 ret = 1;
533 }
534
535 if ((nType == XRAN_SLOT_TYPE_UL) && g_NumULSymSp[nCellIdx][nSfIdxMod])
536 {
537 ret = 1;
538 }
539 }
540 else if (nSfType == XRAN_SLOT_TYPE_FDD)
541 {
542 ret = 1;
543 }
544
545 return ret;
546}
547
548
549
550void sys_save_buf_to_file(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num)
551{
552 if (size)
553 {
554 if (filename && bufname)
555 {
556 FILE *file;
557 printf("Storing %s to file %s: ", bufname, filename);
558 file = fopen(filename, "wb");
559 if (file == NULL)
560 {
561 printf("can't open file %s!!!", filename);
562 }
563 else
564 {
565 uint32_t num;
566 num = fwrite(pBuffer, buffers_num, size, file);
567 fflush(file);
568 fclose(file);
569 printf("from addr (0x%lx) size (%d) bytes num (%d)", (uint64_t)pBuffer, size, num);
570 }
571 printf(" \n");
572 }
573 else
574 {
575 printf(" the file name, buffer name are not set!!!");
576 }
577 }
578 else
579 {
580 printf(" the %s is free: size = %d bytes!!!", bufname, size);
581 }
582}
583
584int sys_load_file_to_buff(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num)
585{
586 unsigned int file_size = 0;
587 int num= 0;
588
589 if (size)
590 {
591 if (filename && bufname)
592 {
593 FILE *file;
594 printf("Loading file %s to %s: ", filename, bufname);
595 file = fopen(filename, "rb");
596
597
598 if (file == NULL)
599 {
600 printf("can't open file %s!!!", filename);
601 exit(-1);
602 }
603 else
604 {
605 fseek(file, 0, SEEK_END);
606 file_size = ftell(file);
607 fseek(file, 0, SEEK_SET);
608
609 if ((file_size > size) || (file_size == 0))
610 file_size = size;
611
612 printf("Reading IQ samples from file: File Size: %d [Buffer Size: %d]\n", file_size, size);
613
614 num = fread(pBuffer, buffers_num, size, file);
615 fflush(file);
616 fclose(file);
617 printf("from addr (0x%lx) size (%d) bytes num (%d)", (uint64_t)pBuffer, file_size, num);
618 }
619 printf(" \n");
620
621 }
622 else
623 {
624 printf(" the file name, buffer name are not set!!!");
625 }
626 }
627 else
628 {
629 printf(" the %s is free: size = %d bytes!!!", bufname, size);
630 }
631 return num;
632}
633
634
635void sys_save_buf_to_file_txt(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num)
636{
637 unsigned int i;
638 int ret = 0;
639 if (pBuffer == NULL)
640 return;
641
642 if (size)
643 {
644 if (filename && bufname)
645 {
646 FILE *file;
647 printf("Storing %s to file %s: ", bufname, filename);
648 file = fopen(filename, "w");
649 if (file == NULL)
650 {
651 printf("can't open file %s!!!", filename);
652 exit(-1);
653 }
654 else
655 {
656 uint32_t num = 0;
657
658 signed short *ptr = (signed short*)pBuffer;
659 for (i = 0; i < (size/((unsigned int)sizeof(signed short) /** 2 * 2 * 2*/)); i = i + 2)
660 {
661#ifndef CSCOPE_DEBUG
662 ret = fprintf(file,"%d %d\n", ptr[i], ptr[i + 1]);
663#else
664 ret = fprintf(file,"%d %d ", ptr[i], ptr[i + 1]);
665 /* I data => Ramp data, from 1 to 792.
666 Q data => Contains time information of the current symbol:
667 Bits [15:14] = Antenna-ID
668 Bits [13:12] = “00”
669 Bits [11:8] = Subframe-ID
670 Bits [7:4] = Slot-ID
671 Bits [3:0] = Symbol-ID */
672 fprintf(file, "0x%04x: ant %d Subframe-ID %d Slot-ID %d Symbol-ID %d\n",
673 ptr[i + 1], (ptr[i + 1]>>14) & 0x3, (ptr[i + 1]>>8) & 0xF, (ptr[i + 1]>>4) & 0xF, (ptr[i + 1]>>0) & 0xF);
674#endif
675 if (ret < 0)
676 {
677 printf("fprintf %d\n", ret);
678 fclose(file);
679 break;
680 }
681 num++;
682 }
683 fflush(file);
684 fclose(file);
685 printf("from addr (0x%lx) size (%d) IQ num (%d)", (uint64_t)pBuffer, size, num);
686 }
687 printf(" \n");
688 }
689 else
690 {
691 printf(" the file name, buffer name are not set!!!");
692 }
693 }
694 else
695 {
696 printf(" the %s is free: size = %d bytes!!!", bufname, size);
697 }
698}
699